Machine Instructions1[1].pdf

Machine Instructions and Addressing Modes  Computer Architect and Computer Programmer Generic Computer Embedded Systems MM Microprocessor...

Machine Instructions and Addressing Modes  Computer Architect and Computer Programmer Generic Computer Embedded Systems MM Microprocessor 100 200 What a System will do? 300 Hardware (Component) CU Programmer Designer R1 R2 R3 Instructions Sets OR Machine Instructions R4 * Instructions : Set of bits M OPCODE Operands ADD SUB ALU INR  Types of CPU organization Single accumulator organization MM General register organization 100 Stack organization CU AC M OPCODE Operands ADD SUB ALU INR  Types of CPU organization Single accumulator organization (1 AI) MM General register organization (2 or 3 AI) Stack organization (0 AI except PUSH and POP) PUSH X, PUSH Y, ADD 100 CU R1 R2 R3 M OPCODE Operands ADD SUB ALU INR Instruction Comment SUB Y, A, B Y¬A–B MPY T, D, E T¬D´E ADD T, T, C T¬T+C DIV Y, Y, T Y¬Y÷T Instruction Comment (a) Three-address instructions LOAD D AC ¬ D MPY E AC ¬ AC ´ E Instruction Comment ADD C AC ¬ AC + C MOVE Y, A Y¬A STOR Y Y ¬ AC SUB Y, B Y¬Y–B LOAD A AC ¬ A MOVE T, D T¬D SUB B AC ¬ AC – B MPY T, E T¬T´E DIV Y AC ¬ AC ÷ Y ADD T, C T¬T+C STOR Y Y ¬ AC DIV Y, T Y¬Y÷T (b) Two-address instructions (c) One-address instructions A- B Figure 12.3 Programs to Execute Y= C+ (D´ E)  Advantages of Addressing Modes To give programmers facilities such as pointers (EA), counters for loop control, indexing of data and program relocation. To reduce the number of bits in the addressing field of the instructions. AC = AC + 2 1 K * 16 (10 Bits) MM 0 1023 16 Registers – 4 bits Addressing Modes Implied Immediate Register Register Indirect Direct Indirect Relative  The operand is specified with in the instruction. Operand itself is provided in the instruction rather than its address  The operand is specified with in one of the processor register. Instruction specifies the register in which the operand is stored.  The instruction specifies the register in which the memory address of operand is placed. It do not specify the operand itself but its location within the memory where operand is placed The instruction specifies the direct address of the operand. The memory address is specified where the actual operand is. “Absolute Mode” The instruction specifies the indirect address where the effective address of the operand is placed. The memory address is specified where the actual address of operand is placed. In relative addressing mode, contents of Program Counter PC is added to address part of instruction to obtain effective address. The address part of the instruction is called as offset and it can +ve or –ve. When the offset is added to the PC the resultant number is the memory location where the operand will be placed.  In index addressing mode, contents of Index register is added to address part of instruction to obtain effective address. The address part of instruction holds the beginning/base address and is called as base. The index register hold the index value, which is +ve. Base remains same, the index changes. When the base is added to the index register the resultant number is the memory location where the operand will be placed. In base register addressing mode, contents of base register is added to address part of instruction to obtain effective address. It is similar to the indexed addressing mode except the register now is called as base instead of index. The base register hold the beginning/base address. The address part of instruction holds the offset. Offset remains same, the base changes. When the offset is added to the base register the resultant number is the memory location where the operand will be placed  DIY Implied Mode Auto Increment OR Auto Decrement Mode Stack Mode Displacement Mode  Basic Addressing Modes Mode Algorithm Principal Advantage Principal Disadvantage Immediate Operand = A No memory reference Limited operand magnitude Direct EA = A Simple Limited address space Indirect EA = (A) Large address space Multiple memory references Register EA = R No memory reference Limited address space Register indirect EA = (R) Large address space Extra memory reference Displacement EA = A + (R) Flexibility Complexity Stack EA = top of stack No memory reference Limited applicability  Indirect Addressing Loops Immediate Addressing Pointers Auto Decrement Addressing Constants ❑ An absolute addressing mode: a. The operand is inside the instruction b. The address of the operand is inside the instruction c. The register containing the address of the operand is specified in the instruction d. Location of the operand is implicit ❑ Which of the following addressing modes are suitable for program relocation at run time: 1. Absolute addressing 2. Based Addressing 3. Relative Addressing 4. Indirect Addressing a. 1 and 4 b. 1 and 2 c. 2 and 3 d. 1, 2 and 4  Indirect Addressing Array implementation Indexed Addressing Writing absolute code Base Register Addressing Passing array as parameter  Type of Instructions Data Program Data Transfer Manipulation Control Instructions Instructions Instructions MM Arithmetic Decision (If, for, while) Operations Logical Operations Shift Operations R1 R2-I/O R3  Type of Instructions Data Program Data Transfer Manipulation Control Instructions Instructions Instructions Load Store Exchange Input Output PUSH POP  Type of Instructions Data Program Data Transfer Manipulation Control Instructions Instructions Instructions Increment Decrement Add Subtract Multiply Divide Add with Carry Subtract with Borrow Negate Clear Complement AND OR Exclusive OR Clear Carry Set Carry Complement Carry Enable/Disable Interrupt  Type of Instructions Data Program Data Transfer Manipulation Control Instructions Instructions Instructions Logical Shift Right Logical Shift Left Arithmetic Shift Right Arithmetic shift Left Rotate right Rorate Left Rotate Right through Carry Rotate Left through Carry  Type of Instructions Data Program Data Transfer Manipulation Control Instructions Instructions Instructions Branch Jump Call Return Skip Compare Test  Type of Instructions Data Program Data Transfer Manipulation Control Instructions Instructions Instructions Branch Jump Call Return Skip Compare Test  Type of Instructions Data Program Data Transfer Manipulation Control Instructions Instructions Instructions Branch Jump Call Return Skip Compare Test  Type of Instructions Data Program Data Transfer Manipulation Control Instructions Instructions Instructions Branch Jump Call Return Skip Compare Test  Type of Instructions Data Program Data Transfer Manipulation Control Instructions Instructions Instructions Branch Jump Call Return Skip Compare Test  Type of Instructions Data Program Data Transfer Manipulation Control Instructions Instructions Instructions Branch Jump Call Return Skip Compare Test  Type of Instructions Data Program Data Transfer Manipulation Control Instructions Instructions Instructions Branch Jump Call Return Skip Compare Test  Call and Return ✓ Register ✓ Subroutine ✓ Fixed Memory Location ✓ Memory Stack PC 1000 101 MM 1000 AB SP 100 Call Subroutine 101 Return 101 Return AB+1 200 201 M[SP] = PC SP++ Context PC=EA  Subroutine Interrupt Transfer of control is initiated by ‘Call’ instructions It is initiated because of a signal generated Interrupt External (I/O, Timer, Power Supply) Flag Internal (Divide by 0, Register overflow, Protection, Recursion Stack overflow) Software (User to System calls) ‘PC’ is saved on the stack ‘PC’, ‘PSW’  CISC A large number of instructions Some instructions that perform specialized tasks and are used infrequently Large number of addressing modes Variable length instruction formats Instructions thar manipulate operands in memory RISC Relatively few instructions Relatively few addressing modes Memory access is limited to load and store instructions All operations are done within the registers of the CPU Single cycle instruction execution Fixed length, easily decoded instruction format Hardwired rather than microprogrammed control  x86 Addressing Modes Mode Algorithm Immediate Operand = A Register Operand LA = R Displacement LA = (SR) + A Base LA = (SR) + (B) Base with Displacement LA = (SR) + (B) + A Scaled Index with Displacement LA = (SR) + (I) ´ S + A Base with Index and Displacement LA = (SR) + (B) + (I) + A Base with Scaled Index and Displacement LA = (SR) + (I) ´ S + (B) + A Relative LA = (PC) + A LA = linear address (X) = contents of X SR = segment register PC = program counter A = contents of an address field in the instruction R = register B = base register I = index register S = scaling factor