Unit 2.pdf

Department of Computer Engineering Unit-2 Basic Computer Organization and Computer Organization and Design Architecture- 01CE140...

Department of Computer Engineering Unit-2 Basic Computer Organization and Computer Organization and Design Architecture- 01CE1402 Prof. Kishan Makadiya  ▪ Instruction codes ▪ Computer registers ▪ Computer instructions ▪ Timing and Control ▪ Instruction cycle Outline ▪ Memory-Reference Instructions ▪ Input- output and interrupt ▪ Complete description ▪ Design of Basic Computer ▪ Design of Accumulator Logic  ▪ Program  A program is a set of instructions that specify the operations, operands and the sequence by which processing has to occur. ▪ Computer Instruction  A computer instruction is a binary code that specifies a sequence of Instruction microoperations for the computer.  The computer reads each instruction from memory and places it in Codes a control register.  The control then interprets the binary code of the instruction and proceeds to execute it by issuing a sequence of microoperations.  ▪ Instruction Code  An instruction code is a group of bits that instruct the computer to perform a specific operation.  Example Unique Binary code is assigned Instruction ADD 1547 to every OpCode Codes ▪ Operation Code (Opcode)  The operation code of an instruction is a group of bits that define such operations as add, subtract, multiply, shift, and complement.  The number of bits required for the operation code of an instruction depends on the total number of operations available in the computer.  The operation code must consist of at least n bits for a given 2n (or less) distinct operations.  Memory 4096 x 16 15 12 11 0 Opcode Address Instructions Stored Instruction Format (program) Program 15 0 Operand Organization (data) Binary Operand Processor Register (accumulator or AC)  ▪ The simplest way to organize a computer is to have one processor register(AC) and an instruction code format with two parts. ▪ The first part specifies the operation (opcode) to be Stored performed and the second specifies an address (operand). Program ▪ The memory address tells the control where to find an Organization operand in memory. ▪ This operand is read from memory and used as the data to be operated on together with the data stored in the processor register.  ▪ Instructions are stored in one section of memory and data in another. ▪ For a memory unit with 4096 words, we need 12 bits to specify an address since 212 = 4096. Stored ▪ If we store each instruction code in one 16-bit memory Program word, we have available four bits for operation code Organization (opcode) to specify one out of 16 possible operations, and 12 bits to specify the address of an operand.  ▪ The control reads a 16-bit instruction from the program portion of memory. ▪ It uses the 12-bit address part of the instruction to read a 16-bit operand from the data portion of memory. Stored ▪ It then executes the operation specified by the operation Program code. Organization  Instruction Format 15 14 12 11 0 I Opcode Address Instruction format of basic computer 0 0 0 1 0 1 0 0 0 1 0 1 0 1 1 1 Add Instruction – ADD 457  Memory Memory 22 0 ADD 457 35 1 ADD 300 300 1350 Direct & 457 Operand Indirect 1350 Operand Addressing of Memory + + AC AC Direct Address Indirect Address  ▪ If the second part of an instruction format specifies the address of an operand, the instruction is said to have a direct address. ▪ In Indirect address, the bits in the second part of the Direct & instruction designate an address of a memory word in Indirect which the address of the operand is found. Addressing of Memory  ▪ One bit of the instruction code can be used to distinguish between a direct and an indirect address. ▪ It consists of a 3-bit operation code, a 12-bit address, and an indirect address mode bit designated by I. Direct & ▪ The mode bit is 0 for a direct address and 1 for an indirect Indirect address. Addressing of Memory  15 14 12 11 0 22 0 ADD 457 ▪ A direct address instruction is placed at address 22 in Direct & memory. Indirect ▪ The I bit is 0, so the instruction is recognized as a direct Addressing of address instruction. Memory ▪ The opcode specifies an ADD instruction, and the address part is the binary equivalent of 457. ▪ The control finds the operand in memory at address 457 and adds it to the content of AC.  15 14 12 11 0 35 1 ADD 300 ▪ The instruction in address 35 has a mode bit I = 1, Direct & recognized as an indirect address instruction. Indirect ▪ The address part is the binary equivalent of 300. Addressing of ▪ The control goes to address 300 to find the address of the Memory operand. ▪ The address of the operand in this case is 1350. ▪ The operand found in address 1350 is then added to the content of AC.  ▪ The indirect address instruction needs two references to memory to fetch an operand. ▪ The first reference is needed to read the address of the operand. Direct & ▪ Second reference is for the operand itself. Indirect ▪ The memory word that holds the address of the operand in Addressing of an indirect address instruction is used as a pointer to an Memory array of data.  11 0 Program Counter(12) PC Holds address of instruction 11 0 Address Register(12) AR Holds address for memory Computer 15 0 Instruction Register(16) Registers IR Holds instruction code 15 0 Temporary Register(16) TR Holds temporary data 15 0 Data Register(16) DR Holds memory operand  15 0 Accumulator(16) AC Processor Register 7 0 Output Register(8) OUTR Holds output character Computer 7 0 Registers Input Register(8) INPR Holds input character Memory 4096 words 16 bits per word  ▪ Common bus Common bus system of basic computer  S2 S1 Bus Memory S0 4096 x 16 7 Address Write Read AR 1 LD INR CLR PC 2 LD INR CLR DR 3 LD INR CLR Adder E & AC 4 Logic LD INR CLR INPR IR 5 LD TR 6 LD INR CLR OUTR Clock LD  1. Memory Reference Instruction 15 14 12 11 0 1 Opcode Address Types of Computer 2. Register Reference Instruction Instructions 15 14 13 12 11 0 0 1 1 1 Register Operation 3. Input – Output Instruction 15 14 13 12 11 0 1 1 1 1 I/O Operation  1. Memory Reference Instruction 15 14 12 11 0 I Opcode Address Types of 01 01 01 01 Address Computer 0xxx 8xxx AND AND the content of memory to AC Instructions 1xxx 9xxx ADD Add the content of memory to AC 2xxx Axxx LDA Load memory word to AC 3xxx Bxxx STA Store content of AC in memory 4xxx Cxxx BUN Branch unconditionally 5xxx Dxxx BSA Branch and save return address 6xxx Exxx ISZ Increment and skip if zero  2. Register Reference Instruction 15 14 13 12 11 0 0 1 1 1 Register Operation 0 1 1 1 01 10 01 1 0 01 1 0 01 0 0 0 0 0 Types of Computer 7800 CLA Clear AC Instructions 7400 CLE Clear E 7200 CMA Complement AC 7100 CME Complement E 7080 CIR Circulate right AC and E 7040 CIL Circulate left AC and E 7020 INC Increment AC  2. Register Reference Instruction 15 14 13 12 11 0 0 1 1 1 Register Operation 0 1 1 1 0 0 0 0 0 0 0 1 0 01 01 01 01 Types of Computer 7010 SPA Skip next instruction if AC is positive Instructions 7008 SNA Skip next instruction if AC is negative 7004 SZA Skip next instruction if AC is zero 7002 SZE Skip next instruction if E is zero 7001 HLT Halt computer  3. Input – Output Instruction 15 14 13 12 11 0 1 1 1 1 I/O Operation 1 1 1 1 01 01 01 01 01 01 0 0 0 0 0 0 Types of Computer F800 INP Input character to AC Instructions F400 OUT Output character from AC F200 SKI Skip on input flag F100 SKO Skip on output flag F080 ION Interrupt on F040 IOF Interrupt off  ▪ Instruction set is said to be complete if it includes sufficient number of instructions in each of the following categories: 1. Arithmetic, logical and shift instructions 2. Instructions for moving information to and from memory and processor registers Instruction Set 3. Program control instructions together with instructions that check status conditions Completeness 4. Input and output instructions  0 0 0 Instruction 1 0 Register 100010101 1 1 Other inputs 15 14 13 12 11 - 0 0 0 0 1 3x8 Decoder Control Unit of 7 6 5 4 3 2 1 0 D0 Control Control Basic I D1 D7 Logic O/p Computer Gates T15 T0 15 14... 2 1 0 4 x 16 Decoder 4-bit sequence Increment (INR) Clear (CLR) counter (SC) Clock  ▪ Components of Control unit are 1. Two decoders 2. A sequence counter 3. Control logic gates ▪ An instruction read from memory is placed in the instruction register (IR). Control Unit ▪ In control unit the IR is divided into three parts: I bit, the operation code (12-14)bit, and bits 0 through 11. ▪ The operation code in bits 12 through 14 are decoded with a 3 x 8 decoder. ▪ Bit-15 of the instruction is transferred to a flip-flop designated by the symbol I.  ▪ The eight outputs of the decoder are designated by the symbols D0 through D7. ▪ Bits 0 through 11 are applied to the control logic gates. ▪ The 4‐bit sequence counter can count in binary from 0 through 15. The outputs of counter are decoded into 16 timing signals T0 through T15. Control Unit ▪ The sequence counter SC can be incremented or cleared synchronously. ▪ Most of the time, the counter is incremented to provide the sequence of timing signals out of 4 X 16 decoder. ▪ Once in awhile, the counter is cleared to 0, causing the next timing signal to be T0.  ▪ As an example, consider the case where SC is incremented to provide timing signals T0, T1, T2, T3 and T4 in sequence. At time T4, SC is cleared to 0 if decoder output D3 is active. This is expressed symbolically by the statement D3T4: SC ← 0 ▪ Initially, the CLR input of SC is active. ▪ The first positive transition of the clock clears SC to 0, which in turn activates the timing T0 out of the decoder. Control Unit ▪ T0 is active during one clock cycle. ▪ The positive clock transition labeled T0 in the diagram will trigger only those registers whose control inputs are connected to timing signal T0. ▪ SC is incremented with every positive clock transition, unless its CLR input is active. ▪ This procedures the sequence of timing signals T0, T1, T2, T3 and T4, and so on. If SC is not cleared, the timing signals will continue with T5, T6, up to T15 and back to T0.  𝑇0 𝑇1 𝑇2 𝑇3 𝑇4 𝑇5 Clock 𝑇0 𝑇1 Timing Cycle for 𝑇2 D3T4: SC ← 0 𝑇3 𝑇4 𝐷3 CLR SC  ▪ The last three waveforms shows how SC is cleared when D3T4 = 1. ▪ Output D3 from the operation decoder becomes active at the end of timing signal T2. ▪ When timing signal T4 becomes active, the output of the AND gate that implements the control function D3T4 becomes active. Control Unit ▪ This signal is applied to the CLR input of SC. ▪ On the next positive clock transition the counter is cleared to 0. ▪ This causes the timing signal T0 to become active instead of T5 that would have been active if SC were incremented instead of cleared.  ▪ Hardwired Control  The control logic is implemented with gates, flips-flops, decoders and other digital circuits.  It can be optimized to produce a fast mode of operation.  It requires changes in the wiring among the various components if Control the design has to be modified or changed. ▪ Microprogrammed Control Organization  The control information is stored in a control memory.  The control memory is programmed to initiate the required sequence of micro-operations.  Any required changes or modifications can be done by updating the microprogram in control memory.  ▪ A program residing in the memory unit of the computer consists of a sequence of instructions. In the basic computer each instruction cycle consists of the following phases: 1. Fetch an instruction from memory. 2. Decode the instruction. Instruction 3. Read the effective address from memory if the instruction has an indirect address. Cycle 4. Execute the instruction. ▪ After step 4, the control goes back to step 1 to fetch, decode and execute the next instruction. ▪ This process continues unless a HALT instruction is encountered.  ▪ Fetch & Decode  PC is loaded with the address of the first instruction in the program.  The micro-operations for fetch and decode phases are as follows: 𝑇0 ∶ 𝐴𝑅 ← 𝑃𝐶 Instruction 𝑇1 ∶ 𝐼𝑅 ← 𝑀 𝐴𝑅 , 𝑃𝐶 ← 𝑃𝐶 + 1 Cycle 𝑇2 ∶ 𝐷0 , … , 𝐷7 ← 𝐷𝑒𝑐𝑜𝑑𝑒 𝐼𝑅 12 − 14 , 𝐴𝑅 ← 𝐼𝑅 0 − 11 , 𝐼 ← 𝐼𝑅(15)  ▪ Determine the type of instruction  During time 𝑇3 , the control unit determines the type of instruction i.e. Memory reference, Register reference or Input-Output instruction.  If 𝐷7 = 1 then instruction must be register reference or input- Instruction output else memory reference instruction. ▪ Instruction Cycle Flowchart Cycle  Start SC ← 0 𝑇0 AR ← PC 𝑇1 IR ← M[AR], PC ← PC + 1 𝑇2 Decode operation code in IR(12-14) AR ← IR(0-11), I ← IR(15) (Register or I/O) = 1 D = 0 (Memory-reference) 7 (I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct) I I 𝑇3 𝑇3 𝑇3 𝑇3 Execute Execute AR ← Nothing input-output register-reference M[AR] instruction instruction SC ← 0 SC ← 0 Execute memory-reference instruction SC ← 0  D7I’T3 = r (common to all register reference instructions) IR(i) = Bi [bit in IR(0-11) that specifies the operation] CLA rB11 AC ← 0 Clear AC CLE rB10 E←0 Clear E CMA rB9 AC ← AC’ Complement AC Register CME rB8 E ← E’ Complement E Reference CIR rB7 AC ← shr AC, AC(15) ← E, E ← AC(0) Circulate right CIL rB6 AC ← shl AC, AC(0) ← E, E ← AC(15) Circulate left Instruction INC rB5 AC ← AC + 1 Increment AC SPA rB4 If (AC(15) = 0) then (PC ← PC + 1) Skip if AC is positive SNA rB3 If (AC(15) = 1) then (PC ← PC + 1) Skip if AC is negative SZA rB2 If (AC = 0) then (PC ← PC + 1) Skip if AC is zero SZE rB1 If (E = 0) then (PC ← PC + 1) Skip if E is zero HLT rB0 S ← 0 (S is a start-stop flip-flop) Halt Computer  1. AND: AND to AC This is an instruction that performs the AND logic operation on pairs of bits in AC and the memory word specified by the effective address. The result of the Memory operation is transferred to AC. Reference D0T4: DRM[AR] Instructions D0T5: AC  AC  DR, SC  0  2. ADD: ADD to AC This instruction adds the content of the memory word specified by the effective address to the value of AC. The sum is transferred into AC and the output carry Cout is Memory transferred to the E (extended accumulator) flip-flop. Reference D1T4: DRM[AR] Instructions D1T5: AC  AC + DR, E  Cout, SC  0  3. LDA: Load to AC This instruction transfers the memory word specified by the effective address to AC. Memory D2T4: DRM[AR] Reference D2T5: AC  DR, SC  0 Instructions  4. STA: Store AC This instruction stores the content of AC into the memory word specified by the effective address. Memory D3T4: M[AR]  AC, SC  0 Reference Instructions  5. BUN: Branch Unconditionally This instruction transfers the program to instruction specified by the effective address. The BUN instruction allows the programmer to specify an instruction out of Memory sequence and the program branches (or jumps) Reference unconditionally. Instructions D4T4: PC  AR, SC  0  6. BSA: Branch and Save Return Address This instruction is useful for branching to a portion of the program called a subroutine or procedure. When executed, the BSA instruction stores the address of the next Memory instruction in sequence (which is available in PC) into a Reference memory location specified by the effective address. Instructions D5T4: M[AR]  PC, AR  AR + 1 D5T5: PC  AR, SC  0  20 0 BSA 135 20 0 BSA 135 PC = 21 Next Instruction 21 Next Instruction AR = 135 135 21 136 PC = 136 BSA Subroutine Subroutine 1 BUN 135 1 BUN 135 Memory, PC and AR at Time T4 Memory and PC after execution D5T4: M  21, AR  135 + 1 D5T5: PC  136, SC  0  7. ISZ: Increment and Skip if Zero These instruction increments the word specified by the effective address, and if the incremented value is equal to 0, PC is incremented by 1. Since it is not possible to Memory increment a word inside the memory, it is necessary to Reference read the word into DR, increment DR, and store the word Instructions back into memory. D6T4: DR  M[AR] D6T5: DR  DR + 1 D6T6: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0  Memory-reference instruction AND ADD LDA STA D0T 4 D1T 4 D2T 4 D 3T 4 DR  M[AR] DR  M[AR] DR  M[AR] M[AR]  AC SC  0 Flowchart for D0T 5 AC  AC /\ DR D1T 5 AC  AC + DR AC  DR D2T 5 SC  0 E  Cout SC  0 Memory SC  0 Reference BUN D4T 4 BSA D5T 4 ISZ D6T 4 Instructions PC  AR SC  0 M[AR]  PC AR  AR + 1 DR  M[AR] D5T 5 D6T 5 PC  AR DR  DR + 1 SC  0 D6T 6 M[AR]  DR If (DR = 0) then (PC  PC + 1) SC  0  Input-Output Serial Computer registers terminal communication and flip-flop interface FGO =1 =0 Receiver Input-Output Printer Interface OUTR of basic computer AC Transmitter Keyboard INPR Interface FGI =1 =0  ▪ A computer can serve no useful purpose unless it communicates with the external environment. ▪ To exhibit the most basic requirements for input and output communication, we will use a terminal unit with a keyboard and printer. Input-Output ▪ The terminal sends and receives serial information and each of basic quantity of information has eight bits of an alphanumeric code. ▪ The serial information from the keyboard is shifted into the input computer register INPR. ▪ The serial information for the printer is stored in the output register OUTR. ▪ These two registers communicate with a communication interface serially and with the AC in parallel.  ▪ Initially, the input flag FGI is cleared to 0. When a key is struck in the keyboard, an 8-bit alphanumeric code is shifted into INPR and the input flag FGI is set to 1. ▪ As long as the flag is set, the information in INPR cannot be Process of changed by striking another key. The computer checks the input flag bit; if it is 1, the information from INPR is transferred in information parallel into AC and FGI is cleared to 0. transfer ▪ Once the flag is cleared, new information can be shifted into INPR by striking another key.  ▪ The output register OUTR works similarly but the direction of information flow is reversed. ▪ Initially, the output flag FGO is set to 1. The computer checks the flag bit; if it is 1, the information from AC is Process of transferred in parallel to OUTR and FGO is cleared to 0. The outputting output device accepts the coded information, prints the information corresponding character, and when the operation is completed, it sets FGO to 1. ▪ The computer does not load a new character into OUTR when FGO is 0 because this condition indicates that the output device is in the process of printing the character.  D7IT3 = p (common to all input-output instructions) IR(i) = Bi [bit in IR(6-11) that specifies the operation] INP pB11 AC(0-7) ← INPR, FGI ← 0 Input Character OUT pB10 OUTR ← AC(0-7), FGO ← 0 Output Character SKI pB9 If (FGI = 1) then (PC ← PC + 1) Skip on input flag Input-Output SKO pB8 If (FGO = 1) then (PC ← PC + 1) Skip on output flag IEN ← 1 Instruction ION IOF pB7 pB6 IEN ← 0 Interrupt enable on Interrupt enable off  Instruction cycle = 0 = 1 Interrupt cycle R Fetch & Decode Store return address instruction in location 0 M ← PC Execute =0 Interrupt Cycle instruction IEN Branch to location 1 =1 PC ← 1 =1 FGI =0 IEN ← 0 =1 FGO R←0 =0 R←1  ▪ The interrupt cycle is a hardware implementation of a branch and save return address operation. ▪ An interrupt flip-flop R is included in the computer. ▪ When R = 0, the computer goes through an instruction cycle. Interrupt Cycle  ▪ During the execute phase of the instruction cycle IEN is checked by the control. ▪ If it is 0, it indicates that the programmer does not want to use the interrupt, so control continues with the next instruction cycle. ▪ If IEN is 1, control checks the flag bits. Interrupt Cycle ▪ If both flags are 0, it indicates that neither the input nor the output registers are ready for transfer of information. ▪ In this case, control continues with the next instruction cycle. If either flag is set to 1 while IEN = 1, flip-flop R is set to 1. ▪ At the end of the execute phase, control checks the value of R, and if it is equal to 1, it goes to an interrupt cycle instead of an instruction cycle.  ▪ The flip-flop is set to 1 if IEN = 1 and either FGI or FGO are equal to 1. This can happen with any clock transition except when timing signals T0, T1 or T2 are active. ▪ The condition for setting flip-flop R= 1 can be expressed Register with the following register transfer statement: transfer T0T1T2  (IEN) (FGI + FGO): R  1 statements for ▪ The symbol + between FGI and FGO in the control function Interrupt cycle designates a logic OR operation. This is AND with IEN and T0T1 T2.  ▪ The fetch and decode phases of the instruction cycle must be modified and Replace T0, T1, T2 with R'T0, R'T1, R'T2 ▪ Therefore the interrupt cycle statements are : RT0 : AR  0, TR  PC Register RT1 : M[AR]  TR, PC  0 transfer RT2 : PC  PC + 1, IEN  0, R  0, SC  0 statements for Interrupt cycle  ▪ During the first timing signal AR is cleared to 0, and the content of PC is transferred to the temporary register TR. ▪ With the second timing signal, the return address is stored in memory at location 0 and PC is cleared to 0. Register ▪ The third timing signal increments PC to 1, clears IEN and transfer R, and control goes back to T0 by clearing SC to 0. statements for ▪ The beginning of the next instruction cycle has the Interrupt cycle condition RT0 and the content of PC is equal to 1. The control then goes through an instruction cycle that fetches and executes the BUN instruction in location 1.  0 0 256 1 0 BUN 1120 PC = 1 0 BUN 1120 255 255 PC = 256 256 Demonstration Main Program Main Program of Interrupt Cycle 1120 1120 I/O program I/O program 1 BUN 0 1 BUN 0 Before Interrupt After Interrupt Complete Computer Description (Micro- operations) Complete Computer Description (Micro- operations)  ▪ Hardware Components of Basic Computer A memory unit: 4096 x 16. Registers: AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC Flip-Flops(Status): I, S, E, R, IEN, FGI, and FGO Decoders: a 3x8 Opcode decoder & a 4x16 timing decoder Common bus: 16 bits Design of Basic Adder and Logic circuit: Connected to AC Computer ▪ Control Logic Gates: Input Controls of the nine registers Read and Write Controls of memory Set, Clear, or Complement Controls of the flip-flops S2, S1, S0 Controls to select a register for the bus AC, and Adder and Logic circuit  ▪ Basic Computer Design of Basic Computer  Start SC ← 0, IEN ← 0, R ← 0 (Instruction cycle) = 0 (Interrupt cycle) = 1 R 𝑅′𝑇0 𝑅𝑇0 AR ← PC AR ← 0, TR ← PC 𝑅′𝑇1 𝑅𝑇1 IR ← M[AR], PC ← PC + 1 M[AR] ← TR, PC ← 0 𝑅′𝑇2 𝑅𝑇2 Decode operation code in IR(12-14) PC ← PC + 1, IEN ← AR ← IR(0-11), I ← IR(15) 0, R ← 0, SC ← 0 (Register or I/O) = 1 = 0 (Memory-reference) D 7 (I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct) I I 𝑇3 𝑇3 𝑇3 𝑇3 Execute Execute AR ← Nothing input-output register-reference M[AR] instruction instruction SC ← 0 SC ← 0 Execute memory-reference instruction SC ← 0  ▪ In order to design the logic associated with AC, it is necessary to extract all the statements that change the content of AC. Design of D0T5: AC ← AC ∧ DR, SC ← 0 AND with DR Accumulator D1T5: AC ← AC + DR, SC ← 0 ADD with DR Unit D2T5: AC ← DR Transfer from DR pB11: AC(0-7) ← INPR, FGI ← 0 Transfer from INPR rB9: AC ← AC’ Complement rB7: AC ← shr AC, AC(15) ← E Shift right rB6: AC ← shl AC, AC(0) ← E Shift left rB11: AC ← 0 Clear rB5: AC ← AC + 1 Increment  Circuit associated with AC 16 16 Adder and logic 16 Accumulator register 16 From DR circuit (AC) To From INPR 8 bus Design of LD INR CLR Accumulator Clock Logic Control gates  Gate structure for controlling LD, INR and CLR of AC D0 AND T5 16 16 AC D1 ADD From Adder To bus & Logic D2 DR LD INR CLR Clock Design of T5 p B11 Accumulator r INPR B9 CMA Logic SHR B7 SHL B6 INC B5 CLR B11 Thank You