HDL Topic Outlines - PDF

IMPORTANTS **1. Number system conversions (e.g., Binary to Hex, Hex to Octal, Decimal to Binary)** LCD **2. FPGA and FPGA Design process flow** **FPGA -- FIELD PROGRAMMABLE GATE ARRAY** - a device (a chip) whose **internal logic can be changed by the developer** (user) after the chip has...

IMPORTANTS **1. Number system conversions (e.g., Binary to Hex, Hex to Octal, Decimal to Binary)** LCD **2. FPGA and FPGA Design process flow** **FPGA -- FIELD PROGRAMMABLE GATE ARRAY** - a device (a chip) whose **internal logic can be changed by the developer** (user) after the chip has been manufactured---it is "field programmable". - its functionality is **similar to a microprocessor but it is not!** - also uses a language to describe the application's functionality, and a tool to generate the new hardware to be configured inside the FPGA. a. employs "writable" technologies, such as SRAM or FLASH memories. **ASIC -- APPLICATION SPECIFIC INTEGRATED CIRCUIT** **LUT -- LOOK UP TABLE** **HDL --** A modelling language used to describe the circuit behavior of a digital circuit. 1. **Specifications** describe abstractly the functionality, interface, and overall architecture of the digital circuit. 2. A **behavioral description** is then created to analyze the design in terms of functionality, performance, compliance to standards, and other high-level issues. 3. The behavioral description is manually **converted to an RTL description** in an HDL. 4. Computer-Aided Design (CAD) processes the designs with its tools from this point forward 5. **Logic synthesis tools** convert the RTL description to a gate-level netlist. 6. A **gate level netlist** is a description of the circuit in terms of gates and connections between them 7. The gate-level netlist is input to an **Automatic Place and Route tool**, [which creates a layout] 8. The layout is verified and then fabricated on chip **3. Digital System Design flow (e.g., VLSI circuits)** **vacuum tubes and transistors** - Earliest digital circuits were designed with. **Era of Integrated Circuits (ICs)** -- logic gates were placed on a single chip. - **Small Scale Integration (SSI)** -- fewer than 12 gates - Medium Scale Integration (MSI) -- 12 to 99 gates - Large Scale Integration (LSI) -- 100 to 9,999 gates **Era of Integrated Circuits (ICs)** -- logic gates were placed on a single chip. - **Very Large Scale Integration (VLSI)** -- 10,000 to 99,999 gates (5 digits) - **Ultra Large Scale Integration (ULSI)** -- 100,000 to 999,999 gates (6 digits) **Logic simulators** came into existence to verify the functionality of these circuits before they were fabricated on a chip. **FORTRAN, Pascal, and C** - these are sequential in nature. **HDL** - allow designers to model concurrency of hardware elements. - **Verilog HDL** originated in **1983** at **Gateway Design Automation**. - **VHDL** was developed under **DARPA.** **Digital System** - composed of interconnected modules designed to handle digital (discrete) signals to analyze and describe specific physical phenomena. - composed of two basic components: Datapath and Control Unit. - **Control Unit** - the generation of control signals to the datapath unit (also known as \"operational block''). - **receive** control inputs from the **external environment**. - **generate one or more output control** signals to communicate with other digital systems. - **Datapath** - **performs** operations on data received, usually, **from the external environment.** - performed in one or more steps, where **each step takes a clock cycle**. - generates "**status" signals** (sometimes also called as "**flags**") - used by the control block - define the sequence of operations to be performed. - **Control Signals --** command the desired operations in the datapath Parts of a Digital System: 1. 2. Control Input 3. Control Unit 4. Control Output 5. Data Input 6. Datapath 7. Data Output  **4. Hierarchical Design Methodologies (top-down and bottom-up)** **Hierarchical Modeling Concepts** - **Top-Down Design Methodology** - top-down defines the top-level block first and identify sub-blocks after - we further subdivide the sub-blocks until we come to leaf cells. - leaf cells are cells that cannot further be divided. - A diagram of a cell block Description automatically generated - **Bottom-Up Design Methodology** - bottom-up identifies building blocks first and use these to create higher level blocks until we build the top-level block. -  **design architects** define the specifications of the top-level block. **logic designers** break up the functionality into blocks and sub-blocks. **circuit designers** are designing optimized circuits for leaf-level cells, they build high-level cells by using these leaf-level cells. **5. VHDL and Verilog comparisons** VHDL - **Very High Speed Integrated Circuits** HDL - Developed by US dept. of defense in 1980s - a very verbose language - strongly-typed - similar to Ada or Pascal Verilog HDL - more compact (less code) - weakly-typed - similar to C - general-purpose hardware description language - allows different levels of abstraction - **Programming Language Interface (PLI)** - is a powerful feature that **allows the user to write custom C code** to interact with the internal data structures of **Verilog.** **6. basic VHDL structure (entity, architecture, component, and process block)** - FPGA devices have three main configurable components: - the logic blocks - the larger squares, interconnected by the routing elements - configured in order to perform the logic operations required by the application, and so they are the "processing elements" of an FPGA. - the routing elements - interconnecting with every block - and the input/output (I/O) blocks. - located in the periphery of the chip - configured in order to function as input pins, output pins, or both - The entity part: - has only the **input and output pins** (interface) to be used by the circuit. - the interface between the implemented logic and the external world - The architecture part: - Is the **operational description** of the circuit - Defines **functionality** of circuit **7. basic Verilog module structure (port interface, module definition)** **Modules** - basic building block in Verilog - consists of distinct parts: - keyword module, module name and port list - variable declarations\* - data flow statements\* - instantiation of lower modules\* - behavioral blocks\* - tasks and functions\* - endmodule statement 1. begin with keyword module followed by module name 2. must end with keyword endmodule 3. Port list, port declarations, and optional parameters must come after module name 4. Port list and port declarations are present only if the module has any ports to interact with the external environment 5. multiple modules in a single file is allowed 6. modules can be defined in any order **Ports** - provide the interface by which the module can **communicate with its environment**. - for example, the **input/output pins** of an IC chip are its ports. - the **environment can interact** with the module only through its ports. - the internals of the module are **not visible** to the environment. - the internals of the module can be changed without affecting the environment if the interface is not modified. - also referred to as **terminals**. **8. Importance, advantages, and purposes of HDLs** HDLs have many **advantages** compared to traditional schematic-based design: 1. Designs can be described at a very **abstract level**. 2. **Functional verification** of the design can be done **early** in the design cycle. 3. Designing with HDLs is **analogous** to computer programming. This provides a **concise representation** of the design, compared to gate level schematics. a. **Gate-level schematics are almost incomprehensible** for very complex designs. **9. Logic symbols** LCD Gate Level - Implemented using logic gates and interconnections between gates Dataflow Level - Module is designed by specifying the data flow. Uses logic equations. Behavioral Level - The highest abstraction level. The module is implemented in terms of the desired algorithm without concern for hardware implementation details. Switch Level - The lowest level. Module is implemented using transistor-level modeling. std\_logic -- IEEE 1164 library, provides standard logic types and functions for digital design std\_ulogic -- IEEE 1164, similar to std\_logic but unresolved (does not allow multiple drivers for same signal) **10. Do some research about Intel Quartus Prime (this is an EDA tool much like EDA playground but is more complex)** **LABS**