Digital Circuit Design Tutorial Sheets 5-7 PDF

# JAYPEE INSTITUTE OF INFORMATION TECHNOLOGY ## Electronics and Communication Engineering ### Digital Circuit Design (18B11EC215) #### Tutorial Sheet: 5 1. **[CO3]** Implement the four Boolean functions using three half-adder circuits: - D = A⊕B⊕C, where ⊕ is XOR gate. - E = A'BC + AB'C...

# JAYPEE INSTITUTE OF INFORMATION TECHNOLOGY ## Electronics and Communication Engineering ### Digital Circuit Design (18B11EC215) #### Tutorial Sheet: 5 1. **[CO3]** Implement the four Boolean functions using three half-adder circuits: - D = A⊕B⊕C, where ⊕ is XOR gate. - E = A'BC + AB'C - F = ABC' + (A'+B')C - G = ABC 2. **[CO3]** Realize 2-bit magnitude comparator, using 1-bit magnitude comparator as black box, which is having two inputs A and B, each of 2 bits, and produces three outputs G, L and E for A>B, A<B and A=B, respectively. 3. **[CO3]** Design a 2-bit multiplier using 1-bit multiplier and Half adder as black boxes. Also mention how many 1-bit multipliers and Half adders would be required for the realization. 4. **[CO3s]** Obtain boolean expressions of the output of a 5-bit Magnitude Comparator [Hint: students are advised not to start with the truth-table for 5-bit Magnitude Comparator, rather try to directly write the expression using the concept of 1-bit magnitude comparator]. 5. **[CO3]** Implement a Full adder circuit using two half adders and one OR gate. If the gates for realization of the complete circuit having following delays: XOR gate - 20 ns, AND gate - 10 ns, and OR gate - 10 ns, then determine the propagation delay to obtain the Sum and Carry outputs. 6. **[CO3]** Design a combinational circuit that compares two 4-bit numbers to check if they are equal or not. The output of the circuit, x, is 1 for A = B and is 0 when A is not equal to B. 7. **[CO3]** A 4-bit parallel adder is implemented using full adders. It is known that each full adder takes 20 ns and 10 ns to produce sum and carry output, respectively. Determine the time required to complete the 4-bit addition. 8. **[CO3]** Without any initial carry, determine the number of half adders and OR gates required to make a 4-bit parallel full adder [Hint: Implement full adder using half adders and OR gate]. 9. **[CO3]** A 1-bit full adder takes 20ns to generate carry-out bit and 40ns for the sum bit. What is the maximum rate of addition per second when four 1-bit full adders are cascaded? # JAYPEE INSTITUTE OF INFORMATION TECHNOLOGY ## Electronics and Communication Engineering ### Digital Circuit Design (18B11EC215) #### Tutorial Sheet: 6 1. **[CO3]** Realize Full Subtractor using 3×8 decoder and basic logic gates. 2. **[CO3]** Implement the following multiple output combinational logic circuit using a 4 line-to- 16 line decoder: - F₁ = ∑m(0,1,4, 7, 12, 14, 15) - F₂ = ∑m(1,3,6,9, 12) - F3 = ∑m(2,3,7,8,10) - F₁ = ∑m(1,3,5) 3. **[CO3]** Design a 4×16 Decoder using 3×8 decoders. 4. **[CO3]** Implement the following expressions: - (a) F (A, B, C) = ∑m (1, 4, 6, 7) using single 4:1 Multiplexer. - (b) F (A, B, C, D) = ∑m (0, 2, 3, 6, 8, 9, 12, 14) using single 8:1 Multiplexer. - (c) Full subtractor using two 4:1 Multiplexers. - (d) F(A, B, C, D)=∑m (0, 1, 4, 6, 12, 13) using 8:1 Multiplexer, choose A, B & D as selection lines S2, S1, SO respectively. - (e) Implement the Boolean function F(A, B, C, D) = AB+BD+BCD using 8:1 Multiplexer, choose A, B & C as selection lines and D as input. 5. **[CO3]** Realize following function F(A, B, C) = AB +ABC+ABC by using minimum number of Multiplexers (a) 2×1 MUX (b) 4×1 MUX (c) 8×1 MUX 6. **[CO3]** What is the logic function of the MUX circuit as shown in Fig. 1. 7. **[CO3]** Realize the following truth table using 4x1 Multiplexer: | A | B | C | F | |---|---|---|---| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | | 0 | 1 | 0 | 0 | | 0 | 1 | 1 | 1 | | 1 | 0 | 0 | 0 | | 1 | 0 | 1 | 1 | | 1 | 1 | 0 | 1 | | 1 | 1 | 1 | 1 | 8. **[CO3]** Design a Binary to Gray code Converter circuit using 4×1Multiplexers. Inputs are of 4 bit binary number. # JAYPEE INSTITUTE OF INFORMATION TECHNOLOGY ## Electronics and Communication Engineering ### Digital Circuit Design (18B11EC215) #### Tutorial Sheet: 7 1. **[CO3]** The truth table for AB flip-flop (FF) is shown below. Draw schematic diagram using JK flip-flop and any additional logic to implement it. Show the design steps? | An | Bn | Qn+1 | |---|---|---| | 0 | 0 | Qn | | 1 | 0 | Qn | | 0 | 1 | 1 | | 1 | 1 | 0 | 2. **[CO3]** Implement JK-FF using D-FF. Show the design steps? 3. **[CO3]** An input signal of frequency 12 kHz is applied to the JK-FF circuit as shown in Fig. 1. What will be the resulting output frequency? 4. **[CO3]** Analyze the circuit of Fig. 2 and prove that it is equivalent to a T flip-flop. 5. **[CO3]** Consider the J-K flip flop shown in Fig. 3 6. **[CO3]** In Fig. 4, A =1 and B =1. If the input B is now replaced by a sequence 101010...., then what will be values of outputs X and Y? 7. **[CO3]** In Fig. 5, if CLK frequency is 10 kHz, then what will be the frequency at output X?