comp org lecture 1.pdf

+ Computer Organization Course Code: INT 203 Dr. Rumana Islam Visting Faculty College of Engineering and Technology University of Science and Technology of Fujairah © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + William Stallings Computer Or...

+ Computer Organization Course Code: INT 203 Dr. Rumana Islam Visting Faculty College of Engineering and Technology University of Science and Technology of Fujairah © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + William Stallings Computer Organization and Architecture 10th Edition © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Chapter 1 Basic Concepts and Computer Evolution © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + ◼ In describing computers, a distinction is often made between computer architecture and computer organization. ◼ Computer architecture refers to those attributes of a system visible to a programmer (Instruction set, number of bits used to represent various data types, I/O mechanisms, techniques for addressing memory) ◼ A term that is often used interchangeably with computer architecture is instruction set architecture (ISA). ◼ The ISA defines instruction formats, instruction opcodes, registers, instruction and data memory; the effect of executed instructions on the registers and memory; and an algorithm for controlling instruction execution. ◼ Computer organization refers to the operational units and their interconnections that realize the architectural specifications. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + IBM System 370 Architecture ◼ IBM System/370 architecture ◼ Was introduced in 1970 ◼ Included a number of models ◼ Could upgrade to a more expensive, faster model without having to abandon original software ◼ New models are introduced with improved technology, but retain the same architecture so that the customer’s software investment is protected ◼ Architecture has survived to this day as the architecture of IBM’s mainframe product line © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Structure and Function Millions of electronic components ◼ Hierarchical system ◼ Set of interrelated subsystems ◼ Hierarchical nature of complex systems is essential to both their design and their description ◼ Designer need only deal with a particular level of the system at a time ◼ Concerned with structure and function at each level Top to More bottom/bottom to effective top ??? © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Function ◼ There are four basic functions that a computer can perform: ◼ Data processing ◼ Data may take a wide variety of forms and the range of processing requirements is broad ◼ Data storage ◼ Short-term ◼ Long-term ◼ Data movement ◼ Input-output (I/O) - when data are received from or delivered to a device (peripheral) that is directly connected to the computer ◼ Data communications – when data are moved over longer distances, to or from a remote device ◼ Control ◼ A control unit manages the computer’s resources and orchestrates the performance of its functional parts in response to instructions. © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  COMPUTER I/O Main memory System Bus CPU CPU Registers ALU Structure Internal Bus Control Unit CONTROL UNIT Sequencing Logic Control Unit Registers and Decoders Control Memory Figure 1.1 A Top-Down View of a Computer © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. +  CPU – controls the operation of the computer and performs its There are four data processing functions main structural components  Main Memory – stores data of the computer:  I/O – moves data between the computer and its external environment  System Interconnection – some mechanism that provides for communication among CPU, main memory, and I/O © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + ◼ Control Unit CPU ◼ Controls the operation of the CPU and hence the computer Major structural ◼ Arithmetic and Logic Unit (ALU) components: ◼ Performs the computer’s data processing function ◼ Registers ◼ Provide storage internal to the CPU ◼ CPU Interconnection ◼ Some mechanism that provides for communication among the control unit, ALU, and registers © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Multicore Computer Structure ◼ Central processing unit (CPU) ◼ Portion of the computer that fetches and executes instructions ◼ Consists of an ALU, a control unit, and registers ◼ Referred to as a processor in a system with a single processing unit ◼ Core ◼ An individual processing unit on a processor chip ◼ May be equivalent in functionality to a CPU on a single-CPU system ◼ Specialized processing units are also referred to as cores ◼ Processor ◼ A physical piece of silicon containing one or more cores ◼ Is the computer component that interprets and executes instructions ◼ Referred to as a multicore processor if it contains multiple cores © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Cache Memory (ch. 4) ◼ Multiple layers of memory between the processor and main memory ◼ Is smaller and faster than main memory ◼ Used to speed up memory access by placing in the cache data from main memory that is likely to be used in the near future ◼ A greater performance improvement may be obtained by using multiple levels of cache, with level 1 (L1) closest to the core and additional levels (L2, L3, etc.) progressively farther from the core © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  MOTHERBOARD Main memory chips Processor I/O chips chip PROCESSOR CHIP Core Core Core Core L3 cache L3 cache Core Core Core Core CORE Arithmetic Instruction and logic Load/ logic unit (ALU) store logic L1 I-cache L1 data cache L2 instruction L2 data cache cache Figure 1.2 Simplified View of Major Elements of a Multicore Computer © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  + Figure 1.3 Motherboard with Two Intel Quad-Core Xeon Processors © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Figure 1.4 zEnterprise EC12 Processor Unit (PU) Chip Diagram © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Figure 1.5 zEnterprise EC12 Core Layout © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + History of Computers First Generation: Vacuum Tubes ◼ Vacuum tubes were used for digital logic elements and memory ◼ IAS computer ◼ Fundamental design approach was the stored program concept ◼ Attributed to the mathematician John von Neumann ◼ First publication of the idea was in 1945 for the EDVAC ◼ Design began at the Princeton Institute for Advanced Studies ◼ Completed in 1952 ◼ Prototype of all subsequent general-purpose computers © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Central processing unit (CPU) Arithmetic-logic unit (CA) AC MQ Input- Arithmetic-logic output circuits equipment (I, O) MBR Instructions and data Instructions and data M(0) M(1) M(2) M(3) PC IBR M(4) AC: Accumulator register MQ: multiply-quotient register MBR: memory buffer register IBR: instruction buffer register MAR IR PC: program counter MAR: memory address register Main IR: insruction register memory (M) Control Control circuits signals M(4092) M(4093) M(4095) Program control unit (CC) Addresses Figure 1.6 IAS Structure © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  0 1 39 sign bit (a) Number word left instruction (20 bits) right instruction (20 bits) 0 8 20 28 39 opcode (8 bits) address (12 bits) opcode (8 bits) address (12 bits) (b) Instruction word Figure 1.7 IAS Memory Formats © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Registers Contains a word to be stored in memory or sent to the Memory buffer register I/O unit (MBR) Or is used to receive a word from memory or from the I/O unit Memory address Specifies the address in memory of the word register (MAR) to be written from or read into the MBR Contains the 8-bit opcode instruction being Instruction register (IR) executed Instruction buffer Employed to temporarily hold the right-hand register (IBR) instruction from a word in memory Contains the address of the next instruction Program counter (PC) pair to be fetched from memory Accumulator (AC) and Employed to temporarily hold operands and multiplier quotient (MQ) results of ALU operations © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Start Yes Is next No instruction MAR PC No memory in IBR? Fetch access cycle required MBR M(MAR) Left No Yes IBR MBR (20:39) IR IBR (0:7) IR MBR (20:27) instruction IR MBR (0:7) MAR IBR (8:19) MAR MBR (28:39) required? MAR MBR (8:19) PC PC + 1 Decode instruction in IR AC M(X) Go to M(X, 0:19) If AC > 0 then AC AC + M(X) go to M(X, 0:19) Execution Yes Is AC > 0? cycle MBR M(MAR) PC MAR No MBR M(MAR) AC MBR AC AC + MBR M(X) = contents of memory location whose addr ess is X (i:j) = bits i through j Figure 1.8 Partial Flowchart of IAS Operation © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Symbolic Instruction Type Opcode Representation Description 00001010 LOAD MQ Transfer contents of register MQ to the accumulator AC 00001001 LOAD MQ,M(X) Transfer contents of memory location X to MQ 00100001 STOR M(X) Transfer contents of accumulator to memory Data transfer location X 00000001 LOAD M(X) Transfer M(X) to the accumulator 00000010 LOAD –M(X) Transfer –M(X) to the accumulator 00000011 LOAD |M(X)| Transfer absolute value of M(X) to the accumulator 00000100 LOAD –|M(X)| Transfer –|M(X)| to the accumulator Unconditional 00001101 JUMP M(X,0:19) Take next instruction from left half of M(X) branch 00001110 00001111 JUMP M(X,20:39) JUMP+ M(X,0:19) Take next instruction from right half of M(X) If number in the accumulator is nonnegative, take next instruction from left half of M(X) Table 1.1 0 JU If number in the 0 MP accumulator is nonnegative, 0 + take next instruction from The IAS Conditional branch 1 M(X right half of M(X) 0 ,20: 0 39) 00000101 0 0 ADD M(X) Add M(X) to AC; put the result in AC Instruction Set 00000111 ADD |M(X)| Add |M(X)| to AC; put the result in AC 00000110 SUB M(X) Subtract M(X) from AC; put the result in AC 00001000 SUB |M(X)| Subtract |M(X)| from AC; put the remainder in AC 00001011 MUL M(X) Multiply M(X) by MQ; put most significant bits of result in AC, put least significant bits Arithmetic in MQ 00001100 DIV M(X) Divide AC by M(X); put the quotient in MQ and the remainder in AC 00010100 LSH Multiply accumulator by 2; i.e., shift left one bit position 00010101 RSH Divide accumulator by 2; i.e., shift right one position 00010010 STOR M(X,8:19) Replace left address field at M(X) by 12 rightmost bits of AC Address modify 00010011 STOR M(X,28:39) Replace right address field at M(X) by 12 rightmost bits of AC (Table can be found on page 17 in the textbook.) © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + History of Computers Second Generation: Transistors ◼ Smaller ◼ Cheaper ◼ Dissipates less heat than a vacuum tube ◼ Is a solid state device made from silicon ◼ Was invented at Bell Labs in 1947 ◼ It was not until the late 1950’s that fully transistorized computers were commercially available © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Table 1.2 Computer Generations Approximate Typical Speed Generation Dates Technology (operations per second) 1 1946–1957 Vacuum tube 40,000 2 1957–1964 Transistor 200,000 3 1965–1971 Small and medium scale 1,000,000 integration 4 1972–1977 Large scale integration 10,000,000 5 1978–1991 Very large scale integration 100,000,000 6 1991- Ultra large scale integration >1,000,000,000 © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + Second Generation Computers ◼ Introduced: ◼ More complex arithmetic and logic units and control units ◼ The use of high-level programming languages ◼ Provision of system software which provided the ability to: ◼ Load programs ◼ Move data to peripherals ◼ Libraries perform common computations © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  IBM 7094 computer Peripheral devices Mag tape units CPU Card punch Data channel Line printer Card reader Drum Multi- Data plexor channel Disk Data Disk channel Hyper- tapes Memory Data Teleprocessing channel equipment Figure 1.9 An IBM 7094 Configuration © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  History of Computers Third Generation: Integrated Circuits ◼ 1958 – the invention of the integrated circuit ◼ Discrete component ◼ Single, self-contained transistor ◼ Manufactured separately, packaged in their own containers, and soldered or wired together onto masonite-like circuit boards ◼ Manufacturing process was expensive and cumbersome ◼ The two most important members of the third generation were the IBM System/360 and the DEC PDP-8 © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Boolean Binary Input logic Output Input storage Output function cell Read Activate Write signal (a) Gate (b) Memory cell Figure 1.10 Fundamental Computer Elements © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. + ◼ A computer consists of gates, Integrated memory cells, and interconnections among these Circuits elements ◼ The gates and memory cells ◼ Data storage – provided by are constructed of simple memory cells digital electronic components ◼ Data processing – provided by gates ◼ Exploits the fact that such components as transistors, resistors, and conductors can be ◼ Data movement – the paths fabricated from a among components are used semiconductor such as silicon to move data from memory to memory and from ◼ Many transistors can be memory through gates to produced at the same time on a memory single wafer of silicon ◼ Control – the paths among ◼ Transistors can be connected components can carry control with a processor metallization to signals form circuits © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  Wafer Chip Gate Packaged chip Figure 1.11 Relationship Among Wafer, Chip, and Gate © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.  t ui g ed of rc or in ga w d st rk ci ul l a at n te gr tio si o ’s an w om e te n r tr irst in ve p r oo In M F 100 bn 10 bn 1 bn 100 m 10 m 100,000 10.000 1,000 100 10 1 1947 50 55 60 65 70 75 80 85 90 95 2000 05 11 Figure 1.12 Growth in Transistor Count on Integrated Circuits (DRAM memory) © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. Moore’s Law 1965; Gordon Moore – co-founder of Intel Observed number of transistors that could be put on a single chip was doubling every year Consequences of Moore’s law: The pace slowed to a doubling every 18 months in the 1970’s but has sustained The cost of The electrical Computer computer logic path length is becomes smaller Reduction in that rate ever since and memory shortened, power and Fewer and is more interchip circuitry has increasing convenient to cooling use in a variety connections fallen at a operating requirements dramatic rate speed of environments © 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.