Analogue Systems RX PDF

THEORY OF OPERATION (Refer to simplified block diagram of figure 2-5-1) The Receiver Analogue System includes RF, IF and VIDEO sections which have been designed to: -convert the RF echo-signal, reflected from the target into a signal in digital form, suited for being more processed in the Digital...

THEORY OF OPERATION (Refer to simplified block diagram of figure 2-5-1) The Receiver Analogue System includes RF, IF and VIDEO sections which have been designed to: -convert the RF echo-signal, reflected from the target into a signal in digital form, suited for being more processed in the Digital Processing System; -keep the received information clean or mixed with clutter, within the dynamics of the radar system, thus avoiding saturation phenomena which may deteriorate the SCV. The SCV value being to degrade when the clutter exceeds the noise of 37dB; this condition would often occur especially in vicinity to the radar site if were not used those circuits adapting the receiver with the operating requirements. The Receiver Analogue System performs the following main functions on the useful signal: \- RF / IF frequency conversion \- IF amplification \- IF to Video conversion \- Analogue to Digital *(AID)* conversion. The following operations are instead performed on the clutter returns: -Definition of the receiver linear dynamic and MTI processable dynamic range (37dB) -Reduction of the clutter amplitude to within the above dynamic (see figure 2-5-6). *Antenna Beam Combined Function* - As previously stated the appearance of extensive low angle phenomena such as strong ground clutter and angels may impair the echoes detection for those aircraft flying within such areas. Making the radar less sensitive to returns coming from very low angles can reduce the phenomena. This is achieved by the use of an auxiliary feed which produces an alternative receiving pattern less sensitive that the main receiving pattern at the angels, as can be seen in figure 2-5-3. The advantage of this approach is that echoes of aircraft flying at medium and high altitude over large blocks of clutter or angels will be more readily detected because the target to clutter ratio will be considerably enhanced by the auxiliary receiving pattern. To further improve on this method, a special system is used to create three patterns for optimum rejection of low angle interference and preservation of target returns. That is, starting from time zero, the overall radar coverage pattern will consists of: \- Difference beam \- Auxiliary beam \- Main beam. The exact time of switching are established either by a manual presetting or automatically in accordance with the actual site surroundings being memorized in a 1024 cells map allowing the switching from one beam to another whenever required, and in any order (see fig. 2-5-4-a). 2-5-1 The manual switching preset should also be done in accordance with the site surrounding clutter and the selection either of the difference beam or the auxiliary beam once done is held up to a certain range for any azimuthal angle to liken of a circular crown (see figure 2-5-4-b). It is also possible to preset for having the combination of the manual and memorized switching in a sort of overlapped map having established that the stronger attenuation between the two will drive the beam selection (see figure 2-5-4-c). The difference beam is obtained suitably attenuating and dephasing the main beam signals in such a way to realize a steerable null in order to minimize ground clutter returns. In this way, clutter and angel rejection versus target illumination is optimised. That, is for instance, for the first few miles only the difference beam is used. Then, in order to detect low flying aircraft over clutter the auxiliary beam is used, for long-range coverage, the main beam is used. The automatic beam selection is performed in accordance with the following parameters: -360° of azimuth are divided into 64 sectors (each 5.6° wide); -The first half part of each azimuth sector is divided into 16 range steps (each range step is 1/32 of the maximum range). Along each of the 16 range steps and in the 64 azimuth sectors (total 1024 cells) any of the 3 possible beams can be used, according to the ground clutter and angels situation, stored in an associated memory. This memory stores for each range and azimuth sector the beam to be utilized according to the ground clutter intensity. The loading of the memory, activated by the BEAM COMBINER STORE control push- button located on the Receiver Control Panel, is accomplished in two antenna revolutions according to the following procedure: during the first antenna revolution main beam selection is forced and in all those sectors where clutter returns exceed the max processable dynamic \"I\" logic is memorized while in all others "0" logic will be memorized. During second antenna revolution in those sectors where \"I\" has been memorized the auxiliary beam selection is driven and in those sectors where clutter returns still exceed the processable dynamic a new one \"I\" logic is generated which is added to the previous one. In this way a \"10*\"* digital word is stored. Once the second revolution is over in each cell of the memory , one of the following three binary word could be memorized: 00; 01; 10 respectively representing the main, aux or difference beam selection. Main beam is always selected in the second half range; while in the first half range the auxiliary or the difference beam can be selected only if the COMB/MAIN function push-button enables this selection. The content of the beam combiner memory is preserved against temporary power failures. *RF signals Mixer and PRE-IF Amplifier* -The \"Beam Combiner\" output signal is applied to a \"Signal Mixer\", where it is mixed with the RF signal of the stabilized local oscillator (ST ALO). The ST ALO frequency is 30MHz above the magnetron transmission frequency. The \"Signal Mixer\" delivers an IF signal that is amplified by the PRE-IF AMPLIFIER; and fed to \"PACA \" circuit. 2-5-2 *PACA Function* The maximum clutter attenuation introduced by the CLUTTER FIX is about 30dB. It may happen there is still some residual clutter exceeding the 30dB of processable dynamic (see figure 2-5-9); the further attenuation (30dB) could be provided by means of traditional STC circuits, however, as clutter and clutter free areas are uniformly distributed in range and azimuth, a much better solution is an attenuation which adapts itself to the actual incoming signal. This is done by PACA. PACA circuit is composed by an IF AMPLIFIER and an STC curve and three levels of attenuation PACA I, PACA2 , PACA3 (see figure 2-5 -8). According with the clutter intensity it is possible to add or not to the STC law, one attenuation step. The STC curve (see figure 2 -- 5 -- 8) has three independent adjustments suitably positioned during setting up i.e. \- Amplitude \- Flat length \- Slope. Moreover it is possible to adjust the three attenuation levels, which allow for the best matching to the incoming signal. The PACA may operate in three different modes: -Adaptive -Programmed -Adaptive + programmed. In the first case, the selection of one among the three possible laws of attenuation is made on the ground of the RAM\'s contents being first loaded according to a principle similar to that of the CF RAMs. In the second case, the law of attenuation is selected on the ground of the PROM\'s contents being programmed in agreement with the site requirements. In the third one, is valid criterion by which the priority logic inserts onto the incoming signal the higher attenuation value. The driving resolution depends on a range-azimuth sectorization of the radar coverage. The operator switches ON the PACA function: *Phase Detector* Two phase detector circuits are used to allow the information to be converted from IF to video signals. The first phase detector is fed by the IF COHO signal; the other is fed by a 90° out of phase COHO signal. Both detectors are simultaneously fed by the IF signal. The phase detectors video output amplitude is function of the phase difference between the incoming IF signal (echo) and the COHO signal. The two outputs are in quadrature, meaning that one is a sine-type signal, the other a cosine one. Therefore, processing separately the two components through a canceller system followed by a Modulus Extractor, one MTI system that doesn\'t suffer the \"Blind Phase\" phenomenon is got. *AID Converters* -The final circuit of the receiver analogue system consists of two double 10 bit analogue-to-digital converters, which separately provide the sine and cosine (I/Q) component being converted and fed to the digital processing system. 2-5-3 Because the conversion speed limitation, two converters are used for each channel, which perform a time-sharing conversion assuring al least a total sampling rate of 1.5 per pulse width; when the main clock of the system is shorter than \>1.1µsec (i.e. A *TCR-33/44).* Only one A/D Converter is normally used in systems having a main clock \> 1.lµsec. The receiver analogue system also includes circuits required for keeping unaltered the performance of the receiver itself as, AFC and AGC. Moreover a COHERENT OSCILLATOR (COHO) with a suitable phase locking system is fitted in order to extract by the \"Phase Detector\" the Doppler information from the echoes reducing at a minimum the effect on it of the transmitter frequency instabilities, that were misinterpreted by the MTI, leading, it to misidentify fixed targets as mobile ones\" *AFC Function* - The purpose of the AFC is to keep the transmitted signal frequency constant. The AFC operates as follows: a sample of the transmitted pulse is derived from the transmitter circuitry, suitably attenuated, and converted to IF by the \"AFC Mixer\" driven by the STALO. The Output of the \"AFC Mixer\" is suitably amplified and fed to the \" AFC SYSTEM\" circuit whose output amplitude is proportional to the frequency difference between the transmitted pulse and the STALO frequency. The amplitude difference between the outputs is zero when the frequency difference is exactly 30MHz, is positive if the difference is larger and negative otherwise. The 'Error Voltage and Threshold Detector\" will thus provide an error signal that controls the frequency of the transmitted RF pulse so as to null the error and therefore keep the IF to the right value. Since if tuning were continuous, there would not be the required phase stability for the fixed target cancellation in the MTI, the AFC is enabled to make the frequency correction only if the frequency error overcomes a certain value preset by threshold circuits; the connection end is controlled by a hysteresis circuit that allows the IF to be set at 30MHz again. The AFC frequency correction must start before the frequency error becomes so large to impair the receiver sensitivity. *COHO Function* -The circuit serves to take memory of the transmitted RF pulses phase, against which compare, along the sweep,.the incoming echoes phase in order to extract in the phase detector the Doppler information necessary for MTI operation. Because the pulse to pulse phase changing of the transmitted pulses a phase locking of this oscillator take place by using the same IF signal of the AFC circuit. *AGC Function* The \"AGC\" circuit essentially consists of a variable attenuator; the attenuation is varied so as to keep the receiver noise level constant at the input of the Moving Window Integrator (1st threshold). *BITE Function* RF, IF and Video Sections are provided each one with a BITE device which generates alarms in case of failure, during ON LINE operation. *Disturbance Type Acknowledgement* The RF signal coming from the OMNIDIRECTIONAL antenna is converted by the MIXER into IF in a way similar to that of the signal produced in the BEAM COMBINER. After the amplification by an IF PREAMPLIFIER the signal is properly filtered and amplified to prevent any type of saturation to the CFAR scopes. After its detection the signal is fed to the DISTURBANCE TYPE ACKNOWLEDGEMENT circuit to obtain univocal video signals relative to the type of disturbance; and eventually it is converted into a digital form by the 8 Bit A/D CONVERTER. 2-5-4 b\. DISCUSSION OF THE FUNCTIONAL BLOCK DIAGRAM (Refer to the \"Functional Block Diagram\" shown in figure 2-5-2) \(I) BEAMS COMBINER AND BEAM SELECTOR (AUXILIARY BEAM KIT) The Analogue System input RF signals, originate from the main and auxiliary antenna beams, are both fed to the AUXILIARY BEAM KIT which performs the combined difference beam and allows the auxiliary or main beam selection. Prior being fed to the AUX. BEAM KIT both signals are amplified by a RF Amplifier (see RF System Description). As previously stated, in this unit takes place the selection among three possible beams. The main beam signal enters the 1st RF switch at 14 through a variable step attenuation whose value is preset during the set-up of the equipment in order to equalize the noise r.m.s. value of the Main Beam and Aux Beam (typical attenuation value 6dB). The RF switch allows the signal to output either through 12 or 13 depending on which \"GATE\" (A) or (C) is enabled. GATES (B) and (D) are used to connect the dummy load (50ohm) to the input 12 or 13 where the RF signal is not flowing through; this is done for matching purposes. The logic of the GATES enabling is the following: when GATE (A) is enabled, the RF signal outputs through 12, GATES (B) and (C) are inhibited while GATE (D) is enabled; vice versa if GATE (C) is enabled the RF signal outputs through 13, GATES (A) and (D) are inhibited while GATE (B) is enabled. The commands for enabling or inhibiting the GATES are generated in the CLUTTER FIX LOGIC PCB 959031-AI (XA22). As previously mentioned the combined beam either sum or difference, is realized by adding or subtracting the main beam signals to the auxiliary beam ones as it is concerned. When the main beam signals are enabled to output through 12, they pass through the phase shifter (Zl) and then through a variable step attenuator. The (Z1) phase shifter serves for making the sum or difference between main and auxiliary beam signals. Steps attenuator serves to adjust the tilt angle of the bottom edge of the combined beam. The main beam signal enters the Hybrid Power Coupler HY1 through 12 while through 11 enters the auxiliary beam signal. In the HY1 the beams combination take place it could be sum or difference depending on the phase shifting produced by Z 1; i.e. in phase equal sum beam while opposite phase equal difference beam. The output of HY1 is 13; 14 is an output for matching purpose (load ATI). The combined beam is fed to the second RF switch through 13 input, the second input of which (12) can be the main beam signal on condition that GATE (C) of the first RF switch and gate (A) of the second one are enabled. With the two RF SWITCHES is so possible to perform the selection of one of the three available beams according to the following table: --------------- --------------- --------------- ----- ----- ----- ----- ----- ---------------- 1st RF SWITCH 2nd RF SWITCH SELECTED BEAM GATES GATES A B C D A B C D ON OFF OFF ON OFF ON ON OFF DIFFERENCE/SUM OFF ON ON OFF OFF ON ON OFF AUXILIARY OFF ON ON OFF ON OFF OFF ON MAIN --------------- --------------- --------------- ----- ----- ----- ----- ----- ---------------- 2-5-5 In the RF SWITCH and DRIVER also there are LINE RECEIVERS for translating the twisted pair in one wire signals; wire wrap switches SI-S2-S3-S4 has been foreseen for receiving TTL command, (no twisted pair) directly from an eventual driving card. For receiving twisted pair commands, (1-3) linkage of the above switches must be performed. The selected beam signal outputs the AUX. BEAM KIT through J4 and is fed to the PRESELECTOR FILTER. \(2) CLUTTER FIX LOGIC PCB (XA22) As previously mentioned, the beams selection can be performed either by a program suitably stored in RAM or by manual presetting made by wire wrap switches. Concerning the operation of this PCB two main phases of operation can be identified: -RAM Program Store -Driving phase with the generation of those signals (commands) to be sent to the RF switches to perform the already explained beams selection. ( *a) RAM Program Store* To make possible the store of the CF LOGIC PCB placed in (XA22), the IF /RF C.F. Selection pushbutton of RCVR Control Panel must be preset to RFCF Selection ON (ICFIT to \"1\") because the beam selection is performed according to a map of sectorization (1024 cells), a decision on the beam to be selected must be taken in relation to the average clutter intensity measured in each cell. This measure is done by counting in each cell the number of clutter returns which amplitude overtakes the maximum MTI processable dynamic. At the end of each cell (more details will be supplied in the Sectorized Devices Description) a comparison against a threshold is performed and only if the counted value is greater than the threshold, information of high clutter is memorized. The processable dynamic crossing counter is placed in the CLUTTER MAP PCB and will be discussed in paragraph 2-7 of this Section; the binary output of this counter (signals TOMAT00 thru 11) arrive at A input of the PCB under description. Then, activating the CLUTTER FIX STORE control push-button, TOMAT00 thru II binary data represents the crossing of the processable dynamic being measured in each cell. Starting from the first North crossing since the activation of the STORE, NOZAF gate is generated which lasts the full first antenna revolution; by the STORE activation a \"\~\" logic level (CLUFIX5 = TIEBIX) signal which lasts 3 antenna revolutions is also generated. The signal CLUFIX5 inhibits the Half Range Law Selection made by S7 and S8 while signal NOZAF per- forms an inhibition of the MPX (A) forcing a 00 data output, which is fed to an adder which performs the sum between this data and the logic level outputting the comparator (LOFIF). The 2 bit data outputting the adder is fed to the LATCH (A), for the registration with the clock BIZAT, which take place almost at the end of each cell exactly at 38.5Cp of each cell during the last sweep of each azimuthal sector. The registered data is fed to the RAM for the memorization, which is performed, with the (read/write) R/W Clock RIGET01. 2-5-6 The azimuth (ZALEF00 thru \~7) and the range (FOZAF, FEZAF, FIZAF, FUZAF) ad- dresses perform the memory cell address for the memorization of the clutter data. During the first antenna revolution a binary combination 01 could be memorized in tile RAM whenever the output of the comparator, LOFIF, is \"1\". As the first antenna revolution is over the signal MOZAF ends, allowing the ENABLE ful1ction on the MPX (A); so during the second revolution in all those cells where 01 has been memorized the auxiliary beam is selected. Obviously if there are cells where the clutter still exceeds the processable dynamic, from the comparator a \"1\" logic LOFIF is got which adds to the previous data. The Output of the adder will have the configuration 10, which through the MPX (B) is fed to the LATCH (A) for the registration by clock BIZAT. This new data is then memorized into the RAM by clock RIGET01. During the third antenna-revolution the selection of the beams take place according to the table 2-5-1. In all those cells, where the difference beam is selected during the third antenna revolution, and the clutter still exceeds the processable dynamic, signal LOFIF is generated thus the data being memorized will be II. The last data configuration doesn\'t affect the beam selection because, as previously mentioned, only three modes of selection are available. At the end of the third antenna revolution, an end store signal NIZAF, is generated, which reset the signal CLUFIX5 = TIEBIX. The beam program automatically memorized in RAM can be manually modified. Infact, activating the MANUAL STORE control in the BITE and DISPLAY PANEL, the binary combination SIPAT03-04 preset by the switch S3-S4 is memorized in the cell addressed by the thumbwheels. The MANUAL STORE occurs via MPX (B) by means of signal SELAF that drives the selection o f signal SIPAT03-04. In coincidence with the last sweep of the addressed azimuth sector and closed the end of the addressed range sector, a write clock RIGET01 is generated to memorize SIPAT data in the RAM; as this operation is carried out the manual store level SELAF is reset. Since the beginning of the forth antenna revolution signal CLUFIX5 enable the Half Range Selection S7, S8 thus forcing the binary data selection by MPX (A) addresses. The MPX (A) outputting data is fed to OR functions (A) and (B) whose output is fed both input \~ of MPX (C) and to OR functions *(C)* and (D); the outputs of which is fed to input 1 of MPX (C). By OR function (C) and (D), an overlapping of the gates generated by MONO 1 and MONO2 to the data coming from OR (A) and (B) is made, in such a way that the resulting data combination is that one which greatly affect the clutter attenuation by suitably addressing the beam selection. Input 2 of MPX (C) receives the MONO1 and MONO2 Outputs directly, while input 3 is unconnected. MPX (C) outputting data is that forced by the selection made by \"Function Selector\" 53- 54-55-5 *11;* this 2 bit data is fed to LATCH (B) previous the encoding of the combination 11 in the 19) combination. The registration is made by clock FILAF01 which take place at half of the third clock (fc) since the beginning of each range sector (se\~ figure 2.:.-2-4 sheet 6). LATCH (B) is cleared either by signal MAINCO5 or the half range gate GAZAT. Every time the above register is cleared, main beam selection is performed, this done either manually by MAINCO5 or by GAZAT or by means the two bit data from the MPX (C). 2-5-7 LATCH (B) outputting data is encoded previous being fed to LATCH (C) in such a way data 00 after the clearing of it, assumes the configuration 01 which represents Main Beam Selection. LATCH (C) registers the data by clock DUZAT which active edge take place every beginning of a range sector. By the last registration it is recovered one range sector of advance due to the RAM address so having the data for beam selection in phase with sweep going on. LATCH (C) is cleared either by VELEF (or RAPMT) and it takes place every time, the Aux Beam noise measurement is performed. Signals FAFIT -MAFIT -SEFIT -ATFIT are fed to the RF SWITCH and DRIVER by twisted pair wires. Control F ANRS when activated (\"0\") enables signal GAF A T to force, via OR logics (A) and (B) or (A), (B), (C), (D), the inputting data to MPX (C) to assume the combination 11 which, if selected in the MPX (C), will select combined difference beam. The presence of FANR5 control only performs the selection of the aux beam. Jumpers S14 and S17 have been foreseen to allow the operation of C. FIX LOGIC in order to operate a sort of control on the detected False Alarms in absence of FAN circuit. Infact, in such event S14 must be not connected while S17 must be linked; activating in this condition FAN VS control, difference beam will be selected reducing so the sensitivity of the radar toward the sources of possible false alarms. When on RCVR Control Panel ANTIANGELS REJECTION function is inserted, CLOCKS AND GATES GEN PCB generates signal FUGET. This signal, on the CLUTTER FIX PCB, is used to insert auxiliary beam in the second half of sweep thus providing a reduction of "angels\" disturbances. \(3) IF CONVERSION AND AMPLIFICATION The RF signal processed by AUX. BEAM KIT is applied to the input of the PRESELECTOR FILTER, in order to ensure that signals and jamming at the receiver image frequency do not de- grade the overall receiver performance. The filter rejection at the image frequency is more than SO dB and its Bandwidth is approximately 9 MHz, centred around the transmitted frequency. The preselector filter is tunable because the FAST FREQUENCY CHANGING FACILITY. So it receives the two command signals FREQUENCY INCREASE and FREQUENCY DECREASE and outputs the PRESELECTED FREQUENCY SIGNAL and the OSCILLATOR GROUP SELECTION SIGNAL to indicate respectively when the desired frequency has been engaged and which OSCILLATOR Group's oscillator must be enabled. The filtered signal is fed through a CIRCULATOR to a balanced MIXER to be converted to IF; the MIXER consists of two crystals and a hybrid coupler. Hybrid coupler allows the STALO signal to be fed with both crystals, which are mounted one reversal of the other, while the crystals represent the non-linear element for heterodyne process between STALO and echo signals. The \"balanced\" type MIXER is used to reduce the noise due to the STALO. The IF signal, is fed to the IF-MTI and PRE-IF AMPLIFIER. The section PRE-IF AMPLIFIER consists of PASS-BAND FILTER followed by a multi- stage AMPLIFIER, and of POWER DIVIDER, which gives two output one of which (13) serves for test when an analogue Performance Monitor is fitted. The output impedance is 50ohm. The PRE-IF AMPLIFIER bandwidth is about 20MHz centred around 30MHz, while the gain is about 30dB. A gain adjustment (R13) is also provided. 2-5-8 (3A) 30 MHz DISTRIBUTOR The output from the PRE-IF AMPLIFIER (J2) is sent to the input (J5) of the circuit 30 MHz DISTRIBUTOR (A7) and reaches a HYBRID COMBINING device, at the second input of which (J6) it arrives a stimulus signal for testing the functionality of the assembly itself. The operational signal or the stimulus one, in output from the HYBRID device, reaches a 30 MHz pass-band filter having a 6 MHz bandwidth and 3 dB attenuation. At the filter output there is a power DISTRIBUTOR that subdivides the output signal into the following four lines: one is fed to a 670 KHz narrow band active filter whose gain of 13.5 dB is adjustable by R148, the other three lines are fed to as many wide band amplifiers whose gain is adjustable by means of R16, R29, R83 respectively for the outputs J1, J2 and J3. The output 11 of the 30MHz DISTRIBUTOR is fed to the strip PACA, while the remaining three outputs J2, J3 and J4 are utilized t o identify the type of disturbance. ARK Assy performs this function. 2-5-8A/2-5-8B \(4) PACA (Sectorized STC Function) The IF signal, at the output of the PRE-IF AMPLIFIER, is sent to the PACA strip. Within this device, is performed a signal attenuation according to one of the following laws of attenuation: -STC + PACA1 -STC + PACA2 -STC + P ACA3 The significance of these laws (see figures 2-5-8) is to insert onto the clutter being considered within each cell, a gain inversely proportional to the amplitude of the clutter itself, so as to obtain the following: -if the clutter is strong, it is attenuated to avoid any target masking phenomena; -if the clutter is weak, all echo-information coming from the given sector are amplified to a great extent. This action occurs in the DIODE ATTENUATOR, which is driven by one of the three DIODE ATTENUATOR DRIVING LOGICS, whose selection is made by the signals BAGET1 thru 3 whose function is to select the ANALOG MPX inputs. The gates BAGET1 thru 3 are generated within the CLOCKS and GATES GEN. Two modes are available to generate gates BAGET1 thru BAGET3: \- Thru PROM (PACA-programmed type) -Thru RAM (PACA-adaptive type). 1\) *Generation of PACA gates thru PROM* This function is developed by means of PROM\'s and is programmed on the ground of the clutter maps of the radar site. In the operational phase, the ZALEF 02 thru 07 (azimuth) and FOZAT-FEZAT-FUZAT- ZIZAF (Range) addresses are sent to the PROM, which generated therefore, a 2-bit data. With S3-S4 at 1-2 position, the 2-bit data enters an OR and PRIORITY and DECODING LOGIC, wherein, in case of simultaneous utilization of PACA-adaptive and programmable type, is performed the choice, between two laws, of the law introducing the higher attenuation onto the signal. During the BITE cycle the above LOGIC is disabled while is enabled from RCVR Control Panel, when inserting PACA ON. The PRIORITY and DECODING LOGIC outputs a 3 bit data, which after the LINE DRIVERS becomes BAGET 1 thru 3. 2\) *Generation of PACA gates thru RAM (optional)* To operate in such configuration RAMs provide the value of attenuation. The RAM loading process occurs during three antenna revolutions. The circuitry has been designed to avoid simultaneous loading of PACA and C.F. memory; therefore, by means of PACA/RF C.F. pushbutton, the selection of the memory to be loaded is chosen. Then by activating the CLUTTER FIX STORE pushbutton, common either for PACA or RF C.F. storage process, the loading is initiated. The end of storage process occurs after three antenna revolutions and the operator is informed by the splitting of the pushbutton lamp from yellow to white light. 2-5-9 PACA/RF C.F. pushbutton generates selection signal ICFIT which assumes value \"1\" if PACA storage is selected and \"0\" if RF C.F. is selected furthermore, as soon C.F. STORE pushbutton is activated, signal CLUFIX is generated which assumes \"0\" only for three antenna revolutions. From signal CLUFIX, enabled by ICFIT, signal RIGET02 (\"0\" level only during three antenna revolution), is generated in the CLOCK AND GATES GEN. PCB utilized in the CLUTTER FIX LOGIC PCB. BIGEF represents the signal information, which is taken into account by an accumulator located on the CLUTTER MAP PCB if the incoming signal is too strong to be processed linearly. A comparison of the accumulated data (TOMAT00÷2) with a threshold reference adjust- able by means of S I-S2 is executed in CLUTTER FIX LOGIC PCB; the result of comparison, through MPX (B) and LATCH (A) is written in the RAM suitably addressed. During the next antenna revolutions, this process is repeated and again, the output of comparator, added to the value stored in the RAM during the previous revolution, is stored in the RAM. The RAM storage cycle is in coincidence of the end of third antenna revolution. During the three revolutions signal RIGET02, through AND GATE (1) forces the selection of MPX (A) to \"0\"; thus RAM output is selected. During 1st antenna revolution, the output of MPX (A) is inhibited by both signals LOFAF and RIGET02. Write signal RILAT for RAM is enabled by ICFIT during all the storage process. When in operative condition, jumpers available in the pcb must be set according to following criteria: S7 -S8 to 0 in order to select the RAM\'s output S14-S17 to 1 S5 --S11 to position 1-3 S3-S4 to position 1-2 In such condition signals MAFIT and ATFIT are generated which allow for the implementation of PACA, adaptive mode. Furthermore: S6-S9 must be set to position 1-2 S 18 to position 1-3 S10 open S20 to position 1-3 Signal GAZAT forces STC law in the second part of the sweep. Other configurations of jumpers are used for test purpose only. \(5) IF-MTI Function It is used to amplify the IF signal at a suitable level for the PHASE DETECTORS (1Vpp). To this purpose, are provided within the AMPLIFIER three adjustments: -R46 gain adjustment -R36 dynamic adjustment -R53 output signal amplitude adjustment. 2-5-10 In particular R46, enables a gain adjustment of ±5dB with respect to the nominal 47dB. R36 is to be adjusted by a dynamic value such as to obtain a limitation of nearly 5dB below the max input signal, so as to recover, with respect to a non-adaptive analogue receiver with a linear-limited characteristic, in terms of SCV. R53 regulates, instead, the max amplitude of the nominal output signal (1Vpp). Even the AGC function is obtained through the signal coming from AGC LOOP PCB, the output signal is kept constant, by modifying ±3dB over the input signal A sample of amplified signal is detected (ENVELOPE DETECTOR) and, after comparison with a threshold (R65), generated the CUSET signal. This signal, being registered with COTIT0\'4, into the CLOCKS AND GATES GEN generates BIGEF, which is used to load the RAM of the CLUTTER MAPPER PCB. \(6) PHASE DETECTORS FUNCTION The IF signal, being amplified, is subdivided into two components (sine, cosine) and one of them is phase-shifted of 90°C with respect to the other one Each component is detected in phase and amplitude in the AMPLITUDE-PHASE DETECTOR, which receives the reference COHO signal In the final check phase, is being provided a BALANCED ADJ (R28-R29) The two video components, thus amplified, are moreover processed in the PACA strip The PHASE DETECTOR characteristics is shown in figure 2-5-7 \(7) PACA (Matched Filter Function The two sine-cosine components with ±1V amplitude are filtered into the MATCHED FILTER, placed within the PACA. This filter is used to maximize the signal-to-noise ratio at the output of the strip. Each video component, prior to being processed within the A/D CONVERTER, is amplified in the DC AMPLIFIER. The PACA contains also a RAMP GEN for the A/D CONV OFF LINE check This way, S2 will be set at RAMP ON position The RAMP GEN is capable to engage all levels of the echo in- formation being available. Moreover, is used an MPX, through which, at each starting sweep, is performed a blanking upon the signal, during which the OFFSET value is stored. This value is subtracted in the overall sweep length (range bin by range bin) from the information relevant to the NORMAL signal. \(8) 10-BIT *A/D CONVERTER* *(a) General Information* The 10-bit AID Converter is used to convert the analogue video data in digital form using the binary code; the Digital Processing System then processes the binary information. 2-5-11 *(b) Theory of Operation* The analogue video signal is sampled and stored within each range bin; thus a 10-bit binary word is also generated within the same interval with successive approximations. The binary would is reconverted to analogue form and compared to the above-mentioned sampled video signal to refine the digital approximation to the sampled analogue video. The comparator output signal causes the generated binary word to the updated in order to have the signal output, in digital form, very approximated to the analogue signal sampled at the scanning of each range-bin. The standard conversion time being utilized by the A/D Converter is nearly lµsec. When the radar sampling clock is lower than lµsec *(ATCR-33144),* are used two A/D Converters, which operate in time-sharing. Figure 2-5-10 and table 2-5-4 shows any possible use of the A/D CONVERTER within the radar. *(c) Technical Description* Figure 2-5-2 shows the 10-bit A/D Converter composed by two conversion boards, named BASIC BOARD and EXPANSION BOARD. For the sake of simplicity, the description that follows refers to only one of the two A/D converting plates. Referring to figure 2-2-2, it can be seen that the converter inputting Video Signal is fed to SAMPLING SYSTEM. This system performs a function like that of a normally open switch, whose contacts closes with the SAMPLING PULSE, which lasts about 50nsec. The sample of the analogue video is then stored in a HOLDING CIRCUIT the output of which is directly connected to the inverting input of the COMPARATOR. The clock obtained by combining the clock ADGET01 and the sweep trigger PUGET02 in turn drives the SWITCH "ON" ENABLING CIRCUIT. The above clock is also differentiated, inverted then used to: -START the CLOCK GENERATOR -RESET the ENABLING LOGIC OF THE SERIAL BIT GENERATOR -SET the MSB (Most Significant Bit) internally to the 6 BIT SERIAL GEN. -STORE the Binary Word in the END CONVERSION REGISTER. Consequently of the RESET operation, the available binary word corresponds to the dynamic midrange (1000000000)*;* the word is fed to the 10-BIT A/D CONVERTER whose analogue output (namely +2.4V) is then fed to the not-inverting input of the COMPARATOR. From the COMPARATOR it is obtained information having the following meaning: -high level \"1 \"; the binary word is greater than the sample of the analogue video; -low level \"0\"; the binary word is smaller than the sample of the analogue video. Therefore, because the conversion take place with successive approximations, the COMPARATOR outputting level is fed to a set of AND LOGIC that provide to revoke one at time those bit which set-up gives a binary word greater than the stored sample. Table 2-5-3 shows a typical sequence of the successive approximation during the A/D conversion. The encircled (\" 1 \") are those revoked because their binary weight is greater than that necessary for the approximation. 2-5-12 The process of Bit Generation and revoke take place as follows: As previously stated with the RESET operation tile MSB is set-up, and the CLOCK GENERATOR is excited, thus after one period of the Oscillator the first internal clock is applied to the ENABLING LOGIC OF THE SERIAL BIT GENERATOR. Consequently a clock outputs this logic which is used to set-up the 2nd Bit and at the same time is fed to the AND LOGIC whose output may RESET (Revoke) or not the MSB upon the logic level outputting the COMPARATOR. When the second internal clock generation occurs the third bit of the 6 BIT SERIAL GENERATOR is set-up while the 2nd bit revoke can be performed if necessary. The process of conversion goes on upon to the l0th bit generation and eventual revoke then stops. At the end of the converting cycle by means the next sampling clock the digital word is registered in the END CONVERSION REGISTER and then output through a MPX and REGISTER. The MPX alternatively outputs (over one range-bin time) the 10 binary word of the BASIC BOARD and the word coming from the EXPANSION BOARD. The first data to be outputted is that converted by the EXPANSION BOARD as is shown in figure 2-5-11 which represents a complete A/D CONVERTER TIMING. Figure 2-5-10 together with table 2-5-4 helps in understanding the system connections of the DUAL 10 BIT A/D CONVERTER. \(9) OSCILLATOR GROUP, BY -M MULTIPLIER, BY -2 MULTIPLIER (STALO FUNCTION) The Oscillator Group and the BY -8 MULTIPLIER together with the BY -2 MULTIPLIER contain the basic devices that accomplishes the STALO function. The Oscillator Group generates a frequency than multiplied in the BY -8 MULTIPLIER and BY -2 MULTIPLIER is used to generate a signal with a stabilized frequency equivalent to the ±30 MHz frequency of the transmitted RF pulse. This signal is utilized within the MIXER as carrier frequency to obtain, through modulation with the echo-signal, a 30 MHz IF signal. According to the magnetron frequency being selected in the S-band frequency range, even the STALO frequency varies so as to obtain: STALO - f transmitted RF pulse = constant = 30 MHz The STALO function is thus realized in the following units: -Oscillator 815721 Combiner 815731 OSCILLATOR GROUP Bite 815751 247433-Al (CH.A)/247433-A2(CH.B) -By-2 Multiplier 816241-A2 -341 thru 361 MHz filter 815001-A2 -By-2 Multiplier 815011-A2 -682.5 thru 722.5 MHz filter 815021-A2X -By-2 Multiplier 815031-A2 X 8 MULTIPLIER -1365 thru 1445 MHz filter 815041-A2 *236228-A5* -1365 thru 1445 MHz amplifier 815051-A2 -BITE 811131-Al -6 dB Coax Attenuator 76X165 P00l -By-2 Multiplier 221981-A2 2-5-13 Here is then reported a brief description of each unit: *Oscillator Group* The circuitry includes six OSCILLATORS, of which only one at a time is enabled to oscillate in function of the 6-wire signal OSCILLATOR GROUP SELECTION SIGNAL with a ground level. The outputs from the six Oscillators arrive to a COMBINER where the signal amplitude or each Oscillator may be finely adjusted to obtain at the output J I a value or +6 dBm. A sample of the signal is withdrawn from the COMBINER and utilized for purposes of BITE checking. After its detection the signal is compared with a threshold adjustable by R3. When the power of the output signal at J 1 of the COMBINER is the nominal one (+6 dBm), at the FAILURE OUTPUT there will be a logic level \"1\", if instead the power is less than + 3 dBm there will be present a logic level \"1\". The FAILURE OUTPUT signal is sent to the BITE AND ANALOGUE VIDEO PROCESSING circuit of Fig. 2-5-2, Sheet 4. The quartz list being available is reported in the volume relative to the \"Electrical Parts list\". *By-8 Multiplier* 1st BY -2 MULTIPLIER It operates according to the principle of the double semi-wave rectifier. The outgoing waveform, mainly of 2nd harmonic, is filtered into the TUNED AMPLIFIER. -341 *thru 361MHz filter* It operates as further filtering. *-2nd BY-2MULTIPLIER* It consists of two biased amplifier stages; a proper ratio between the input signal level at each stage and the bias voltage produces mainly 2nd harmonic signals, in the outgoing waveform. -682.5 *thru 722.5MHz filter* (635 *thru 695MHz filter}* It ensures, in conjunction with the other filters, the desired STALO selecting. *-3rd BY-2MULTIPLIER* It operates similarly to the 2nd By-2 Multiplier. \- 1365 *thru 1445MHzfilter* (1270 *thru 1390MHz)* It contributes to obtain the desired selectivity. -1365 *thru 1445MHz amplifier* (1270 *thru 1390MHz)* It allows to obtain at the output of the By-8 Multiplier a + l3dBm level. -6 *dB Coax Attenuator* It makes the power suitable to Mixers input. *-By-2 Multiplier* It converts the frequency in to the S-band frequency. 2-5-14 The block diagram shows adjustments and test-points that are utilized only in the test performance at the strip bench input/output impedance of the strip, which is 50 Ohm. \(10) Automatic Frequency Control As earlier explained in the previous paragraph, the automatic frequency control function has the aim of referring the transmitted frequency to the frequency of a highly stable local oscillator (STALO), in order, for the IF circuits are part of the analogue processor, to achieve their optimum performance. A directional coupler contained in the RF system provides a sample of the transmitted signal to be compared with a portion of the STALO output signal, on a MIXER. The result of the comparison is an IF signal, 30MHz being the difference between tile instantaneous magnetron output frequency and the STALO frequency. The mixer output is applied to the input of the AFC-IF amplifier; the amplified signal is used to generate a lock pulse that becomes (see description further down) the reference input for the coherent oscillator (COHO). The Lock Pulse, besides fed to the above-mentioned circuits, is also brought to test point El of the AFC amplifier for maintenance purposes. The output of the 30MHz WIDE BAND AMPLIFIER stage is fed to a BUFFER AMPLIFIER whose outputs drive four IF amplifiers tuned to four different frequencies. The purposes of the AFC-IF AMPL stage is that of providing an error voltage with an amplitude proportional to the difference of the frequencies compared in the MIXER, and whose sign output J5-J4 depends on which way the transmitted frequency is displaced with respect, to the STALO reference frequency. The four amplifiers are tuned to 19,29, 31; and 39MHz respectively. The filter outputs are detected, inverted, and added together so to obtain an equivalent voltage of J5-J4 according to figure 2-5-5. The centre point of the response shown in figure 2-5-5, corresponds to the nominal 30MHz frequency value corresponding to zero error voltage; the limit frequencies, A and B, determine (depending on the nominal frequency deviation) the interval over which the automatic frequency control is operate (pull-in range). The minimum pull-in range is ±7MHz around the centre frequency. The CROSSOVER adjustment made by R23 aims of making the AFC response balanced respect the IF (30MHz) value. The Lock Pulse previous being sent to the COHO is amplified for phase locking error reduction; the level of the lock pulse signal can be adjusted by C81. The DIFFERENTIAL AMPLIFIERS contained in the AFC DIFFERENTIAL AMPLIFIER unit are used to get high sensitivity to error voltages appearing at their inputs. As soon as the error voltage reaches the amplifier intervention threshold, relay K1 (or K2) is energized. The relays (that operate on the magnetron as explained further on) stay energized until the error voltage has decreased below the amplifier intervention end threshold. The intervention threshold values can be adjusted both ways by means of R3 and R 13; the hysteresis (end threshold) is adjustable by means of R8 and R 19. In the absence of manual control, the energizing of K I (or K2) causes a ground voltage available at one of the (two) outputs; the voltage is brought (via the control panel) to the Magnetron Gear Box and allowing supply for a motor connected to the Magnetron tuning cavity. The mechanical deformation of the cavity produces a change in the magnetron transmission frequency. The operation continues until the difference between the magnetron frequency and the STALO frequency drops below the AFC differential amplifier intervention end threshold, thereby deenergizing the relays. 2-5-15 If the system is under manual control (function MFC activated} and the error voltage is allowed to drift outside the pull-in range, the operator is alerted by the lighting of the PULL-IN RANGE indicator lamp on the Control Panel. The manual controls located on the receiver Control Panel allow the motor contained in the Magnetron Gear Box to be set in motion so as to bring: the error voltage back within the AFC pull-in range (as indicated by the indicator lamp going off). The lighting or the corresponding lamps on the Receiver Control Panel indicate the intervention of the AFC. Values C and D 011 the response curve are higher than the intervel1tion thresholds, to prevent the AFC system from trying to lock-in on them. Through a FILTERING AND DECOUPLING NETWORK, it is possible to check the AFC MIXER crystal current by means of a meter when fitted. \(11) Coherent Oscillator The COHO circuit outputs the IF signal, phase-Locked with the transmission pulse signal, required by the PHASE DETECTORS to phase-discriminate the radar returns. The operations that will be described in the following are repeated once per sweep. A PULSE FORMER is set by ROLET (start sweep trigger), through a LINE RECEIVER and a DELAY. In this condition the LOCK PULSE is enabled to pass through the MODULATOR and reaches the OSCILLATOR for phase locking purpose. Both the DELAY and PULSE FORMER can be adjusted in order to eliminate transmission pulse instabilities present in the tail of the LOCK PULSE. A switch selector S I is used to enable (COHO OFF position) or inhibit (COHO ON position) the locking-in phase of the OSCILLATOR by the LOCK PULSE. The OSCILLATOR output frequency can be adjusted to exactly 30\~\[Hz by means of variable capacitor C42; C38 is used to adjust the amplitude of COHO signal. All the adjustments shown in the block diagram, C42 excluded, are internal adjustments used for bench final alignment. The MODULATOR GATE and COHO GATE can be checked to J5 and 6 of strip, respectively. The output of AMPLIFIER is fed to DIRECTIONAL COUPLER. One output supplies the DIVIDER and MODULATOR; the last one suitably driven by a PULSE FORMER AND DRIVER, gives a pulsed phase-locked IF TEST signal. The other output of DIRECTIONAL COUPLER, through a comparison with a THRESHOLD PRESET, gives an ON LINE ALARM (COBIT) when COHO signal goes below the pre- set threshold. \(12) BITE Function The RCVR Analogue System is provided or a BITE facility that generates ON LINE ALARMS if any failure occurs within the main devices or the system. A BITE facility OFF LINE is provided too. I\) ON LINE BITE The following parts are checked automatically without interrupting the operative condition: -BY -8 MULTIPLIER and BY -2 MULTIPLIER (if fitted) -- COHO -Part of PACA (part of CLOCKS and GATES GENERATOR included) -Part of IF MTI and PIF -PHASE DETECTORS -1st and 2nd (if fitted) A/D CONVERTER. 2-5-16 The ON LINE checks give right information only if the related thresholds have been correctly preset during OFF LINE alignment of the system. -BY-8 MULTIPLIER and BY-2 MULTIPLIER (if fitted). An ALARM signal GIGET (digit: 19 displayed on BITE display) is generated whenever the BY -8 MULTIPLIER OR BY -2 MULTIPLIER falls 6dB below the nominal level (+13dBm). IfBY-2 MULTIPLIER is not fitted; S l of CLOCKS and GATES GENERATOR must be set to ground. Processing the STALO signal through a DIRECTIONAL COUPLER, an ENVELOPE DETECTOR and a COMPARATOR which threshold adjustment is done by R6 generates GIGET. -COHO An ALARM signal COBUT (digit 17 displayed on BITE display) is generated whenever the COHO output falls 6dB below the nominal value (+10dBm at J2). -PACA The PACA is partially tested ON LINE. Part of CLOCK and GATES GEN is tested ON LINE too through the same ALARM logic. An ALARM signal GOGET (digit 20 displayed on BITE display) is generated whenever one or more DRIVING ATTENUATION LOGIC generating PACA LAW1 - LAW2 - LAW3 are failed. Gate DAUNF disables the PRIORITY AND DECODING LOGIC while SAUNT0l generates the PACA gates thru 03. Only one gate is enabled within one sweep if a so selecting one of the three DIODE ATTEN. DRIVING LOGIC. The signal, outgoing from ANALOGUE MPX, through a COMPARATOR, generates signal PABIT used as clock in the P ACA test SIGNAL GEN. On rate, one pulse for each law (1-2-3) is generated. If one or more of the PACA LAWS are not enabled, GOGET remains at high-level so generating an ALARM. R48 (BITE TH. ADJ.) must be preset so as to have A\>B even in presence of the lower PACA law. A possibility of check OFF LINE of PACA gates is also provided (BEGET signal). -IF MTI and PIF Only the IF -MTI section of the strip is tested ON LINE. By means of OSFUT, BITE QUARTZ OSCILLATOR is enabled to oscillate. The test signal, suitably amplified, is injected in the IF -MTI section thus providing a video signal which is compared with a threshold. The resulting signal IF BIT represents the BITE information for the display of ALARM (digit 18) when the strip gain decrease of 3dB with reference to the nominal gain (47dB). 2-5-17 -PHASE DETECTOR The same TEST signal generated by IF -MTI and PIF is utilized in PHASE DETECTOR in order to provide BITE ALARM signal DEBIT. This signal is generated if one or both quadrature components decrease of 6dB. Digit 21 is displayed as consequence of FAILURE. -1st A/D CONV. The same TEST signal generated by the IF -MTI and PIF is also used for ON LINE check of *AID* CONVERTERS. The IF signal through the PHASE DETECTORS becomes a video signal of ±l Vpp amplitude. This signal, delivered to the A/D CONV., engages all 10-bit A/D CONV dynamic. If some bit is missing due to a failure within the A/D CONV, the top or bottom preset threshold is not overcame, an ALARM signal is generated in order to display digit 21. -2nd A/D (optional) The ON LINE check operates as the 1st A/D CONV ON LINE Check. In case of ALARM, digit 23 will be displayed. 2\) OFF LINE BITE In order to make an OFF LINE check of the RCVR Analogue System some facilities are provided i.e.: -IF TEST signal -RAMP generator -TEST PROM -IF TEST signal This IF TEST signal is generated in the COHO strip. By using this pulsed coherent TEST signal a step-by-step check of the whole Analogue System can be carried out. Such a TEST signal, by using a MIXER and a CIRCULATOR both available within the Analogue system, is suitable to create a RF pulsed TEST signal which can be used for RF parts of the radar checking purposes. The IF TES1= signal is 600mVpp/50ohm while the duration can be adjusted by R79 of COHO strip. -RAMP generator PACA strip contains a RAMP generator for OFF LINE testing purposes of A/D CONV. The RAMP generator starts with the P*ACA* delayed trigger. The slope is adjusted by R76 while the amplitude is stopped when the RAMP reaches +2Vpp. To utilize the RAMP signal, S2 must be set to RAMP ON. 2-5-18 \- TEST PROM A TEST PROM, located in the PRIORITY and DECODING LOGIC of GATES and CLOCKS GEN., is provided in order to check OFF LINE the PACA PROM\'s contents. Such a TEST PROM, through a LADDER, gives information of the PACA gates being selected. The information, once J 1 -9 has been connected to J 1 -24 of CLOCKS and GATES GEN. is suitably amplified in order to provide BEGET signal to PPI. The less or more intensity of BEGET, displayed on PPI, makes the maintenance personnel capable of individuating which PACA gate is being enabled by PROM\'s content. \(13) DISTURBANCE TYPE ACKNOWLEDGMENT This function, mainly performed by the ARK Assy illustrated in Figure 2---5---2, Sheet 1, is achieved by properly processing the IF signals of the OMNIDIRECTIONAL Channel and DIRECTIONAL Channel. Both IF signals are fed to two distinct 30 MHz DISTRIBUTORS (815691-AL designated respectively as A---15 and A---7 in the illustration): they are described in Para. 2-5---8(4). The narrow band filtered outputs (J4) and the wide band ones (J2) are sent individually to as many LOG AMPLIFIER AND DETECTOR circuits to amplify the signal with a logarithmic characteristic that is known to prevent the saturation even of very strong signals. Besides it is generated a malfunction indication for every individual block of the assembly. The wide band output (J3) of the assembly *A---I* is sent to a DICKE FIX (DF) circuit having the property of producing at its output, even under conditions of constant CFAR, a signal with characteristics such to eliminate the wide band disturbance. From the analysis of the signal in output from the DF it is possible to acquire the informa­tion on the type of disturbance, WB or NB as described in Para. DISTURBANCE SUPPRESSION FUNCTION, Chapter 2.6. The DF is essentially a wide band amplifier with function of hard limiting, followed by a narrow band filter and by an envelope detector: a FAULT DETECTOR circuit allows to detect the eventual malfunction of the assembly. Inside the strip there are three semi operative potentiometers and precisely: --- R32 for Output Amplitude Adjusting - R64 for Output DC Level Adjusting --- R68 for Fault threshold Level Adjusting All the signals relative to the malfunction indications for the strips 30 MHz DISTRIBUTOR and DICKE FIX, as well all the signals in output from the DOUBLE LOG DETECTOR are forwarded to the BITE AND ANALOGUE VIDEO PROCESSING circuits. 2-5-19 \(14) BITE AND ANALOGUE VIDEO PROCESSING (815711 -Al) The schematic block diagram for this function is given in Figure 2---5---2, Sheet 4. In it the following tasks are accomplished: \- Generation of the stimulus signals for the strips of the DISTURBANCE TYPE ACKNOWLEDGEMENT circuits and precisely for both the 30 MHz DISTRIBUTOR and DOUBLE LOG AND DETECTOR, in addition to the DICKE FIX for a BITE function of OFF-LINE type. \- Generation of the malfunction signal relative to the same strips and to the OSCILLATOR GROUP, in addition to that of the DIGITAL ARK (\"OR\" between them). \- Driving of the video signal with the characteristic of the LOG processing that will be selected, in accordance with the results of the analysis on the type of disturbance, in alternative to the video with the characteristic of the DF processing: then it will be sent to the selector that will perform the selection in alternative to the signal in output from the primary threshold of the MOVING WINDOW (MUMUT). \- Generation of the signals that indicate or contribute to determine univocally the eventual presence of disturbance and its type. Omitting the description of the first two functions that will be discussed in the Paragraph 2---8, this module receives in J1 the signal with the characteristic of the logarithmic processing NB LOG of the DIRECTIONAL CHANNEL; after driving by the DRIVER block the signal is issued on a 50 Ohm characteristic impedance at the J5 output, designated \"IN A\". The above-mentioned input signal is also supplied to two differentiating circuits to be compared respectively: \- With the signal of the same channel and with same characteristics of LOG processing, but wide band (J2). The output from this differentiating circuit integrated with an integrating constant adjust­able from 5 through 280 µsec by means of R8 is compared with a positive DC threshold adjustable in turn by R67. The result of such a comparison on a balanced line is forwarded to the DIGITAL ARK circuit with the designation IN C: reference is made to Fig. 2---6---5, Sheet A. The eventual presence of a WB disturbance is denoted by a \"low\" logic level, while a \"HIGH\" level occurs only if there is NB, or at limit CW, disturbance presence, inside the channel N.B., and this disturbance has such a duration to overcome the threshold even after the integration effect. 2-5-20 \- With the signal with same characteristics NB LOG but from the OMNIDIRECTIONAL Channel (J4) to generate a signal denoting, if higher than a threshold adjustable by means of R46, the possible presence of a disturbance of the type NB LOG more intense on the OMNIDIRECTIONAL CHANNEL in regard to the DIRECTIONAL one. This type of disturbance may be due to a spot type jamming if its duration is shorter than 5 µs. or to a NB type jamming when its duration is longer and the antenna is not pointing on the direction of the jammer. In the first instance with an appropriate logic the undesired signals must be cancelled and this is achieved by sending the same signal of J4 to *a* differentiating circuit that generates, in correspondence of its leading and trailing edges, two pulses with duration of about 2.5 *us.* Whenever these overcome a given threshold, adjustable with R121 and R132 they are ored in logic and sent to NAND logic with the signal of possible disturbance. The output from the NAND logic is the cancellation signal that, on a balanced line, is sent IN D output. In the second instance they will be generated only two cancellation signals with duration of about 2.5 us in correspondence of the start and end of the disturbance itself, for the cancellation of the residues due to the LOG---FTC processing. *NOTE: The logic circuits are designed in such a way that, in presence of disturbance signals due to the inherent system noise, i.e. signals of very short duration, do no; generate any cancellation signals.* At the input of the two comparators along the path of the signal OMNI CHANNEL NB LOG they are present two resistive voltage divider adjustable by means of R2 and R29 for calibration purpose. The signal WB LOG of the OMNI CHANNEL (J3) is compared with the analogous signal from the DIRECTIONAL CHANNEL, integrated as described above, and compared with a negative DC threshold adjustable by R61, and issued on a balanced line at the output designated JAMMING STROBE to denote the direction of the disturbance source. This signal, enabled only in absence of clutter (LUG ET) and regenerated by the staggered DELAYED MAIN TRIGGER (NETIT) is forwarded to the PEX as signal JAIRT. The same signal (J4), integrated in a similar way and compared with a DC positive threshold adjustable by R48, is sent, on a balanced line, to the output designated OUTPUT NOISE FIG­URE for the indication of the noise figure of the OMNIDIRECTIONAL CHANNEL.