Unit 4: Input/Output Organization PDF

UNIT 4: INPUT / OUTPUT ORGANIZATION Input & Output (I/O) Systems Functions of input output systems:  Interface to the processor and memory via the system bus.  Interface to one or more I/O devices by tailored data links. Requirements of I/O system Control and Timing The I/O modu...

UNIT 4: INPUT / OUTPUT ORGANIZATION Input & Output (I/O) Systems Functions of input output systems:  Interface to the processor and memory via the system bus.  Interface to one or more I/O devices by tailored data links. Requirements of I/O system Control and Timing The I/O module includes a control and timing requirements to co- ordinate the flow of traffic between internal resources (memory , system bus) and external devices. Processor communication CPU communication involves different types of signal transfers such as : CPU sends commands to the I/O module which are generally the control signals on the control bus. Exchange of data between the CPU and I/O module over the data bus. The status signals such as BUSY , READY. 1  Device communication The I/O module must be able to perform device communication which involves commands , status information and data. Data buffering Data transfer rates of peripheral devices are quite high than that of CPU and memory.The data coming from memory or cpu are sent to an I/O module , buffered and then sent to the peripheral device at its data rate. Also data are buffered in I/O module so as not to tie up the memory in a slow transfer operation. Thus the I/O module must be able to operate at both peripheral and memory speeds Error detection I/O module is also responsible for error detection and for reporting errors to the CPU. The different types of errors are mechanical and electrical malfunctions reported by the CPU. Block Diagram of I/O interface I/O interface consists of data register, status/control registers, address decoder and external device interface logic. 2  The data register holds the data being transferred to or from the processor. The status/control register contains information relevant to the operation of the I/O device. Both data and status/control registers are connected to the data bus. The address decoder enables the device to recognize its address when address appears on the address lines. The external device interface logic accepts inputs from address decoder , processor control lines and status signal from the I/O device and generates control signals to control the direction and speed of data transfer between processor and I/O devices. Input Output Interfacing techniques I/O devices can be interfaced to a computer system I/O in two ways: Memory mapped I/O I/O mapped I/O Memory mapped I/O  In this technique, the total memory address space is partitioned and part of this space is devoted to I/O addressing.  When this technique is used , a memory reference instruction that causes data to be fetched from or stored at address specified , automatically becomes a I/O instruction if that address is made the address of an I/O port.  The usual memory related instructions are used for I/O related operations.  The special I/O instructions are not required. 3 I/O mapped I/O  If we do not want to reduce the memory address space , we allot a different I/O address space , apart from total memory space which is called I/O mapped I/O.  Here the advantage is that the full memory address space is available.  The memory related instructions do not work.  Therefore, processor can only use this mode if it has special instructions for I/O related operations such as I/O read, I/O write. Comparison between Memory mapped I/O and I/O mapped I/O Memory mapped I/O I/O mapped I/O Memory and I/O share the Processor provides separate entire address range of address range for memory and processor. I/O devices. Processor provides more Processor provides less address lines for accessing address lines for accessing memory. Therefore more I/O. Therefore less decoding is decoding is required. required. Memory control signals are I/O control signals are used to used to control read and write control read and write I/O I/O operations. operations. 4 Types of data transfer techniques  Program controlled I/O or polling control  In program controlled I/O, the transfer of data is completely under the control of processor program.  This means that the data transfer takes place only when an I/O transfer instructions executed.  In most cases it is necessary to check whether the device is ready for data transfer or not.  To check this, processor polls the status bit associated with the I/O device.  Interrupt program controlled I/O or interrupt driven I/O  In interrupt program controlled I/O, when the peripheral is ready to transfer data ,it sends an interrupt signal to the processor.  This indicates that the I/O data transfer is initiated by the external I/O device.  When interrupted, the processor stops the execution of the program and transfers the program control to an interrupt service routine.  This interrupt service routine performs the data transfer.  After the data transfer, it returns control to the main program at the point it was interrupted.  Hardware controlled I/O  The transfer of data is controlled by DMA controller.  The DMA controller sends a HOLD signal to the processor to initiate data transfer.  In response to HOLD signal, processor releases its data ,address and control buses to the DMA controller.  Then the data transfer is controlled at high speed by the DMA controller without the intervention of the processor. 5   I/O control by handshake signals  The status of handshaking signals is checked between the processor and I/O device and when both are ready actual data transfer is initiated.  The handshake signals are used to ensure the readiness of the I/O device and to synchronize the timing of the data transfer. Interrupt Driven I/O This method provides an external asynchronous input that would inform the processor that it should complete whatever instruction that is currently being executed and fetch a new routine (Interrupt Service Routine) that will service the requesting device. Once this servicing is completed, the processor would resume exactly where it left off. This event that causes this interruption is called interrupt and the special routine executed to service the interrupt is called Interrupt Service Routine ( ISR). An interrupt caused by an external signal is referred as hardware interrupt. Conditional interrupts or interrupts caused by special instructions are called software interrupts. 6 Response to interrupt 1. The CPU recognizes the interrupt when the external asynchronous input is asserted by an I/O device. 2. In response to an interrupt a special sequence of actions are performed. 3. These are as follows : a. The processor completes its current instruction. b. The PC current contents are stored on the stack. c. The PC is loaded with the address of ISR. d. Program execution continues with the instruction taken from the memory location pointed by the new PC contents. e. The interrupt program continues to execute until a return instruction is executed (RET). f. After execution of the RET instruction processor gets the old address of the PC from the stack and puts it back into the PC. g. This allows the interrupted program to continue executing at the instruction following the one where it was interrupted. Enabling and Disabling interrupts In the processor those interrupts which can be masked under software control are called maskable interrupts. The interrupts which cannot be masked under software control are called non-maskable interrupts. Maskable interrupts are enabled and disabled under program control. 7  When masked , processor does not respond to the interrupt even if the interrupt is activated. Handling multiple devices To handle interrupts from multiple devices processor has to perform following tasks : – It has to recognize the device requesting an interrupt. – It has to obtain the starting address of interrupt service routine corresponding to interrupt request. – It has to allow the device to interrupt while another interrupt is being serviced. – It has to take decision that which interrupt should be serviced first when there are simultaneous interrupt requests from two different devices.  Vectored Interrupts  When the external device interrupts the processor (interrupt request), processor has to execute ISR for servicing that interrupt.  If the internal control circuit of the processor produces a CALL to a predetermined memory location which has the starting address of ISR, then that address is called vector address and such interrupts are called vector interrupts.  When processor is interrupted , it reads the vector address and loads it in to the PC.  Interrupt Nesting  A system of interrupts that allow an ISR to be interrupted is known as nested interrupts.  Example: Consider a computer that keeps track of the time of day using real time clock. This real time clock requests to the processor at regular intervals and processor accordingly updates the counts for seconds, minutes and hours of the day. For the proper operation such an interrupt request from real time clock must be processed even though computer is executing an ISR for another device. 8  Interrupt Priority  When interrupt requests arrive from two or more devices simultaneously , the processor has to decide which request should be serviced first and which one should be delayed.  The processor takes the decision with the help of interrupt priorities.  It accepts the request having the highest priority. Comparison between Programmed I/O and Interrupt Driven I/O 9