FET Operation and Characteristics PDF

# Circuit Symbol and Conventions * **N-channel NMOS**: * The vertical solid line denotes the gate electrode. * The vertical broken line denotes the channel. * The broken line indicates that the device is in enhancement mode. * The separation between the gate line and channel line d...

# Circuit Symbol and Conventions * **N-channel NMOS**: * The vertical solid line denotes the gate electrode. * The vertical broken line denotes the channel. * The broken line indicates that the device is in enhancement mode. * The separation between the gate line and channel line denotes the oxide that insulates the gate from the channel, usually body and source. * **PMOS**: * Direction of current is from P-type to n-type region. # Depletion MOSFET * Construction of an n-channel depletion MOSFET is very similar to that of an NMOS. * An actual channel is formed by adding n-type impurity atoms to the P-type substrate. * The gate can be positive, zero, or negative. # Operation of NMOS * Consider the following arrangement, where the drain and source are grounded, and the gate voltage is varied. * As Vg increases from zero, the positive charge on the gate must be mirrored by the negative charge in the substrate. * Another phenomenon precedes the formation of the channel: As Vg increases from zero, the positive charge on the gate repels the holes in the substrate, thereby exposing negative ions and creating a depletion region. ## Depletion Region * There is no mobile charge carrier, only immobile negative ions. * Here, no current flows from the source to the drain. * The MOSFET is off. ## To avoid current flow * To avoid current flow between the source-substrate and drain-substrate junction, the substrate itself is also tied to zero, ensuring that these diodes are not forward biased. ## What happens as VG↑? * To mirror the charge on the gate, more negative ions are exposed and the depletion region under the oxide becomes deeper. * If Vg becomes sufficiently positive, free electrons are attracted to the oxide-silicon interface, forming a conductive channel. * We say MOSFET is ON. ## The gate potential at which channel begins to appear is called the "threshold voltage"(VTH). * It is in the range of 300mV to 500mV. * Note that the electrons are readily provided by the n+ source and drain regions and need not be supplied by the substrate. ## The conductive channel formed between D and S can be viewed as a resistor. * As Vg↑, electron density in channel increases. * Channel resistance between S and D goes down. ## Channel act as a voltage-dependent resistance. ## Now apply drain voltage as shown below. ## If VG<VTH, no channel exists and device is OFF and ID=0 regardless of the value of VD. * If VG > VTH, then ID > 0. * Let us keep VG = constant and above VTH. * Now, we can vary VD. * The source-drain path may act as a simple resistor "Ron". ## How does the characteristic changes if VG↑? * Higher density of electrons lowers the on-resistance, yielding a greater slope. ## Also, let us keep VD constant and vary VG alone. ## Effect of channel length and the thickness of oxide layer * As channel length increases, so does the on-resistance (Ron). * As tox increases, the capacitance between the gate and silicon substrate decreases. * We have Q = CV. * Hence given voltage results in less charge on the gate and hence a lower electron density. * Consequently the device suffers from a higher on resistance producing less drain current for a given gate voltage or drain Voltage. ## Another MOS parameter that affects performance is the width (W). * As we increase ‘w’, the channel resistance↓ # Device act as a voltage-controlled resistance if VG>VTH. * To form a channel, the potential difference between the gate and oxide silicon interface must exceed VTH. * If the drain voltage is higher than source voltage, voltage along the channel increases as we go from source towards the Drain. ## If the drain voltage is high enough to produce VG-VD = VTH, then the channel ceases to exist near the drain. * The gate-substrate potential difference is not sufficient at x = L to attract electrons and the channel is “pinched off”. ## What happens if VD rises even higher than VG-VTH? * Here, at some point L1 < L, VG-VD = VTH as shown in the figure. ## Hence, no channel between L’ and L. * Does it mean that the transistor cannot conduct current? No. * The device still conducts. * Once electrons reach at the ends of the channel, they experience the high electric field in the depletion region surrounding the drain junction and are rapidly swept to the drain terminal. # Derivation of IV characteristics * Let us find out the charge density of the channel i.e., free electron per unit length. We have Q = CV. * If C is the gate capacitance per unit length and V the voltage difference between the gate and the channel, then Q is the desired charge density, Let Cox = Gate Capacitance / area. * Hence C = Cox WL and V = VG - VTH. Then, the charge density Q = WL Cox (VGS – VTH). Here Q is expressed in C/m. * We know that the channel voltage varies along the length of the transistor, and the charge density falls as we go from the source to the drain. * Hence, the above relationship es valid only near the source terminal. * Let us denote the channel potential at x by V(x) * Hence Q(x) = W Cox [VGS-V(X)-VTH]. * Note that (VGS - VTH) is also known as over Drive Voltage. * The drain current ID can be derived as ID = ½ µn Cox [2 (VGS – VTH) VDS – VBS]. Valid if VGS > VTH. ## Aspect ratio * Equivalent to placing more transistors in parallel. * For a constant VGS, ID varies parabolically with VDS and reaching, a maximum of IDmax = ½ µn Cox W (VGS-VTH)² at VDS = VGS – VTH ## In (a), the characteristics exhibit maximum that follow a parabolic shape themselves. * IDmax = ½ (VGS-VTH)² because IDmax = ½ (VGS-VTH) * The nonlinear relationship between ID and VDS reveals that the transistor cannot generally be modeled as a simple linear resistor. However, if VDS << 2(VGS-VTH), the above equation reduces to ID ~ µn Cox W (VGS-VTH) VDS exhibiting a linear ID – VDS behaviour for a given VGS. * In fact, the equivalent on resistance is given by: Ron = µn Cox W (VGS-VTH) ## At small VDS (near the origin), the parabolas can be approximated by straight lines. ## We have ID = ½ µn Cox W [2 (VGS-VTH) VDS-VBS]. This relation suggests that ID begins to fall for VDS > VGS-VTH. * In reality, the drain current reaches “Saturation” that is become constant for VDS > VGS-VTH. * This is because the channel experiences pinch-off if VDS = VGS-VTH * Thus, further increase in VDS simply shifts the pinch-off point slightly toward drain. * The ID during this region is given by ID= ½ µn Cox (VGS-VTH)² * The above relationship is independent of VDS. ## The I-V characteristics of MOSFET appears similar to saturation and forward active regions in BJT. * le triode = Saturation in BJT * Saturation = Forward-active in BJT # Channel Length Modulation * The point at which pinch-off occurs moves toward the source as the drain voltage increases. * The effective channel length varies with VDS to some extent. * This is known as channel length modulation. * Due to this drain current increases as VDS increases because ID α 1/L. * Similar to the early effect of BJT, channel length modulation results in a finite output impedance given by the inverse of ID – VDS slope. * To account for channel length modulation, we assume Lus constant, but multiply by a corrective term. * ID = ½ µn Cox W (VGS-VTH)² (1 + λVDS) * X = channel length modulation coefficient. # Wish you all the best - Shelas Sathyan