Sequential Logic Design PDF

ELCE 434 set 3 Sequential Logic Design Dr. Hani Saleh & Dr. Baker Mohammad Motivation: Why do we need sequential elements? Combinational versus sequential –Combinational locks (b) open based on combination only –Sequential locks (a) need to follow the correct sequence R15 -> L25 -> R 20...

ELCE 434 set 3 Sequential Logic Design Dr. Hani Saleh & Dr. Baker Mohammad Motivation: Why do we need sequential elements? Combinational versus sequential –Combinational locks (b) open based on combination only –Sequential locks (a) need to follow the correct sequence R15 -> L25 -> R 20 Need to separate operation on time to utilize same hardware –This is called pipelining in digital system Increase throughput Increase latency  3 Synchronous Sequential Circuit Model SEQUENTIAL ELEMENTS  Basic NOR (SR) Latch Set state: Set = 1, Reset = 0  Q = 1 Reset State: Set = 0/1, Reset = 1  Q = 0 Memory/hold state: Set = Reset = 0  Q = memory Reset Set Q Basic NOR Latch Redrawn S R Q Q 0 0 0/1 1/0 memory state 0 1 0 1 1 0 1 0 1 1 0 0 R Q Q S  Timing Analysis of Basic Latch t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 1 R 0 1 R S Q 0 1 Q ? Q 0 S 1 Q ? 0 –What happens at t10?? S and R both go from 1 to 0 simultaneously If gate delays are exactly the same  oscillation!!!  Gated SR Latch –To get better control of the state changes, we must limit when the input signals affect the outputs Clk S R Q(t+1) 0 x x Q(t) R Q 1 0 0 Q(t) Clk 1 0 1 0 Q 1 1 0 1 S –Outputs change only when Clk = 1 1 1 1 x Clk acts as an Enable signal undefined since we don't know which stable state will result Comments on Latches –Need to avoid the unstable state Note that all other states have “correct” Q and Q –Can use the cross-coupled NOR approach, or can use the cross-coupled NAND approach All gates are the same type S S Q Q Clk R Q Clk Q R  Gated D Latch –Provide only a single control signal D (for Data) More common than SR latch, and simpler S D Clk D Q(t+1) (Data) Q 0 x Q(t) Clk 1 0 0 R Q 1 1 1 D Q Clk Q D Latch Timing Diagram –Output Q changes only when Clk = 1 Q tracks D when Clk = 1 –This latch is level-sensitive since the output is sensitive to the level of the clock t1 t2 t3 t4 Clk D Q Time FROM TRANSISTORS TO GATES How Do We build logic Gates? We Build Logic Gates Using CMOS Transistors: NMOS Transistors PMOS Transistors Inverter Gate Most Basic Gate Inverter Operation Other Gates Tri-State Buffers Very important gate Very Effective to build muxes Tri-State Buffers Truth Table 2:1 Mux Using Tri-State Buffers Tri-State Buffers Schematic Transmission Gate 18 CMOS Transmission Gate Analog Switch Can Pass signals in both directions (a) transistor-level schematic. (b) circuit symbol How Gated D Latch are really built? 19 Figure CMOS D-latch built using transmission gates Can we build shifter/counters from latches? What happen when we cascade latches?  20 CMOS master–slave circuit of a D-type flip-flop (with Clear): (a) circuit schematic and (b) sample waveforms.  21 Signal paths in a CMOS master–slave D-type flip- flop: (a) master cycle signal paths and (b) slave cycle signal paths. Master-Slave D Flip-Flop (Negative Edge) –Desire to remove the level-sensitive wilderness Want changes in Q only on the transition of the Clk signal from 1  0 (or from 0  1) When Clock = 1, master D latch tracks D; slave D latch remains unchanged (Q remains fixed) When Clock = 0, master D latch is unchanged; slave D latch tracks Q m Master Slave D D Q Q D Q Q D Q Clock Clk Q Clk Q Q Q negative edge-triggered flip-flop Timing of Negative Edge D-FF Changes to Q occur only on the negative edge of the Clock Clock D Q m Q =Q s Master Slave Q m Q s D D Q D Q Q Clock Clk Q Clk Q Q Timing of Master-Slave D Flip-Flop  +ve Edge D-FF Changes to Q occur only on the negative edge of the Clock Timing of Master-Slave D Flip-Flop  +ve Edge D-FF Changes to Q occur only on the negative edge of the Clock Summary –Latch Two NANDs (or NORs) used to store one bit –Gated latch Latch with an control enable, called Clk Two basic types: SR and D, both level sensitive –Master-slave flip-flop State changes only on clock edge; made from two gated D latches REGISTERS, SHIFTERS AND COUNTERS Building Complex Memory Elements Flipflops: most primitive "packaged" sequential circuits More complex sequential building blocks: Storage registers, Shift registers, Counters Available as components in the TTL Catalog How to represent and design simple sequential circuits: counters Problems and pitfalls when working with counters: Start-up States Asynchronous vs. Synchronous logic ECE C03 Lecture 9 28 Registers Storage unit. Can hold an n-bit value Composed of a group of n flip-flops –Each flip-flop stores 1 bit of information Normally use D flip-flops ECE C03 Lecture 9 29  Controlled Register Reset Load Action 0 0 Q = old Q 1 0 Q=0 0 1 Q=D Parallel output Q 3 Q 2 Q 1 Q 0 D Q D Q D Q D Q Q Q Q Q Parallel input Clock ECE C03 Lecture 9 30  Shift Registers Storage + ability to circulate data among storage elements Q1 Q2 Q3 Q4 1 0 0 0 Shift 0 1 0 0 Shift 0 0 1 0 Shift 0 0 0 1 Shift Shift from left storage Q1 element to right neighbor on every lo-to-hi transition Q2 on shift signal Q3 Q4 ECE C03 Lecture 9 31 Application of Shift Registers Parallel to Serial Conversion Sender Receiver Serial Data Out Serial transmission ECE C03 Lecture 9 32 Counters Proceed through a well-defined sequence of states in response to count signal 3 Bit Up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000,... 3 Bit Down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111,... Binary vs. BCD vs. Gray Code Counters AAcounter counterisisaa"degenerate" "degenerate"finite finitestate statemachine/sequential machine/sequentialcircuit circuit where the state is the only output where the state is the only output ECE C03 Lecture 9 33 Counter Design Procedure This procedure can be generalized to implement ANY finite state machine Counters are a very simple way to start: no decisions on what state to advance to next current state is the output Example: 3-bit Binary Upcounter Present Next Flipflop State State Inputs 000 111 C B A C+ B+ A+ TC TB TA Decide to implement with D-Flipflops 001 110 0 0 0 0 0 1 0 0 1 What inputs must be 0 0 1 0 1 0 0 1 0 presented to the FFs 0 1 0 0 1 1 0 1 1 to get them to change 010 101 0 1 1 1 0 0 1 0 0 to the desired state bit? 1 0 0 1 0 1 1 0 1 011 100 1 0 1 1 1 0 1 1 0 This is called 1 1 0 1 1 1 1 1 1 "Remapping the Next 1 1 1 0 0 0 0 0 0 State Function" State Transition Flipflop Table Input Table 34 ECE C03 Lecture 9 Example Design of Counter K-maps for Toggle Resulting Logic Circuit: Inputs: BA C 00 01 11 10 0 1 1 TA = A’ 1 1 1 BA C 00 01 11 10 0 1 1 TB =B’A+AB’ 1 1 1 BA C 00 01 11 10 0 1 1 1 1 1 TC =C’AB+CB’+CA’ ECE C03 Lecture 9 35 Timing Diagram 100 \Reset QC QB QA Count 36 Another way to build the same counter What type of FF is this? Implementing Counters with D-FFs Different counters can be implemented best with different FFs Steps in building a counter –Build state diagram –Build state transition table –Build next state K-map Implementing the next state function with D-FFs Toggle flip flops best for binary counters Existing CAD software for finite state machines favor D FFs ECE C03 Lecture 9 38  More Complex Counter Design Step 1: Derive the State Transition Diagram Count sequence: 000, 010, 011, 101, 110 S0 S6 S2 S5 Present Next State State S3 Step 2: State Transition Table 000 0 1 0 010 0 1 1 011 1 0 1 101 1 1 0 110 0 0 0 ECE C03 Lecture 9 39 Complex Counter Design (Contd) S0 S6 Step 1: Derive the State Transition Diagram Count sequence: 000, 010, 011, 101, 110 S2 S5 Present Next S3 State State CBA C+B+A+ Step 2: State Transition Table 000 0 1 0 001 XXX 010 0 1 1 011 1 0 1 100 XXX 101 1 1 0 110 0 0 0 Note the Don't Care conditions 111 XXX 40 Counter Design (Contd) Step 3: K-Maps for Next State Functions CB A 00 01 11 10 0 X 1 CB 1 X 1 X A 00 01 11 10 SET A D Q C+ = B 0 1 X 1 CLR 1 X 1 X Q B SET B+ = C’+A’B’ D Q CB CLR Q A 00 01 11 10 C 0 X 1 1 D SET Q 1 X X CLR Q A+ = A’C ECE C03 Lecture 9 41 Resultant Circuit for Complex Counter Timing Waveform: 100 Count \Reset 0 0 0 0 1 1 0 C B 0 0 1 1 0 1 0 A 0 0 0 1 1 0 0 42 BCD (Binary A two-digit BCD Coded Decimal) counter Enable Counter 1 0 D0 Q0 0 D1 Q1 Consists of 2 modulo- BCD0 0 D2 Q2 10 counters, one for 0 D3 Q3 each digit. Each counter resets Load after the count of 9 Clock Clock has been obtained. Load=1 when Q3=Q0=1. This caused Clear Enable 0 D0 Q0 0s to be loaded to FFs D1 Q1 0 at the next +ve edge D2 Q2 BCD1 0 of the clock. 0 D3 Q3 When BCD0=9, the Load next stage gets Clock enabled. When Clear=1, 0s get loaded to initialize counters.