Digital Logic - Latches and Gates

Gated SR Latch

• Limits when input signals affect outputs
• Clock signal acts as an Enable signal
• Outputs change only when Clk = 1
• Avoid the unstable state where both S and R are HIGH (1)

Gated D Latch

• Uses a single control signal D (for Data)
• More common and simpler than the SR latch

D Latch Timing Diagram

• Output Q changes only when Clk = 1
• Q tracks D when Clk = 1
• This latch is level-sensitive since the output is sensitive to the level of the clock

CMOS Transistors for Logic Gates

• NMOS and PMOS transistors are used to build logic gates

Inverter Gate

• The most basic gate, inverts the input signal

Tri-State Buffers

• Allow selectively enabling or disabling the output signal
• Crucial for building multiplexers (muxes)

Transmission Gate

• Acts as an analog switch
• Can pass signals in both directions, unlike a traditional gate

CMOS D-Latch Construction with Transmission Gates

• Uses transmission gates to create a D latch

Master-Slave D Flip-Flop (Negative Edge)

• State changes only on the negative edge of the clock signal
• Master D latch tracks D when Clock = 1,Slave D latch remains unchanged
• When Clock = 0, master D latch freezes, slave D latch tracks Q (master output)

Timing of Negative Edge D Flip-Flop

• Changes in output Q occur only on the negative edge of the Clock

Timing of Master-Slave D Flip-Flop for +ve Edge D-FF

• Changes to Q occur only on the positive edge of the Clock

Summary of Latches and Flip-Flops

• Latch: basic storage element using two NAND or NOR gates to store 1 bit
• Gated Latch: Latch with a control enable (Clk)
• SR Latch: two inputs: S (Set) and R (Reset)
• D Latch: single input: D (Data)
• Master-Slave Flip-Flop: composed of two gated D latches to achieve edge-triggered behavior

Registers

• Storage units that hold an n-bit value
• Composed of a group of n flip-flops, each storing 1 bit
• Typically use D flip-flops

Controlled Register

• Can reset, load or store the old value based on the state of Reset and Load signals
• Parallel input and output

Shift Registers

• Storage with the ability to circulate data among storage elements
• Shift data from left storage element to right neighbor on every clock transition

Applications of Shift Registers

• Parallel to Serial conversion: Sending data bit by bit

Counters

• Proceed through a specific sequence of states in response to a count signal
• Typical examples: Up-counters, Down-counters, Binary Counters, BCD counters, Gray Code Counters
• Counters are degenerate finite state machines where the state is the only output

Counter Design Procedure

• Design procedure for any finite state machine, simplified for counters.
• No decision needed on which state to advance to, the current state is the output
• Remapping the Next State Function: determines inputs for the FFs to change to the desired state
• Use State Transition Table and K-maps to implement the FF input logic

Timing Diagram for a Counter

• Illustrates the behavior of the counter over time
• Tracks the states of the counter, clock signal and control signals like reset

Implementing Counters with D Flip-Flops

• Different counters are better suited for different flip-flop types
• Steps: build state diagram, state transition table, K-maps
• Implement the next state function with D flip-flops
• Toggle flip flops are best for binary counters

More Complex Counter Design

• Derive the State Transition Diagram
• Create a State Transition Table
• Use K-maps to generate the next state logic functions for each FF
• Don’t cares for unused states to simplify the logic

Resultant Circuit for Complex Counter

• Shows the circuit implementation of the complex counter
• Timing Waveform represents the counter's operation over time

BCD (Binary Coded Decimal) Counter

• Composed of two modulo-10 counters, one for each digit (for decimal representation)
• Used for representing decimal values using binary encoding (each decimal digit is represented by 4 bits)

Sequential Logic Design

• Sequential circuits operate based on sequences of inputs, not just combinations.
• Sequential locks require specific input order, unlike combination locks.
• Pipelining in digital systems utilizes time separation for more efficient use of hardware.
• Pipelining increases throughput but also increases latency.

Synchronous Sequential Circuit Model

• Utilizes a central clock signal to synchronize all state transitions.

Sequential Elements

• Basic building blocks of sequential circuits.
• Enable the storage and manipulation of data over time.

Basic NOR (SR) Latch

• A fundamental latch with two inputs: Set and Reset.
• Set state: Q = 1 when Set = 1 and Reset = 0.
• Reset state: Q = 0 when Reset = 1, regardless of Set input.
• Memory/hold state: Q retains its previous state when Set and Reset are both 0.

Basic NOR Latch Redrawn

• Illustrates the latch's behavior through a table with input and output combinations.
• Memory state: Q stays the same when S and R are both 0.

Timing Analysis of Basic Latch

• Analyzing the latch's behavior over time, with changing inputs.
• Demonstrates the potential for oscillation if Set and Reset go low simultaneously with equal gate delays.

Gated SR Latch

• Improves control over state changes by adding a clock input (Clk).
• Outputs change only when Clk = 1, acting as an enable signal.
• Avoids the unstable state where both S and R are high.

Comments on Latches

• Essential to prevent unstable states, as they can lead to unpredictable behavior.
• Both NOR and NAND gates can be used to construct latches.

Gated D Latch

• Simplifies the SR latch by using only one data control input (D).
• More common than SR latches.
• Output Q follows D when Clk = 1 and retains previous state when Clk = 0.

D Latch Timing Diagram

• Depicts the relationship between clock, input, and output signals.
• Shows the output Q changing only when Clk = 1 and tracking D during that period.

CMOS Transistors

• NMOS transistors are the basis for logic gates.
• PMOS transistors are also used in logic gates.

Inverter Gate

• The most basic logic gate.

Inverter Operation

• An inverter inverts its input signal: 0 becomes 1, and 1 becomes 0.

Other Gates

• AND, NAND, OR, NOR, XOR, XNOR gates.
• All logic gates can be implemented using basic CMOS transistors.

Tri-State Buffers

• Enable or disable the transmission of a signal based on an enable input.
• Used to build multiplexers (MUX) for signal selection.

Transmission Gate

• An analog switch that can pass signals in both directions.
• Constructed using NMOS and PMOS transistors.

How Gated D Latch are Really Built?

• Illustration of a CMOS D-latch built using Transmission Gates.

CMOS Master–Slave Circuit

• A circuit that combines two D-latches to create an edge-triggered flip-flop.

Master-Slave D Flip-Flop (Negative Edge)

• Avoids level-sensitive behavior in latches.
• State changes occur only on the falling edge of the clock signal.
• During the clock high phase, the master latch tracks D.
• During the clock low phase, the slave latch tracks the output of the master latch.

Timing of Negative Edge D-FF

• Only changes at the clock's falling edge.

Timing of Master-Slave D Flip-Flop  +ve Edge D-FF

• Enables state changes only on the rising edge of the clock.
• Commonly used in synchronous systems.

Summary

• Latches are fundamental storage elements in sequential circuits.
• Gated latches are controlled by a clock signal.
• Master-slave flip-flops provide edge-triggered functionality for more precise state changes.

Registers, Shifters and Counters

• Building complex memory elements on top of flip-flops.
• Registers store multiple bits of data.
• Shifters move data between internal positions.
• Counters track a sequence of counts.

Building Complex Memory Elements

• Flip-flops are the most basic sequential circuits.
• More complex circuits: registers, shift registers, and counters.

Counter Design Procedure

• A general procedure applicable to designing any finite state machine.
• Counters provide a straightforward introduction to the process.

Example: 3-bit Binary Upcounter

• Shows the step-by-step design of a 3-bit up-counter.
• Identifies the inputs needed for flip-flops to achieve the desired state changes.

Timing Diagram

• Visual representation of the counter's behavior over time.
• Shows how each output changes in response to the input clock signal.

Implementing Counters with D-FFs

• Illustrates the implementation of a counter using D flip-flops.

More Complex Counter Design

• Provides a step-by-step explanation of how to create a counter with a specific counting sequence.

Resultant Circuit for Complex Counter

• Displays the complete circuit diagram implementing the complex counter.

Timing Waveform:

• Details the timing behavior of the circuit with varying input and output signals.

BCD (Binary Coded Decimal) Counter

• A counter designed to represent decimal digits using binary codes.
• Uses multiple modulo-10 counters to represent each digit.