Rania Lec 1 PDF - Computer Architecture

Improving the interconnections inside a microcontroller (MCU) can significantly enhance its performance and flexibility. a. Increased Power Consumption Dynamic Power Dissipation: o Dynamic power is proportional to the operating frequency: Pdynamic=C * VDD2 * F → (C is the...

Improving the interconnections inside a microcontroller (MCU) can significantly enhance its performance and flexibility. a. Increased Power Consumption Dynamic Power Dissipation: o Dynamic power is proportional to the operating frequency: Pdynamic=C * VDD2 * F → (C is the capacitance) o As the frequency increases, dynamic power consumption rises linearly, making the system more power-hungry. Leakage Power: High frequencies often necessitate smaller transistor sizes and lower threshold voltages, which increase leakage currents and, consequently, static power consumption. Effect on Cost Design Complexity High-frequency operation demands advanced semiconductor fabrication technologies, which are more expensive. High frequencies require precise impedance control and reduced signal loss, necessitating multi-layer PCBs with higher-quality materials. High-frequency circuits are harder to test due to signal integrity issues and faster signal transitions, increasing the cost of production testing. At high frequencies, EMI becomes a significant issue. Mitigating EMI involves: Adding shielding. Using filters and ferrites. Ensuring proper grounding. These measures add to the overall cost. Higher frequencies improve performance but increase power consumption, heat, and costs due to more complex designs Communication Within a computer system → interconnection Communication with external world → interfacing Buses serve as shared communication channels, enabling devices to interact with one another. These communication processes can transmit both data and control signals. Bus variations: on-chip vs. off-chip buses serial vs. parallel buses wired vs. wireless buses Comparison of Bus Variations 1. On-Chip vs. Off-Chip Buses On-chip buses connect components within the same chip, while off-chip buses connect external devices or peripherals. Aspect On-Chip Buses Off-Chip Buses Definition Connect components within the same Connect the peripherals. chip. Examples AMBA (AHB, APB) PCI, USB, I2C, SPI Pros - High speed and low latency. - Support for external devices. - Lower power consumption. - Greater scalability. - Smaller size requirements. Cons - Limited to components on the chip. - Higher latency due to external connections. - Complex routing in dense chips. - Higher power consumption. Off chip buses → slaves are slower than MCU And we don’t need to degrade the MCU speed to communicate with them So we add a controller on bus to handle this issue While CPU is executing the instructions the controller communicate with slaves and collect the data But When the CPU needs to execute an instruction, it uses the memory. If the bus is occupied due to communication between slave devices, the bus is divided into two separate buses to resolve the conflict. The controller now manages the issue of varying communication speeds, ensuring it handles the CPU's speed as well as the different speeds of the slave devices. Here there are two main buses 1) bus for the upper group which has a controller North bride (memory controller) 2) bus for the lower group which has a controller South bride and the two buses are connected if one of the upper group needs to communicate with one in the lower group Bus design The bus is a shared resource, allowing any device to send data (after arbitrating for access). All other devices can read the data from the bus once it’s sent. Arbitrating the bus means Mastering the bus — the arbiter controls which device becomes the master (the one allowed to send data). The arbiter ensures that only one device sends data at a time, while other devices can read the data from the bus. Address/control signals on the bus specify the intended receiver of the message. The length of the bus determines its speed, making a hierarchy of bus structures logical. Buses can be: o Synchronous: A clock determines when each operation occurs. o Asynchronous: A handshaking protocol coordinates operations between devices. Transaction A transaction is a complete piece of communication (collection of data). All the transfers that take place across the bus are split across transactions. There are three distinct phases of every transaction: 1. Arbitration: The device that will control the bus (drive the common medium) during the transaction is determined, becoming the master. This applies to multi-master bus systems, while in some other protocols, usually there is a single master. 2. Addressing: The master activates another listening device by broadcasting (via bus) its address (i.e., device address or control register address) for reception. o Can be unicast (message applies to a single device) or multicast (applies to many). o The addressed devices are traditionally called slaves. 3. Actual data transfer (finally send the data). Synchronization Synchronization methods are required to ensure that the data presented during each of the phases mentioned above is valid (not corrupt or changing) when being read. Three types of synchronization protocols can be distinguished across the bus: 1) Synchronous protocols 2) Semi-synchronous protocols 3) Asynchronous protocols Synchronous protocols A clock signal is used to indicate when all the data is stable and can be safely read. Since many logic circuits are synchronous, extending this concept to the buses is natural. Challenge: how to synchronize different devices operating at different frequencies which frequency we will use when the frequencies are not the same When different devices operate at different frequencies, the challenge is determining how to synchronize their clocks. If the frequency ratio between devices is not an integer, it can lead to timing issues where the edges of the clocks don’t align. For a ratio of frequencies that is an integer (device 1 is twice the speed of device 2), the synchronization can be achieved by reading the data at every clock edge of the faster device, then skipping the next edge before repeating the process. For a non-integer ratio, there’s no clear alignment of clock edges, making it impossible to synchronize perfectly. This results in timing mismatches where one clock edge will never align with another, potentially causing data corruption or loss. Semi-synchronous Protocols Communication is synchronized with a clocking signal (‫)كل واحد بالكلوك بتاعتو‬. Master sends a request that is coordinated with the clock. Slave's response is conveyed through a dedicated line (READY or WAIT) (slave ‫) الريدي تبع‬ The value of the response line is sampled by the clock signal. The slave may need extra time to process the request, causing the WAIT or READY line to indicate whether the slave is ready for data transfer. Data transfer does not necessarily occur on every clock cycle, preventing timing mismatches. The master must wait for the READY or WAIT signal before proceeding with communication, ensuring correct data transfer. Asynchronous protocols There are no implicit time constraints in this system, meaning both the master and slave can trigger asynchronous events on their own, without being strictly coordinated by a common clock. No clock & slave receives or sends data by indicator signal→ ACK signal (acknowledge) same concept for master with REQ signal (Request) Pros: 1) No degradation in speeds 2) Used in on-chip communications 3) it does not suffer the constraints/delays imposed by the slowest signal. Serial vs Parallel Communications Parallel communication utilizes multiple wires running alongside each other, allowing data to be transmitted simultaneously across all the wires. Serial communication employs a single wire to transmit data bits sequentially, one at a time. 2. Serial vs. Parallel Buses Aspect Serial Buses Parallel Buses Examples USB, I2C, SPI ISA, PCI, DDR (RAM buses) Pros - Fewer wires reduce complexity. - Faster data transfer rates for short distances. - Lower EMI and power consumption. - all data are sent in one clock - Suitable for long distances. - Easier to synchronize for short runs. Cons - Slower for large amounts of data. - Requires more physical space and wires. - Higher EMI and power consumption. - cross taking and routing Parallel Buses → used On-Chip Parallel data transfer offers significantly higher speeds compared to serial data transfer. An 8-bit parallel data transfer is 8 times faster than serial data transfer. However, clock skew can reduce the speed of all the links, as it forces the system to operate at the speed of the slowest link. The propagation conditions for each wire may differ slightly, causing variations in travel time across the entire line due to differing distributed reactance. Balancing multiple lines to ensure equal propagation times is challenging, and this imbalance results in a phenomenon known as skew → skew may be for data and for a clock and they are independent Crosstalk can occur between parallel lines due to capacitance and mutual inductance between the wires in a parallel system. This results in inter-symbol interference (ISI) and noise, which can degrade the signal quality. The presence of crosstalk reduces the bandwidth of the link, leading to lower transmission rates. The negative impact of crosstalk becomes more significant as the length of the communication link increases. This imposes an upper limit on the length of a parallel data connection. As a result, parallel buses are typically much shorter than serial buses. Serial vs Parallel Communications: High Frequency Performance It is hard to route many signals across a board without introducing timing variation (clock skew) between them – the more variation the lower the maximum frequency is. 𝟏 𝑭𝒄𝒍𝒌 = 𝑻𝒆𝒙𝒆𝒄𝒖𝒕𝒊𝒐𝒏 + | 𝑻𝒔𝒌𝒆𝒘 − 𝑻𝒔𝒆𝒕𝒖𝒑 | Many wires switching simultaneously at high frequency produce more EMI and interfere and limit the maximum frequency.  Aspect Parallel Serial Distance Short Long Frequency of one-line Low (EMI + cross taking) Short While the frequency of each individual line in a parallel system may be lower than that of a serial system, parallel communication offers higher throughput. This allows parallel systems to transfer more data simultaneously, enabling them to complete the transmission faster despite each line operating at a lower frequency. So, parallel buses are an option of choice for on-chip buses while in off-chip communication one often resorts to serial protocols. 3. Wired vs. Wireless Buses Wired buses use physical wires or traces for data transmission, while wireless buses transmit data through wireless signals. Aspect Wired Buses Wireless Buses Definition Physical wires or traces transmit Data is transmitted through wireless data. signals. Examples Ethernet, CAN, PCIe Wi-Fi, Bluetooth, Zigbee Pros - Reliable and stable connections. - Eliminates the need for physical - High bandwidth and low latency. connections. - Flexible and portable. Cons - Limited by physical constraints. - Prone to interference and latency. - Requires more maintenance - Lower bandwidth compared to wired (wiring). solutions.