Computer Architecture and Power Consumption

Study Notes

Components include processors, memory, and I/O devices.
Organizational principles design microarchitecture, overall system design, and a programming interface for software, instructions, and state changes.
Goals involve meeting functional and performance targets within constraints (cost and power) while leveraging technological advancements.
Architecture involves making trade-offs.

Dynamic Power Dissipation is proportional to the operating frequency (Pdynamic = C * VDD2 * F).
Dynamic power consumption rises linearly as frequency increases, making the system more power-hungry.
Leakage Power is higher at higher frequencies due to smaller transistor sizes and lower threshold voltages, leading to increased leakage currents and static power consumption.

Design complexity increases with higher-frequency operation, requiring advanced semiconductor fabrication technologies, which are more expensive.
Precise impedance control and reduced signal loss necessitate multi-layer printed circuit boards (PCBs) with high-quality materials.
High-frequency circuits are harder to test due to signal integrity issues, increasing production testing costs.
Electromagnetic interference (EMI) becomes a significant issue at high frequencies, requiring measures like shielding, filters, and proper grounding, all increasing the overall cost.
Higher frequencies increase performance but also increase power consumption, heat, and costs due to more complex designs.

A desktop design example could have processors accounting for 25% of the cost, memory representing 25%, and the remainder (50%) for components like I/O, power supply, and enclosure.

Buses allow devices to communicate, transmitting data and control signals.
Types of bus variations include on-chip vs. off-chip buses, serial vs. parallel buses, and wired vs. wireless buses.
On-chip buses connect components within the chip, while off-chip buses connect external devices or peripherals.

Buses act as shared resources.
Arbitration ensures that only one device sends data at a time, while others can read data.
Address/control signals specify the recipient.
Bus length determines speed and logical hierarchy.
Synchronous buses are based on a clock signal timing each operation.
Asynchronous operations use a handshaking protocol for coordination between devices.
Transaction involves three phases: arbitration, addressing, and data transfer.

Synchronous protocols use a clock signal to ensure data stability.
Semi-synchronous protocols use synchronized clocking signals with dedicated lines (READY/WAIT) for communication.
Asynchronous protocols coordinate operations without timing constraints.

Parallel communication uses multiple wires, enabling simultaneous data transmission.
Serial communication uses a single wire, transmitting data sequentially.
Parallel communication is faster for short distances but has higher cost and complexity concerns due to potential imbalance and cross-talk. Serial communication is better for long distances because the wiring complexity is significantly lower.

Wired buses use physical wires for data transmission.
Examples include Ethernet, CAN, and PCI Express.
Wireless buses use wireless signals.
Examples include Wi-Fi and Bluetooth.
Wired buses offer high bandwidth and low latency but are limited by physical constraints and are more costly to maintain while wireless buses eliminate these physical constraints.