Mixed-Mode Transceivers PDF

Jeffrey Walling Mixed-Mode Transceivers A brief tutorial T his bri...

Jeffrey Walling Mixed-Mode Transceivers A brief tutorial T his brief tutorial intro- tectural choices for both are presented. ,. In fact, from 1971 to 2021, duces the motivations Finally, conclusions and future work in the number of transistors increased and concept of mixed- mixed-signal transceivers are provided. from. 2,000 to 2 50 billion (see signal RF transceivers. Figure 1 ). Scaling has generally The basics of mixed-signal The Scaling of CMOS Devices resulted in the MOS device operat- transmitter (TX) circuits and receiver (RX) Over the past 50 years, the scaling ing as a faster, reduced resistance circuits are described, and several archi- of CMOS transistor devices follow- switch while having reduced intrin- ing Moore’s Law has been motivated sic gain. These facts dictate that in Digital Object Identifier 10.1109/MSSC.2022.3182634 primarily by the desire to increase deeply scaled CMOS, architectural Date of current version: 24 August 2022 the transistor count on a single die changes that exploit CMOS’ strength 1943-0582/22©2022IEEE thorized licensed IEEE SOLID-STATE use limited to: Universitaetsbibliothek der RWTH Aachen. Downloaded on November 13,2024 at 22:12:24CIRCUITS UTC fromMAGAZINE SU M M E R 2 0apply. IEEE Xplore. Restrictions 22 53  as a high-speed switch should be 1011 exploited: for example, architectures Number of Transistors Number of Transistors that use more digital logic gates and 109 Trend fewer traditional analog blocks (e.g., 107 filters and amplifiers). Conventional TX and RX chains 105 (shown in Figure 2) are laden with ana- 103 log components that rely on the tran- 1971 1981 1991 2001 2011 2021 sistor acting as a voltage-dependent Year current source with large transconduc- tance (g m) and large output resis- FIGURE 1: The number of transistors on microprocessors from 1971 to 2021. (Source:.) tance (rd ). Typically, the individual blocks in the transceiver chains (e.g., amplifiers, mixers, filters, data con- I-DAC verters, and so on) must be interfaced with each other. This requires imped- Baseband ance matching between blocks and/or PA bias-independent coupling. Impedance Modem RF Channel 90° matching is typically provided using Q-DAC bandpass-matching networks and hence causes band limiting, particu- (a) larly when several impedance matched blocks are cascaded. I-DAC A conventional TX is shown in Figure 3(a). Each interface between circuit blocks requires that the cor- LNA Baseband Modem rect impedance be presented to the 90° preceding/succeeding stage. This serves to narrow the operational bandwidth Q-DAC of each block of the conventional TX (b) and increases the area and the routing and interconnect complexity. Alterna- FIGURE 2: (a) Conventional TX and (b) RX block diagram schematics. tively, a mixed-signal TX, shown in Figure 3(b), combines data conver- sion, mixing and, when implemented ZDAC-FILT ZFILT-MIX as a digital power amplifier (PA), ZMIX-DRV power amplification in a single block I DAC consisting only of high impedance switches and logic gates in the stages Baseband 0 preceding the output stage. Hence, Modem LO 90 the only interface that requires band- width-limiting impedance matching Q DAC ZPA-ANT is between the output stage and the ZDRV-PA antenna. Similar benefits are true for (a) mixed-signal RXs. In conventional TXs and RXs, a I large amount of high-order filtering Q is required in the analog baseband Baseband RF-DAC for reconstruction and antialias- Modem High Z or ing filters. This often results in a Digital PA relatively large die area. When using φ 0 RF-DACs/ADCs, much of the filter- LO ZDPA-ANT 90 ing can be pushed into a combina- (b) tion of the digital and RF domains, FIGURE 3: (a) Interface impedances between blocks in a conventional TX. (b) Interface im- resulting in an overall smaller foot- pedances in an RF-DAC. ANT: antenna; DRV: driver; FILT: filter; MIX: mixer. print required for filtering. In the RF 54 useSUlimited thorized licensed IEEE SOLID-STATE M M E Rto:2 0Universitaetsbibliothek 22 derCIRCUITS MAGAZINE RWTH Aachen. Downloaded on November 13,2024 at 22:12:24 UTC from IEEE Xplore. Restrictions apply.  domain, the filtering can often also This brief tutorial introduces the motivations be leveraged as part of the output matching, biasing, and differential- and concept of mixed-signal RF transceivers. to-single-ended conversion. This is particularly true when planar spiral transformers are used in the output- adoption in the next generation of scaled (e.g., all elements scaled by 2×), matching network. wireless communications. unary scaled (e.g., all elements are In the TX, the PA often limits the equal), or segmented (e.g., part of the power efficiency of the entire TX. RF-DACs array is unary, and part is binary) to Switching amplifiers are typically The primary type of mixed-signal TX leverage the benefits of both binary more power efficient than linear is the RF-DAC (sometimes referred to (e.g., lower complexity in decoding) amplifier counterparts but require as mixing DAC). The RF-DAC serves as and unary scaling (e.g., better slice linearization before they can be uti- 1) a data converter, converting base- matching). Though the functionality lized in modern wireless communica- band digital signals to the ana- of current-mode and voltage-mode tions systems that use nonconstant log domain RF-DACs is similar, their operation envelope modulation. RF-DACs allow a 2) a mixer, upconverting the data is quite unique and subject to differ- mechanism to linearize switching PAs from the baseband to the RF/mm- ent limitations. using current-mode or voltage-mode wave frequency digital PAs –. In this way, the 3) an output stage, driving a PA Current-Mode RF-DACs output stage of the RF-DAC can act as or antenna. The basic current-mode RF-DAC con- either a switching current source in a Generally RF-DACs operate either sists of a bank of parallel current class-D−1 mode or a switching volt- in the current domain, using arrays cells that are summed together into a age source [e.g., switched-capacitor PA of switchable current sources, or in common load. The current cells can (SCPA)] in a class-D mode. In both the voltage domain, using arrays of be individually controlled to be on cases, the ideal peak efficiency of the switchable capacitors, as shown or off and can operate as a discrete- amplifier can reach 100%, whereas for in Figure 4. level linear amplifier (e.g., class-B) or a linear PA (e.g., class-B), the ideal peak A conventional TX and RF-DAC as a discrete-level switching ampli- drain efficiency is 78.5%. achieve the same objective: to con- fier (e.g., class-D −1). Operation in a RF-DACs and -ADCs have limita- vert a digital baseband signal to an switching mode yields the highest tions in operating frequency in that analog signal, up-convert the signal efficiency, and class-D −1 has become the transistor devices that they are to the RF frequency, and amplify the the most common basis for current- composed of must be able to operate signal, but this is achieved differently mode RF-DACs. A class-D −1 PA is as switches, which typically lim- in RF-DACs, as shown in Figure 5. For shown in Figure 6 (left). A differential its their frequency of operation to instance, the mixer in a conventional pair switching at the RF frequency, 1 fT /10. However, recent efforts TX is replaced by a digital logic gate f RF, switches the current into a par- have shown successful pathways (e.g., an AND-gate) in each slice of the allel resonant tank composed of L 0, for translation to the mm-wave fre- RF-DAC. In this way, the baseband C 0, and ropt. The output power is not quency –. data are up-converted on a slice-by- dependent on the input power (e.g., Newer wireless communications slice basis. Amplification in the con- the PA is nonlinear) and is given as: standards are leveraging wider band- ventional TX is replaced by switches widths (e.g., hundreds of MHz) and must and switch drivers in the RF-DAC. The (rVDD)2 Pout = 1.(1) operate with high linearity to transmit data conversion in the conventional 2 ropt and receive information-dense non- TX is replaced by the tiled, digi- constant envelope modulation [e.g., tally controlled slices in the RF-DAC. To convert the class-D−1 into an RF- orthogonal frequency-division mul- Finally, analog baseband filtering in DAC, the switching cells can be sub- tiplexing (OFDM); 4096-quadrature the conventional TX is replaced by a divided into smaller unit switches amplitude modulation (QAM); and so combination of digital and RF filter- [Figure 6 (right)], where the unit on]. SCPAs have already been demon- ing in the RF-DAC. We attempt to high- switches can be individually switched strated to operate in the Wi-Fi-6 stan- light the function in the conventional at f RF or held at ground. In this dard (160 MHz, 1024-QAM OFDM) , TX by matching colors with the blocks w ay, t he out put power c a n be and are no doubt a path toward that provide the same function in the increased (decreased) by switching the more difficult Wi-Fi-7 standard mixed-signal TX (Figure 5). more (fewer) cells. It is important (320 MHz, 4096-QAM OFDM). Given Designs for RF-DACs are typically to note either that all current-mode the inherent advantages of wide optimized as a 1-b slice and then tiled RF-DACs have compressive output bandwidth and linearity, mixed-sig- and interconnected together to com- voltage characteristics as a function nal transceivers are poised for rapid plete an array. Arrays can be binary of the digital input control codes IEEE SOLID-STATE thorized licensed use limited to: Universitaetsbibliothek der RWTH Aachen. Downloaded on November 13,2024 at 22:12:24CIRCUITS UTC fromMAGAZINE SU M M E R 2 0apply. IEEE Xplore. Restrictions 22 55  Current Cell VDD1 VDD.diag DPA Silicon Chip VDD.diag CK Binary-to- 127 Q D EN Thermom. R 7 CS EN M 7 EN Decoder EN C2 2 CK ACW Signals to Cells VDD.diag D [delay] Q M1 M2 3 3 VDD2 EN EN CK M 11 M 12 M8 LCHOKE C1 C1 LW R1 R1 RFin M3 M4 EN RFout LW M5 M6 LCHOKE VDD1 Bias M13 M9 M 10 VDD2 Gate Bias EN EN Voltage Elementary Cell M14 Elementary Cell IB (a) 510 fF Output Matching Network 2VDD 56/0.1 112/0.1 1,430 µm 0–VDD VDD–2VDD VDD Level Shifter Capacitor Array Drivers, Switch, 0–VDD 0–VDD Logic and 730 µm 0–VDD φP DIN φN Voltage Cell (b) FIGURE 4: Slice-based design in (a) current-mode and (b) voltage-mode RF-DACs. ACW: amplitude control word; CK: clock; DPA: digital power amplifier; EN: enable; Thermom.: thermometer. 56 useSUlimited thorized licensed IEEE SOLID-STATE M M E Rto:2 0Universitaetsbibliothek 22 derCIRCUITS MAGAZINE RWTH Aachen. Downloaded on November 13,2024 at 22:12:24 UTC from IEEE Xplore. Restrictions apply.  due to power-dependent current division or that the output power When using RF-DACs/ADCs, much of the filtering is inversely proportional to the can be pushed into a combination of the digital ­switching ­resistance. Hence, Pout is a and RF domains, resulting in an overall smaller nonlinear function of the number of switches that are enabled (e.g., of the footprint required for filtering. “on” resistance) unless the current sources/switches are scaled nonuni- formly. transformer to set the value of ropt Voltage-Mode RF-DACs In addition to nonlinearity, the max- and hence the maximum value of To this point, all voltage-mode RF- imum voltage that can appear across Pout. Ideally, a current-mode RF-DAC DACs use the SCPA topology. The the switch is rVDD, potentially subject- can have a peak efficiency value of basis for the SCPA is the class-D PA, ing the topology to severe overvoltage 100%, and the efficiency rolls off pro- as shown in Figure 7 (left). In the stress. The resonant tank can be real- portionally to Pout , which is similar class-D PA, a complementary pair ized by an impedance-transforming to the efficiency characteristic of a of transistors is switched at f RF and matching network in the form of a class-B PA. drives a square output voltage into SCPA VDD Core Amplitude SCPA Slice VDD P1 CU Decoder CU N I-DAC P1 CU 1 Ropt bit N Modem N1 bit 1 bit 0 Baseband Digital Filter/ PA Modem Interpolation 90° bit 0 bit 1 N1 Ropt bit N Q-DAC Clock and P1 CU CU N 1 Phase VDD CU Modulator P1 (a) VDD (b) FIGURE 5: A comparison of block functions in (a) a conventional TX and (b) an RF-DAC. The corresponding functions share a common color in each block. vout = vocos(ω t ) Lo vout = vocos(ω t ) Lo Co Co ropt ropt vDA vDB vDA vDB IDA + vout – IDB IDA + vout – IDB Vin Vin Vin Vin Slice-Based Design FIGURE 6: Left: A schematic of a class-D−1 PA. Right: a schematic of a class-D−1-based current-mode RF-DAC. IEEE SOLID-STATE thorized licensed use limited to: Universitaetsbibliothek der RWTH Aachen. Downloaded on November 13,2024 at 22:12:24CIRCUITS UTC fromMAGAZINE SU M M E R 2 0apply. IEEE Xplore. Restrictions 22 57  IDN Co /N iopt = iocos(ωt ) MP iopt = iocos(ωt ) Vin,1 Lo Vin Vin,N + Co Lo Co /N + vout ropt – ropt vout MN IDN – Slice-Based Design FIGURE 7: Left: A schematic of a class-D PA. Right: A schematic of a class-D-based current-mode RF-DAC (SCPA). a resonant tank circuit composed of of the unit capacitors at f RF and hold- unary- and binary-weighted cells. C 0, L 0, and ropt, and tuned to reso- ing others at ground. As the number The output voltage, Vout, and the out- nate at f RF. The tank filters the har- of capacitors switching is increased put power, Pout, for any given output monic content from the square wave (decreased), the output voltage is code, n, are given by: and delivers a sinusoidal voltage with increased (decreased) proportionally frequency f RF to the load resistance. with the number of cells switching. Vout = 2 n VDD.(2) r N To convert the class-D PA to an SCPA, When all of the capacitors in Pout = 22 ` n j 2 2 V DD the switches and capacitors are sub- the array are switched, as shown.(3) r N ropt divided into unit cells and arrayed, in Figure 8(a), the output voltage as shown in Figure 7 (right), such that is maximum, while when some of where VDD is the supply voltage of the the total capacitance and switching the cells are grounded, as shown in switches. As is seen, the output volt- resistance of the transistors in the Figure 8(b), the output voltage is age is linear with respect to the out- array remain constant compared to reduced. Assuming that a total of N put code, n, unlike the current-mode Figure 7 (left). The conceptual opera- desired output levels, the array can RF-DACs. This can be maintained for tion of the SCPA is that the output be divided into N unary-weighted well-decoupled voltage supply net- voltage, and hence, the output power unit cells, log 2 N binary-weighted works with well-matched capacitors can be controlled by switching some cells, or a segmented combination of and switches. This linearity means that SCPAs can be operated linearly up to their saturation point (e.g., they VC do not need to be operated with addi- tional power backoff). Unlike most L0 current-mode RF-DACs, the SCPA C0 C1 C2 CN VR + does not subject any devices to over- VR RoptΩ voltage stress topologically. Simi- – larly to current-mode RF-DACs, the b0 b1 b2 bN resonant tank can be realized by a bandpass impedance transformation network, which can be used to trans- (a) form a fixed impedance (e.g., 50 X) VC to a desired ropt, hence setting the maximum achievable value of Pout. L0 The power efficiency of the SCPA C0 CN + C1 C2 VR has an ideal peak value of 100% and VR RoptΩ reduces more slowly than the cur- – rent-mode RF-DAC, meaning that it is b0 b1 b2 bN systematically more efficient for all output power levels when compared to current-mode RF-DACs operat- (b) ing with similar Pout. It should FIGURE 8: The operation of the SCPA (a) when outputting full-scale voltage and (b) when be noted that while the SCPA is outputting reduced voltage. systematically more efficient than 58 useSUlimited thorized licensed IEEE SOLID-STATE M M E Rto:2 0Universitaetsbibliothek 22 derCIRCUITS MAGAZINE RWTH Aachen. Downloaded on November 13,2024 at 22:12:24 UTC from IEEE Xplore. Restrictions apply.  ­ urrent-mode RF-DACs, the SCPA is c Given the inherent advantages of wide typically limited to lower-frequency operation due to the necessity of the bandwidth and linearity, mixed-signal PMOS switch to the supply. Addi- transceivers are poised for rapid adoption in tionally, the SCPA typically needs a smaller ropt to achieve the same out- the next generation of wireless communications. put power as a current-mode RF-DAC. This can be explained by the smaller coefficient in the output power expres- leads to better timing precision as distinct nonidealities that must be sion (e.g., 2/r 2). generally the Cartesian components considered when choosing an RF-DAC are generated simultaneously, and compared to a conventional TX. The Polar Versus Cartesian/ hence, symmetric routing preserves first is that RF-DACs are sampled- Multiphase RF-DACs the timing between the vectors. data systems where the reconstruc- For complex signals containing both However, the Cartesian vector sum- tion filter is directly at the RF, and amplitude and phase modulation mation results in 3 dB of lower output this means that the spectral images (AM and PM), RF-DACs operate as vec- power due to the out-of-phase vector cannot be filtered as well as they can tor combiners and can do so in either summation, as shown in Figure 9(b). in a conventional TX. The sampling the polar domain or a multiphase The Cartesian RF-DAC uses four basis frequency and the images can be sup- (e.g., Cartesian) domain. A block dia- phase vectors 0c, 90c, 180c, and pressed using digital interpolation fil- gram schematic for a polar RF-DAC is 270c). Cartesian RF-DACs can use ters, but this comes at the expense of shown in Figure 9(a), while the block completely separate arrays to weight some additional power consumption diagram schematic for a Cartesian the basis phase vectors , , or in the digital baseband. RF-DAC is shown in Figure 9(b). they can use a cell-sharing approach Additionally, out-of-band noise can In polar RF-DACs –, the base- that outputs a predetermined wave- be reduced by increasing the resolu- band modem must convert Carte- form given for each basis phase , tion of the RF-DAC, but this typically sian in-phase (I(t)) and quadrature. Adding more basis phases (e.g., requires careful design in the layout (Q(t)) components to AM (A(t)) and PM 0c, 45c, 90c, 135c, f, and so on) can of the individual slices to ensure (z (t )) components. This generally reduce the power loss due to the out- that the capacitors or current cells requires a coordinate rotation digi- of-phase summation at the expense are well matched with their neigh- tal computer (CORDIC) processor or of more complicated clock genera- bors and within the matching limits lookup table. The conversion from tion and a more complicated vector of the process that is being used. Cartesian to polar vectors results in a summation algorithm ,. This can also mean having to use large bandwidth expansion due to the slightly larger capacitors or current nonlinear mathematical operations RF-DAC Nonidealities sources, depending on the mismatch used. A(t) is used to control individ- Though significant progress has been statistics in the process being used. ual slices in the RF-DAC, while z (t ) made in RF-DAC architectures, it Another challenge, particularly for modulates the clock edge. The tim- should be noted that there are some switching operations, is that the ing between the A(t) and z (t ) paths must be precisely controlled so that recombination of the correct vec- Q tor results. Polar modulators allow A A the output voltage to fully cover the Polar φ unit circle and hence result in high Baseband Digital I power efficiency. Modem PA In multiphase RF-DACs [e.g., Car- φ LO tesian RF-DACs, see Figure 9(a)] – , I(t) and Q(t) are used to control (a) individual slices that are clocked on Q an appropriate phase of the clock, I Q allowing for recombination of the Baseband Quadrature Q′ vectors in the output stage of the I Modem Digital I′ RF-DAC. Because this operation can 90 PA work on the raw Cartesian vector LO 0 components, no CORDIC is needed, (b) and hence, there is no bandwidth expansion of the signal. This also FIGURE 9: A block diagram schematic of (a) a polar RF-DAC and (b) a Cartesian RF-DAC. IEEE SOLID-STATE thorized licensed use limited to: Universitaetsbibliothek der RWTH Aachen. Downloaded on November 13,2024 at 22:12:24CIRCUITS UTC fromMAGAZINE SU M M E R 2 0apply. IEEE Xplore. Restrictions 22 59  It can potentially allow for the reduc- When considering RF-DACs, there are many tion of components (e.g., there is no choices to be made, and though significant work RF mixer, and the frequency down has been completed in the RF bands, there is conversion is in the digital domain), and like RF-DACs, it is inherently still a lot of investigation that needs to happen. wider band. This is for similar rea- sons to the RF-DAC. Converting directly to the digital parasitic capacitances in the circuit RF-ADCs domain means that there are reduced are charged and discharged peri- Significant progress has been made circuit interfaces that require imped- odically, and this can consume sig- on a wide variety of RF-DACs, while ance transforms. This can also lead nificant energy. Layout design at the the counterpart RF-ADCs are less to relaxation in the design of the slice level should aim to minimize mature. This is partially because frequency synthesizer and interme- parasitic capacitance as they reduce work on RF TXs is often motivated diate-frequency filtering. An RF-sam- the overall efficiency. by the strong desire to improve pling ADC schematic is shown energy efficiency, and the switch- in Figure 10(a). A bandpass channel RF-DAC Summary ing operation of the RF-DAC has that selection and an antialiasing filter As the reader can see, when con- effect. In RXs, the primary concern precede the ADC, which is followed sidering RF-DACs, there are many is usually to minimize the overall by a digital direct down converter choices to be made, and though sig- system noise floor, which typically consisting of digital mixers driven nificant work has been completed in is done using an analog low-noise by a numerically controlled oscillator the RF bands, there is still a lot of amplifier (LNA) and bandpass filter (NCO). The down-converted signals investigation that needs to happen. at the RF front end, obviating the are then filtered by a digital decima- Though there are some RF-DACs need for extremely wideband direct- tion filter. The sampling frequency operating at the mm-wave spectrum to-digital conversion. does not necessarily need to meet the –, more work is needed in However, with the increased usage Nyquist requirements at the RF cen- this space; additionally, support for of software-defined radios and the ter frequency; it needs to meet only multiband carrier aggregation and opening of the mm-wave spectrum the Nyquist requirements related reductions in out-of-band noise and for 5G, the RF-ADC is becoming more to the bandwidth of the signal with spurious signals are still needed. attractive due to its versatility as sufficient margin to be able to filter Also, spectral purity is something either a front-end RX or as an inter- Nyquist images. that must be worked on, and hence, mediate-frequency RX. When con- RF-sampling ADCs can read- designs that more optimally filter sidering an ADC, the input sampling ily enable multiband operation by spectral images arising from sam- operation is usually the first thing using a single RF-ADC and separate pling are needed. No transceiver is that is considered. Direct sampling digital down-conversion chains, as complete without the RX, and hence, at the RF has become more popular shown in Figure 11. In this case, the the counterpart to the RF-DAC, the as CMOS device scaling has increased sampling rate needs to be optimized RF-ADC, is discussed next. the switching speed of the transistor. only to mitigate any intermodulation RF Sampling ADC Blocker Gain, Relative Power (dB) Digital Down Converter RF Filter Q N sin Rx Band Decimation NCO ADC LNA Filter cos Filter Signal I N fs /2 fs Frequency (Hz) (a) (b) FIGURE 10: (a) A block diagram schematic of an RF-sampling ADC and (b) an example power spectral density (PSD) including blocker impairment. 60 useSUlimited thorized licensed IEEE SOLID-STATE M M E Rto:2 0Universitaetsbibliothek 22 derCIRCUITS MAGAZINE RWTH Aachen. Downloaded on November 13,2024 at 22:12:24 UTC from IEEE Xplore. Restrictions apply.  Multiband RF Sampling ADC Digital Down Converter Q1 N sin Decimation NCO ADC 1 LNA Filter Filter cos Relative Power (dB) I1 N Signal2 Digital Down Converter Q2 Signal1 N sin fs Decimation NCO 2 Filter Frequency (Hz) cos (b) I2 N (a) FIGURE 11: (a) A block diagram schematic of a multiband RF-sampling ADC and (b) an example multiband digital down conversion. products existing between the dif- ing the number of interleaved sub- In a pipelined ADC, the data con- ferent channels. ADCs results in increased complex- version is broken down into a series of ity and typically higher overhead sub-ADCs that each operate at a lower Pipelined and Interleaved power. resolution, also intending to relax the High-Speed ADCs Direct sampling at the RF is gen- erally impractical because power consumption increases as a func- ADC4 tion of the sampling frequency, fS. Signal This is largely because switching ADC3 Input operations consume power propor- ADC2 tional to the switching speed, and generating clocks with low jitter ADC1 and distribution and buffering also require substantial power. Time Signal Sample Output interleaving uses a combination of Clock fs /4 Quadrature 0° Alignment M ADCs operating at an effective (fs) 90° sampling rate of fS /M as shown in Clock 180° Figure 12. In principle, each of the Generator 270° M sub-ADCs and the clocking are (a) easier to design since they are not operating near the limits of the technology. However, this does not Clock Input necessarily result in power savings 0° Clock because though each of the sub- 90° Clock ADCs ostensibly operates with a 180° Clock factor of M less power, there are M 270° Clock sub-ADCs. In reality, the need for (b) precision multiphase clocking and precise sample alignment requires FIGURE 12: (a) A block diagram schematic of a time-interleaved ADC and (b) an example additional overhead power. Increas- interleaved sampling operation. IEEE SOLID-STATE thorized licensed use limited to: Universitaetsbibliothek der RWTH Aachen. Downloaded on November 13,2024 at 22:12:24CIRCUITS UTC fromMAGAZINE SU M M E R 2 0apply. IEEE Xplore. Restrictions 22 61  Work on mixed-signal TXs has progressed found independently using superpo- sition, and the NTF has a high-pass directly into the mm-wave spectrum using frequency selectivity, while the STF embedded frequency multipliers. has an all-pass frequency selectivity, as shown in Figure 14(a). In the limit, a combination of high oversampling design requirements of the sub-ADCs, circuits. With proper calibration, these ratio (OSR) and a 1-b quantizer can be as shown in Figure 13. The stage RF-ADCs can operate with 2 5 GHz of used to achieve an ADC with an effec- 1 sub-ADC converts the first three bandwidth at a 10-b resolution. tive resolution 2 10 b. (most significant bits) and then feeds To utilize the T - R ADC as an RF- the residue to subsequent stages for Bandpass T − R ADCs ADC, the integrator can be replaced conversion of the remaining bits. T - R ADCs leverage a combination by a bandpass filter or a resonator Pipelining is typically more power of oversampling (e.g., fs 22 2 # fsignal) to yield a bandpass T - R ADC, as hungry than other architectures (e.g., and noise shaping to achieve high- shown in Figure 15(a). The reso- successive approximation), but it can precision data conversion while using nator/bandpass filter can be realized reduce the interleaving requirements. a relatively low-resolution signal as a passive LC-tank circuit or A combination of interleaving quantization. The schematic for embedded in an active g m LC filter and pipelining can lead to a more T - R ADCs with a 1-b quantizer is. In either case, the NTF is repre- optimal ADC design that achieves a shown in Figure 14(a). Here, a signal is sented by a “notch” or band-stop fre- high effective sampling rate at lower injected into a feedback loop consist- quency selectivity, while the STF is power than a purely interleaved or ing of an integrator, a c ­ omparator, and represented by a bandpass frequency purely pipelined ADC. This is a 1-b feedback DAC. The quantization selectivity, as shown in Figure 15(b). particularly true when digital cali- noise is modeled as being injected The advantage of the active configu- brations can be performed to digi- just before the 1-b quantizer. The ration is that some of the loss of the tally “trim” the individual pipelined noise- and signal-transfer functions passives can be cancelled using the stages and interleaving reconstruction (NTFs and STFs, respectively) can be active g m cell, and if strong enough, the cell can be programmed to oscil- late and provide a calibration signal. 12b Pipelined ADC The bandpass T - R ADC is typically limited to narrowband applications due to the requirements for rela- tively high OSR. It is also noted that Vin 3b 3b 3b 3b Sub-ADC Sub-ADC Sub-ADC Sub-ADC the bandpass T - R ADC also pro- (Stage 1) (Stage 2) (Stage 3) (Stage 4) vides only limited flexibility for mul- tiband operation because multiband or broadband resonators can be dif- 3b Dout 3b Dout 3b Dout 3b Dout ficult to realize without significant (MSB) loss, and the digital baseband filters must typically be optimized for a FIGURE 13: A block diagram of a pipelined ADC. given band of operation. M. fs Noise Gain Magnitude (dB) Vin + – Digital Vout Decimation Filter (at fs ) Signal DAC Frequency (Hz) (a) (b) FIGURE 14: (a) A block diagram of a D - R ADC. (b) The signal- and noise-transfer functions for the circuit in Figure 14(a). 62 useSUlimited thorized licensed IEEE SOLID-STATE M M E Rto:2 0Universitaetsbibliothek 22 derCIRCUITS MAGAZINE RWTH Aachen. Downloaded on November 13,2024 at 22:12:24 UTC from IEEE Xplore. Restrictions apply.  RF-Sampling Polar RXs to the TDC so that the ADC samples the potential system relaxation that The polar RX is a relative newcomer the signal at the correct instant to polar operation affords. architecturally ,. In conven- recover the signal amplitude accurately. tional Cartesian RXs [Figure 2(b)], a Though conceptually simple, some Conclusion and Future Work coherent detection is often required, complexity must be added to differ- Continued scaling of CMOS processes which requires synchronization and entiate between rising-/falling-edge has made the direct ­sampling of RF can increase power consumption as a zero crossings and to compensate signals practical. This has enabled result. This can be obviated in polar for pulse-shaping filtering. But architectural changes toward mixed- RXs by injection locking the local the results are encouraging given signal transceivers that provide oscillator with the incoming signal. Additionally, polar systems often have reduced resolution requirements compared to Cartesian systems. In M. fs polar systems, it is often possible to RFin use larger quantization steps as the + + Digital – – Bandpass BBout magnitude of the signal grows (i.e., Analog Analog Decimation (at fs ) the step size is not fixed). Finally, Filter Filter Filter in the phase path, the quantization step is driven by requirements for the acceptable phase step and is not DAC driven by noise requirements. An example RF-sampling polar RX (a) is shown in Figure 16(a). In the cir- cuit, a nonconstant envelope-modu- lated signal is simultaneously input Gain Magnitude (dB) Noise f3db to a time-to-digital converter (TDC) and an ADC. The TDC is clocked by a global reference clock from a fre- quency synthesizer, and the phase of the signal is recovered by comparing the input signal’s “zero crossing” to Signal that of the reference, as shown in Fig- ure 16(b). Once the phase of the signal fc Frequency (Hz) is known, it is known that the peak (b) of the signal will occur 90c after the zero crossing. This allows the global FIGURE 15: (a) A block diagram of a “bandpass” D - R ADC. (b) The signal- and noise-trans- reference clock to be delayed relative fer functions for the circuit in Figure 15(a). –λ/4 Signal A ADC A Polar Demodulator Delay φ φ Ref. Clock TDC Synthesizer (a) (b) FIGURE 16: (a) A block diagram schematic of an RF-sampling polar RX and (b) waveforms demonstrating the sampling operation. Ref.: reference. (Source:.) IEEE SOLID-STATE thorized licensed use limited to: Universitaetsbibliothek der RWTH Aachen. Downloaded on November 13,2024 at 22:12:24CIRCUITS UTC fromMAGAZINE SU M M E R 2 0apply. IEEE Xplore. Restrictions 22 63  Mixed-signal transceivers will be particularly pp. 1320–1330, 2017, doi: 10.1109/JSSC. 2016.2626277. instrumental in enabling future hybrid and S.-W. Yoo, S.-C. Hung, and S.-M. Yoo, “A watt-level quadrature class-G switched- capacitor power amplifier with lineariza- digital beamforming systems, owing to their tion techniques,” IEEE J. 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