লজিক গেট ও কম্বিনেশনাল সার্কিটস 1 PDF

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x™Äyëûé Ÿé 1 ¡!?†þ öˆØþ ~î‚ †þ!Áºöìl¢l¡ ¤y!†ÅþØäþ¤  x™Äyëû− 1 ¡!?†þ öˆØþ ~î‚ †þ!Áºöìl¢l ¤y!†ÅþØþ þ›y‘þĤ)!‹þ î%¡#ëû î#?ˆ!”öì þîû þ›)îÅKþyl G ¡!?†þ öˆØþ ¤yîØþÆyQîû ¤îÅ?l#l öˆØþ ôy!ÎØþöì²Õ:yîû !mhßìîû#ëû î Åþl# îy Two-Level Circuit !’þéŸéôy!ÎØþöì²Õ:yîû ¤‚ë%_« ¡!?†þ î Åþl# !’þöì†þy’þyîû !î!èþ§¬ ™îûöìlîû ¤‚ë%_« ¡!?†þ î Åþl# ~löì†þy’þyîû xÄy’þyîû Question Pattern MCQ VSAQ SAQ SAQ LAQ Total (1 Mark) (1 Mark) (1 Marks) (3 Marks) (7 Mark) 1×5=5 — 1×4=4 — 7×1=7 16 †þ# ?ylîÚ ~¥z x™Äyëû öíöì†þ xyôîûy !lÁ¬!¡!‡ þ !î£ìëû=!¡ 5 !mhßìîû#ëû î Åþl# G þyîû ²Ì†þyîûöìèþ˜ ?ylöì þ þ›y!îû韟Ÿé 6 ¤‚ë%_« ¡!?†þ î Åþl#îû ¤‚KþyÐ 1 ~†þy˜¢ ö×!”öì þ î%¡#ëû î#?ˆ!” þ– ¤ þĤyîû!” !î!èþ§¬ 7 !î!èþ§¬ ™îûöìlîû ¤‚ë%_« ¡!?†þ î Åþl# ŒxÄy’þyîû– ¤)e ¤Á›öì†Åþ ²Ìy® Kþyöìlîû þ›%lîûyëû xl%¢#¡lÐ ¤yîØþÆyQîû– ôy!ÎØþöì²Õ:yîû– !’þéŸéôy!ÎØþöì²Õ:yîû– !’þöì†þy’þyîû 2 !î!èþ§¬ ¡!?†þ öˆØþ G þyöì˜îû ÷î!¢ÜTĤô)¥Ð ~î‚ ~löì†þy’þyîûŠéŸé~îû ¤ þĤyîû!”– î%¡#ëû îûy!¢ôy¡y– 3 ¤îÅ?l#l öˆØþ G xlÄylÄ !îö좣ì öˆØþ¤ô)¥Ð îφþ !‹þe– ¡!?†þ ’þyëûy@ýÌyô G þyöì˜îû †þyëÅþ›m*! þ 4 ¤îÅ?l#l öˆöìØþîû ¤y¥yöìëÄ öˆØþ ÷ þ!îûÐ ¤Á›öì†ÅþÐ x™Äyëû¤)!‹þ 1.1. è)þ!ô†þy 3 1.11. xÄy’þyîû 6 1.2. î%¡#ëû xöìþ›Çþ†þ 3 1.12. ¤yîØþÆÄyQîû 7 1.3. î%¡#ëû î#?ˆ!”öì þîû ¤)eyî¡# 3 1.13. ôy!ÎØþöì²Õ:yîû 7 1.4. ö²Ìy’þyQ ØþyôÅ G !ôlØþyôÅ 3 1.14. î!’þéŸéôy!ÎØþöì²Õ:yîû 8 1.5. ¤yôØþyôÅ G ôÄy:ØþyôÅ 3 1.15. !’þöì†þy’þyîû 9 1.6. ¡!?†þ öˆØþ 4 1.16. ~löì†þy’þyîû 10 1.7. !î!èþ§¬ ¡!?†þ öˆØþ ¤Á›öì†Åþ ™yîû”y 4 1.17. Key-Notes 10 1.8. !mhßìîû#ëû î Åþl# (Two Level Circuit) 5 1.18. ?yly þíÄ 11 1.9. ¤îÅ?l#l (Universal) öˆØþ 5 1.19. ¤½þyîÄ ²ÌÙÀyî¡# 11 1.10. †þ!Áºöìl¢ly¡ ¤y!†ÅþØþ îy ¤‚ë%_« ¡!?†þ î Åþl# 6 1.20. !¢Çþ†þô[þ¡#îû þ›îûyô¢Å 17 Class-10 my˜¢ ö×!” |†þ!Á›’þz Bengali | Chapter Øþyîû xÄy!²Õ Name öì†þ¢l ¡!?†þ öˆØþ ~î‚ †þ!Áºöìl¢ly¡ ¤y!†ÅþØäþ¤ ¤‚öìÇþöìþ› !î£ìëûîéÝ ŒBrief Content) 1.3 î%¡#ëû î#?ˆ!”öì þîû !î!èþ§¬ ¤)e: þ ¤)öìeîû lyô ¤)öìeîû Statement 1.1 è)þ!ô†þy: 1 Associative Law (a) a + (b + c) = (a + b) + c !’þ!?Øþy¡ †þ!Á›’þzØþyîû ¤†þ¡ ²Ì†þyîû ˆy!”! þ†þ G (b) a.(b.c) = (a.b).c 2 Commutative Law (a) a + b = b + a öëï!_«†þ !e«ëûy ¤Á›y˜öìlîû ?lÄ îy¥zly!îû ¤‚‡Äy (b) a. b = b. a xíÅyê ‘1’ G ‘0’ îÄî¥yîû †þöìîûÐ îy¥zly!îû ¤‚‡Äyîû 3 Distributive Law (a) a.(b + c) = (a.b) + (a.c) ¤y¥yöìëÄ xyôyöì˜îû ‹þ %þß›yöìÙ»Åîû ¤†þ¡ þíÄ ~†þ!Øþ (b) (a + b). c = (a+b). (a+c) 4 Identity Law !îöì¢£ì ¤y‚!‡Ä†þ (Digital) îû*þ› þ›yëûÐ þíÄ xy¥îû”– (a) a + 0 = a ¤Méþëû– ²Ì!e«ëûy†þîû”– æþ¡²Ì˜yl韟Ÿé ~¥z ¤†þ¡ öÇþöìe 5 Complement Law (b) a. 1 = a (a) a + a = 1 ~¥z ¤y‚!‡Ä†þ îy !’þ!?Øþy¡ îû*þ›öì†þ¥z †þ!Á›’þzØþyîû (b) a. a = 0 îÄî¥yîû †þöìîûÐ ~¥z !’þ!?Øþy¡ þíÄöì†þ ²Ì!e«ëûy†þîûöì”îû 6 De Morgains Law (a) (a+b) = a. b ?lÄ îÄî¥* þ ¥ëû !îö좣ì ë%!_«!î˜Äy韟Ÿé ëyöì†þ xyôîûy (b) a. b = a + b 7 Boundadn’s Law î%¡#ëû î#?ˆ!” þ lyöìô ?y!lÐ î%¡#ëû î#?ˆ!”öì þîû (a) a + 1 = 1 (b) a. 0 = 0 þ_´ G ¤)eöì†þ ¤Á›y˜l †þîûyîû ?lÄ îÄî¥* þ ¥ëû 8 Idempeotent Law (a) a + a = a ¡!?†þ öˆØþÐ ¡!?†þ öˆØþ !î!èþ§¬ IC myîûy ÷ þ!îû (b) a. a = a 9 Absorption Law ¥ëûÐ ¡!?†þ öˆØþ¥z ¥¡ ¤†þ¡ !’þ!?Øþy¡ î Åþl#îû (a) a. (a + b) = a (b) a + ab = a ˆ‘þlˆ þ G †þyëň þ ~†þ†þÐ xyîyîû x¤‚‡Ä ¡!?†þ 9 Involution Law a = a, a = 0 öˆØþ ¤!Á¿!¡ þ ¥öìëû¥z ÷ þ!îû ¥ëû †þ!Áºöìl¢ly¡ ¤y!†ÅþØþ îy ¤‚ë%_« ¡!?†þ î Åþl#Ð 1.4 ö²Ìy’þyQ ØþyôÅ G !ôl ØþyôÅ (Product Term î%¡#ëû î#?ˆ!” þ− î%¡#ëû î#?ˆ!” þ ¥¡ ˆ!” þ G and Min term: ë%!_«îû ¤‚öìëyöìˆ ÷ þ!îû ~†þ²Ì†þyîû î#?ˆ!” þ öë‡yöìl ö†þyöìly î%¡#ëû îûy!¢ôy¡yëû ë‡l ~†þy!™†þ ‹þ¡îûy!¢ ²Ì! þ!Øþ ‹þ¡îûy!¢îû ôyl ¥ëû ¤ þÄ (True) îy !ôíÄy †þô!²ÕöìôöìrØþ’þ îy lléŸé†þô!²ÕöìôöìrØþ’þ xîßiyîû =” îy (False)Ð !îÊ!Øþ¢ ˆ!” þKþ ??Å î%¡ ²Ìíô î%¡#ëû AND ²Ì!e«ëûy myîûy ë%_« íyöì†þ þ‡l þyöì†þ ö²Ìy’þyQ î#?ˆ!” þ ²Ìî Åþl †þöìîûlÐ ‹þ¡îûy!¢îû ôyl ¤ þÄ ¥öì¡ ØþyôÅ îöì¡Ð öëôl韟Ÿé A´.B.C, A.B.C´ ¥z þÄy!˜Ð þyöì†þ ‘1’ ~î‚ !ôíÄy ¥öì¡ þyöì†þ ‘0’ myîûy ²Ì†þy¢ ö†þyöìly î%¡#ëû xöìþ›Çþöì†þ îÄî¥* þ ¤†þ¡ î%¡#ëû ‹þ¡îûy!¢ †þîûy ¥ëûÐ ë!˜ †þô!²ÕöìôöìrØþ’þ îy lléŸé†þô!²ÕöìôöìrØþ’þ xîßiyëû î%¡#ëû î#?ˆ!”öì þîû ô)¡ ²Ì!e«ëûy=!¡ ¥¡ AND îy ö†þyöìly ö²Ìy’þyQ ØþyöìôÅ ’þzþ›!ßi þ íyöì†þ– þ‡l þyöì†þ =”– OR îy öëyˆ ~î‚ þ›!îûþ›)îû†þ îy †þô!²ÕöìôrØþÐ !ôl ØþyôÅ îöì¡Ð öëôl韟Ÿé ¤ þĤyîû!” − ö†þyöìly î%¡#ëû xöìþ›Çþ†þ îy æþy‚¢yléŸé~îû F = A.B.C + A.B+B.C ¤†þ¡ ¤½þyîÄ ¥zlþ›%Øþ G ²Ìy® xy’þzØþþ›%Øþöì†þ ë‡l ¤ þÄ xíîy ‘1’ G !ôíÄy ‘0’ ~îû ¤y¥yöìëÄ ~†þ!Øþ ¤yîû!”îû !ôl ØþyôÅ !ôl ØþyôÅ lëû xy†þyöìîû ²Ì†þy¢ †þîûy ¥ëû þ‡l þyöì†þ ¤ þĤyîû!” îy Œ¤†þ¡ ‹þ¡îûy!¢ ŒA xl%þ›!ßi þŠ Truth Table îöì¡Ð ’þzþ›!ßi þŠ 1.2 î%¡#ëû xöìþ›Çþ†þ îy î%¡#ëû æþy‚¢yl: !ôl ØþyôÅ lëû î%¡#ëû ‹þ¡îûy!¢=!¡ !î!èþ§¬ î%¡#ëû ²Ì!e«ëûy (AND, ŒC xl%þ›!ßi þŠ OR, NOT) ¥z þÄy!˜ myîûy ë%_« ¥öìëû ë‡l ~†þ!Øþ 1.5 ¤yô ØþyôÅ G ôÄy: ØþyôÅ (Sum term and ˜#‰Å îûy!¢ôy¡y îy xöìþ›Çþ†þ ˆ‘þl †þöìîû– þyöì†þ î%¡#ëû Max term): xöìþ›Çþ†þ îy ‘Boolean Function’ îöì¡Ð ö†þyöìly î%¡#ëû îûy!¢ôy¡yëû ë‡l ~†þy!™†þ ‹þ¡îûy!¢ ’þz˜y¥îû”− F (A, B) = A’B + AB’ †þô!²ÕöìôöìrØþ’þ îy lléŸé†þô!²ÕöìôöìrØþ’þ xîßiyëû öëyˆ îy 3 Class-10 my˜¢ ö×!” |†þ!Á›’þz Bengali | Chapter Øþyîû xÄy!²Õ Name öì†þ¢l ¡!?†þ öˆØþ ~î‚ †þ!Áºöìl¢ly¡ ¤y!†ÅþØäþ¤ OR ²Ì!e«ëûy myîûy ë%_« íyöì†þ þ‡l þyöì†þ ¤yô ØþyôÅ 1.6 ¡!?†þ öˆØþ: Sum term) îöì¡Ð öë îφþ!‹þöìeîû ¤y¥yöìëÄ ö†þyöìly î%¡#ëû îûy!¢ôy¡y îy öëôl韟Ÿé (A + B + C ), ( A + B + C) ¥z þÄy!˜Ð xöìþ›Çþ†þöì†þ ~†þ!Øþ !’þ!?Øþy¡ î Åþl#îû îû*þ› ö˜Gëûy ¥ëû ö†þyöìly î%¡#ëû xöìþ›Çþöì†þ îÄî¥* þ ¤†þ¡ î%¡#ëû ‹þ¡îûy!¢ þyöì†þ Logic Gate îöì¡Ð ë!˜ †þô!²ÕöìôöìrØþ’þ îy lléŸé†þô!²ÕöìôöìrØþ’þ xîßiyëû ¡!?†þ öˆØþ=!¡ ¥z!rØþöì@ýÌöìØþ’þ ¤y!†ÅþØþ (IC) myîûy ÷ þ!îû ö†þyöìly ¤yô ØþyôÅéŸé~ ’þzþ›!ßi þ íyöì†þ– þ‡l þyöì†þ Max †þîûy ¥ëû öë!Øþöì þ ¤‚öì†þ þ @ýÌ¥” †þîûyîû ?lÄ ~†þ îy term îöì¡Ð öëôl韟Ÿé ~†þy!™†þ ¥zlþ›%Øþ íyöì†þ G xy’þzØþþ›%Øþ ö˜‡yöìlyîû ?lÄ ~†þ!Øþ xy’þzØþþ›%Øþ íyöì†þÐ F = (A + B + C). (A + B). (B + C) Max term A, Max term lëû B, C A xl%þ›!ßi þ ¤†þöì¡ ’þzþ›!ßi þ Max term lëû C xl%þ›!ßi þ 1.7 !î!èþ§¬ ¡!?†þ öˆØþ ¤Á›öì†Åþ ™yîû”y : öˆöìØþîû lyô ²Ì†þyîû ë%!_«ˆ þ !‹þe !lˆÅôl xöìþ›Çþ†þ ¤ þÄ ¤yîû!” AND öî!¤†þ öˆØþ f = A.B 1 A f=A.B = A AND B A B f = AB. B 0 0 0 0 1 0 1 0 0 1 1 1 OR öî!¤†þ öˆØþ f=A+B 2 A f=A+B A B f =A+B = A OR B B 0 0 0 0 1 1 1 0 1 1 1 1 NOT öî!¤†þ öˆØþ f= A 3 A f=A A f =A = NOT A 0 1 1 0 4 NAND öëï!ˆ†þ öˆØþ A f = A.B f=A.B A B. f = AB B = A NAND B 0 0 1 0 1 1 1 0 1 1 1 0 4 Class-10 my˜¢ ö×!” |†þ!Á›’þz Bengali | Chapter Øþyîû xÄy!²Õ Name öì†þ¢l ¡!?†þ öˆØþ ~î‚ †þ!Áºöìl¢ly¡ ¤y!†ÅþØäþ¤ öˆöìØþîû lyô ²Ì†þyîû ë%!_«ˆ þ !‹þe !lˆÅôl xöìþ›Çþ†þ ¤ þÄ ¤yîû!” 5 NOR öëï!ˆ†þ öˆØþ A f = A+B f=A+B = A NOR B A B f =A+B B 0 0 1 0 1 0 1 0 0 1 1 0 6 XOR öëï!ˆ†þ öˆØþ f=AÅ B A f = AB A B f = A⊕B = A XOR B B =A´B+A.B´ 0 0 0 0 1 1 1 0 1 1 1 0 7 XNOR öëï!ˆ†þ öˆØþ f=A B A f=A. B A B f = AB = A XNOR B B 0 0 1 =A.B+ A. B 0 1 0 1 0 0 1 1 1 1.8 !mhßìîû#ëû î Åþl# îy Two Level Circuit: A A !’þ!?Øþy¡ î Åþl#öì þ ¥zlþ›%Øþ G xy’þzØþþ›%öìØþîû ôyVþ‡yöìl îÄî¥* þ ¡!?†þ öˆØþ=!¡ !î!èþ§¬ hßìöìîû xîßiyl †þöìîû NAND gate îÄî¥yîû †þöìîû NOR gate ÷ þ!îû韟Ÿé !l!˜ÅÜT î Åþl#!Øþ ˆ‘þl †þöìîûÐ ~öì†þ î Åþl#îû hßìîû !îlÄy¤ A.B=A+ B =A+B îöì¡Ð î Åþl#îû ¡!?†þ öˆØþ=!¡ !mhßìîû#ëû– !ehßìîû#ëû– A A ‹þ %þhßìîû#ëû ¥z þÄy!˜èþyöìî !îlÄhßì íy†þöì þ þ›yöìîûÐ A.B=A+B=A+B öë¤ôhßì !’þ!?Øþy¡ î Åþl#öì þ ¡!?†þ öˆØþ=!¡ ˜%!Øþ hßìöìîû B B !îlÄhßì íyöì†þ– þyöì†þ !mhßìîû#ëû î Åþl# îöì¡Ð !mhßìîû#ëû î Åþl# ˜%éŸé²Ì†þyîû韟Ÿé NAND gate îÄî¥yîû †þöìîû AND gate ÷ þ!îû韟Ÿé (i) AND—OR î Åþl# îy SOP î Åþl# A.B =A.B (ii) OR—AND î Åþl# îy POS î Åþl# A 1.9 ¤îÅ?l#l öˆØþ: A.B A.B=A.B NAND G NOR öˆØþöì†þ ¤îÅ?l#l öˆØþ î¡y ¥ëû– B †þyîû” ’þz_« öˆØþ ˜%!Øþ îÄî¥yîû †þöìîû NOT, AND NOR gate îÄî¥yîû †þöìîû ô)¡ öˆØþ=!¡ ÷ þ!îû韟Ÿé ~î‚ OR ~¥z öî!¤†þ öˆØþ=!¡ ÷ þ!îû †þîûy ëyëûÐ ~ NOR gate îÄî¥yîû †þöìîû NOT gate ÷ þ!îû韟Ÿé Séy’þüyG NAND G NOR öˆØþ îÄî¥yîû †þöìîû xlÄylÄ A+A = = A. A = A öëï!_«†þ !e«ëûyîû îyhßìî ¤ þÄ þy ?yly ëyëûÐ ¤îÅ?l#l öˆØþ îÄî¥yîû †þöìîû ô)¡ öˆØþ=!¡ (AND, OR, NOT) ²ÌéÝ þ †þîûy : NOR gate îÄî¥yîû †þöìîû AND gate ÷ þ!îû韟Ÿé NAND gate îÄî¥yîû †þöìîû ô)¡ öˆØþ=!¡ ²ÌéÝ þ韟Ÿé A.B=A. B =A.B NAND gate îÄî¥yîû †þöìîû NOT gate ÷ þ!îû韟Ÿé A.A=A+A=A 5 Class-10 my˜¢ ö×!” |†þ!Á›’þz Bengali | Chapter Øþyîû xÄy!²Õ Name öì†þ¢l ¡!?†þ öˆØþ ~î‚ †þ!Áºöìl¢ly¡ ¤y!†ÅþØäþ¤ A A î¡y ¥ëûÐ xÄy’þyîû ˜%¥z ²Ì†þyîûÐ (i) ¥yæþ xÄy’þyîû韟Ÿé ˜%!Øþ !îöìØþîû öëyˆæþ¡ !l”Åëû †þîûöì þ îÄî¥* þ ¥ëûÐ B B (ii) æ%þ¡ xÄy’þyîû韟Ÿé! þl!Øþ !îöìØþîû öëyˆæþ¡ !l”Åëû †þîûöì þ îÄî¥* þ ¥ëûÐ NOR gate îÄî¥yîû †þöìîû OR gate ÷ þ!îû韟Ÿé ÷î!¢ÜTÄ: A+B = A + B ¥yæþ G æ%þ¡ xÄy’þyöìîûîû ˜%!Øþ ¥zlþ›%Øþ G ˜%!Øþ xy’þzØþþ›%ØþÐ A A+B A+B=A+B öëyˆæþ¡ (Sum) ~î‚ †þÄy!îû (Carry). Half AdderéŸé~îû ØþÆ$í öØþ!î¡– î%¡#ëû îûy!¢ôy¡y G B ¡!?†þ ’þyëûy@ýÌyô韟Ÿé ~†þ!Øþ †þ!Áºöìl¢ly¡ ¡!?†þ ¤y!†ÅþØþ îy ¤‚ë%_« ¡!?†þ Input Output î Åþl# †þ þ†þ=!¡ ¡!?†þ öˆØþéŸé~îû ¤ô§ºöìëû ÷ þ!îû ¥ëûÐ ~¥z î Åþl#îû xy’þzØþþ›%Øþ ¤îûy¤!îû þyîû ¥zlþ›%Øþ öíöì†þ ŒG¥z A B Sum Carry ¤ôöìëû ²Ì˜_Š !l™Åy!îû þ ¥ëûÐ ~îû xy’þzØþþ›%Øþ ~îû þ›)îÅî Åþ# 0 0 0 0 ö†þyöìly ¥zlþ›%Øþ îy xy’þzØþþ›%öìØþîû Gþ›îû !lèÅþîû †þöìîû lyÐ 0 1 1 0 ~†þ!Øþ †þ!Áºöìl¢ly¡ î Åþl#îû þíÄ ²Ì!e«ëûy†þîû” þ›m*! þ 1 0 1 0 !†þéS%é î%¡#ëû xöìþ›Çþ†þ (Boolean Function) myîûy 1 1 0 1 !l™Åy!îû þ ¥ëûÐ ~†þ!Øþ †þ!Áºöìl¢ly¡ î Åþl#îû ¤y™yîû” Sum = A.B + A.B. = A Å B îφþ!‹þe (Block Diagram)!Øþ ¥¡ !lÁ¬îû*þ›éŸŸŸé Carry = A.B A B n¤‚‡Ä† † !Áºöìl¢ly¡ m¤‚‡Ä† AB (sum) ¡!?† xy’ zØ ›%Ø ¥zl ›%Ø î Å l# !‹þe 1: ~†þ!Øþ †þ!Áºöì¢ly¡ ¡!?†þ î Åþl#îû îφþ!‹þe AB(Carry) 1.10 Combinational Logic Circuit îy ¤‚ë%_« ¡!?†þ î Åþl#îû ÷î!¢ÜTÄ: ~†þ¥zèþyöìî Full AdderéŸé~îû ØþÆ$í öØþ!î¡– ¡!?†þ †þ!Áºöìl¢ly¡ ¡!?†þ ¤y!†ÅþØþ îy ¤‚ë%_« ¡!?†þ î Åþl#îû ö†þyöìly öôöìôyîû# îy ß¿,! þèþy[þyîû öl¥zÐ ’þyëûy@ýÌyô G î%¡#ëû îûy!¢ôy¡y ¥¡ !lÁ¬îû*þ›éŸŸŸé ~îû xy’þzØþæ%þØþ Ö™%ôye ö¤¥z ô%¥)öì Åþîû ¥zlþ›%öìØþîû Gþ›îû Input Output !lèÅþîû †þöìîû– þ›)îÅî Åþ# ¥zlþ›%Øþ î Åþôyl xy’þzØþþ›%öìØþîû Gþ›îû A B Cin Sum Carry ö†þyöìly ²Ìèþyî öæþöì¡ lyÐ 0 0 0 0 0 !îö좣ì =îû&cþ›)”Å †þ!Áºöìl¢ly¡ ¡!?†þ ¤y!†ÅþØþ=!¡ ¥¡ 0 0 1 1 0 (i) xÄy’þyîû (Adder) 0 1 0 1 0 (ii) ¤yîØþÆÄyQîû (Subtractor) 0 1 1 0 1 (iii) ôy!ÎØþöì²Õ:yîû (Multiplexer) 1 0 0 1 0 (iv) !’þéŸéôy!ÎØþöì²Õ:yîû (De-Multiplexer) 1 0 1 0 1 (v) !’þöì†þ’þyîû (Decoder) 1 1 0 0 1 (vi) ~löì†þy’þyîû (Encoder) 1 1 1 1 1 1.11 xÄy’þyîû (Addar): îy¥zly!îû ¤‚‡Äyîû öëyˆæþ¡ !l”Åëû †þîûyîû ?lÄ öë Sum = A.B.Cin+A.B. Cin +A.B. Cin +A.B.Cin ¤‚ë%_« ¡!?†þ î Åþl# îÄî¥yîû †þîûy ¥ëû þyöì†þ xÄy’þyîû = A(B.Cin+B. Cin )+A(B. Cin +B.Cin) 6 Class-10 my˜¢ ö×!” |†þ!Á›’þz Bengali | Chapter Øþyîû xÄy!²Õ Name öì†þ¢l ¡!?†þ öˆØþ ~î‚ †þ!Áºöìl¢ly¡ ¤y!†ÅþØäþ¤ = A(BÅCin)+A(BÅCin ) æ%þ¡ xÄy’þyöìîûîû lÄyëû æ%þ¡ ¤yîØþÆÄyQîû î Åþl#G ÷ þ!îû = AÅ(BÅCin) †þîûy ëyëûÐ = AÅBÅCin 1.13 ôy!ÎØþöì²Õ:yîû: Carry = A.B.Cin+A.B.Cin+A.B. Cin +A.B.Cin öë ¤‚ë%_« ¡!?†þ î Åþl# xöìl†þ=!¡ ¥zlþ›%Øþ ¡y¥zöìlîû = Cin (A.B+A.B) + AB.(Cin +Cin) îy¥zly!îû þöìíÄîû ôöì™Ä öíöì†þ ö†þyöìly ~†þ!Øþ öîöìSé = Cin (AÅB) + AB !löìëû ö¤!Øþ þyîû ~†þ!Øþôye xy’þzØþþ›%Øþ ¡y¥zöìlîû ô™Ä !˜öìëû þ›y!‘þöìëû ö˜ëû þyöì†þ ôy!ÎØþöì²Õ:yîû îöì¡Ð 1.12 ¤yîØþÆÄyQîû (Subtractor): ôy!ÎØþöì²Õ:yöìîû ˜%!Øþ !èþ§¬ ™îûöìlîû ¥zlþ›%Øþ ¡y¥zöìlîû ö¤Øþ ¤yîØþÆÄyQîû ¥¡ !îöìëûyˆæþ¡ !l”Åyëû†þÐ îy¥zlyîû# !îöìØþîû íyöì†þ韟Ÿé ¥zlþ›%Øþ ö’þØþyîû ö¤Øþ G !lëûsf†þ ¥zlþ›%öìØþîû ö¤ØþÐ !îöìëûyˆæþ¡ !l”Åëû †þîûöì þ ¤yîØþÆÄyQîû îÄî¥yîû †þîûy ¥ëûÐ ¥zlþ›%Øþ ö’þØþyîû ö¤öìØþîû ¤öìD !lëûsf†þ ¥zlþ›%Øþ ö¤öìØþîû xÄy’þyöì î û î û ôöì þy ¤yîØþÆ Ä yQîû G ˜% ¥ z ²Ì†þyîû Ð ¥yæþ ¤‚‡Äyîû ~†þ!Øþ ˆy!”! þ†þ ¤Á›†Åþ xyöìSéÐ 2n ¤‚‡Ä†þ ¤yîØþÆÄyQîû G æ%þ¡ ¤yîØþÆÄyQîûÐ ö’þØþy ¡y¥zl !lîÅy‹þl †þîûyîû ?lÄ n ¤‚‡Ä†þ !lëûsf†þ ˜%!Øþ îy¥zly!îû !îöìØþîû !îöìëûyˆæþ¡ !l”Åëû †þîûöì þ ¥yæþ ¡y¥zl ²Ìöìëûy?lÐ ¤yîØþÆÄyQîû G ! þl!Øþ îy¥zly!îû !îöìØþîû !îöìëûyˆæþ¡ !l”Åëû N ¤‚‡Ä†þ ö’þØþy ¥zlþ›%Øþ ¡y¥zl G 1!Øþ xy’þzØþþ›%Øþ ë%_« †þîûöì þ æ%þ¡ ¤yîØþÆÄyQîû îÄî¥* þ ¥ëûÐ ¤yîØþÆÄyQîû î Åþl#îû ôy!ÎØþöì²Õ:yîûöì†þ N × 1 ôy!ÎØþöì²Õ:yîû îöì¡Ð ˜%!Øþ xy’þzØþþ›%Øþ ¥¡ Difference ~î‚ Borrow. ~†þ!Øþ Half-SubtractoréŸé~îû Truth Table, î%¡#ëû I0 I1 îûy!¢ôy¡y G ¡!?†þ ’þyëûy@ýÌyô韟Ÿé I2 n 2 × 1 MUX 0 I3 Input Output A B Diff Borrow I2n–1 0 0 0 0 0 1 1 1 S0 S1 S2 Sn–1 1 0 1 0 ~†þ!Øþ 4 × 1 ôy!ÎØþöì²Õ:yîûéŸé~îû Truth Table î%¡#ëû 1 1 0 0 îûy!¢ôy¡y G ¡!?†þ ’þyëûy@ýÌyô韟Ÿé î%¡#ëû îûy!¢ôy¡y韟Ÿé Select Input Output Difference = A.B + A.B = AÅB S0 S1 Y Borrow = A.B A B 0 0 I0 0 1 I1 AB 1 0 I2 1 1 I3 A.B î%!¡ëû îûy!¢ôy¡y韟Ÿé S0. S1.I0 + S0 S1I1 + S0 S1 I2 +S0S1I3 7 Class-10 my˜¢ ö×!” |†þ!Á›’þz Bengali | Chapter Øþyîû xÄy!²Õ Name öì†þ¢l ¡!?†þ öˆØþ ~î‚ †þ!Áºöìl¢ly¡ ¤y!†ÅþØäþ¤ S1 S0 I0 S0 S1 I0 I1 S0 S1 I1 Y I2 S0 S1 I2 I3 S0 S1 I3 4 × 1 Multiplexer 1.14 De-Multiplexer Œ!’þéŸéôy!ÎØþöì²Õ:yîûŠ !’þéŸéôy!ÎØþöì²Õ:yîû ¥¡ ~ôl ~†þ!Øþ ¤‚ë%_« ¡!?†þ î Åþl#– ëyîû †þôÅþ›m*! þ ôy!¡öìØþöì²Õ:yöìîûîû !‘þ†þ !îþ›îû# þÐ ~¥z î Åþl#öì þ ~†þ!Øþôye ¥zlþ›%Øþ G 2n ¤‚‡Ä†þ xy’þzØþþ›%Øþ G n ¤‚‡Ä†þ !¤ö졆þ¢yl ¡y¥zl íyöì†þÐ ~¥z î Åþl#îû Selection line =!¡ ~îû ~†þ!Øþôye ¥zlþ›%Øþ ¡y¥zl öíöì†þ þíÄ !löìëû xöìl†þ=!¡ xy’þzØþþ›%Øþ ¡y¥zöìlîû ôöì™Ä öíöì†þ ö†þyöìly ~†þ!Øþöì þ ö²Ìîû” †þöìîûÐ ~†þ!Øþ 1×4 De-Multiplexer Input Output S1 S0 O3 O2 O1 O0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0 ØþÆ$í öØþ!î¡ î%¡#ëû îûy!¢ôy¡y韟Ÿé O 0= S 0 S 1 I O 1= S 0 S 1I O2=S0 S1 I O3=S0S1I 8 Class-10 my˜¢ ö×!” |†þ!Á›’þz Bengali | Chapter Øþyîû xÄy!²Õ Name öì†þ¢l ¡!?†þ öˆØþ ~î‚ †þ!Áºöìl¢ly¡ ¤y!†ÅþØäþ¤ O0 O1 I 1 × 4 DMUX O2 O3 S1 S0 !‹þeé/ 1 × 4 DMUX 1.15 !’þöì†þy’þyîû (Decoder): !’þöì†þy’þyîû ¥¡ ~ôl ~†þ!Øþ ¤‚ë%_« ¡!?†þ î Åþl# ëy n ¤‚‡Ä†þ ¥zlþ›%Øþ ¡y¥zl öíöì†þ îy¥zly!îû þíÄ @ýÌ¥” †þöìîû ¤öìîÅyF‹þ 2n ¤‚‡Ä†þ xy’þzØþþ›%öìØþ ¥z’þz?yîû îy îÄî¥yîû†þyîû#îû öîy™ˆôÄ þöìíÄ îû*þ›yhsý!îû þ †þöìîûÐ !î!èþ§¬ !’þöì†þy’þyîû î Åþl# !î!èþ§¬ †þyöì? îÄî¥* þ ¥ëûÐ öëôl韟Ÿé (i) 3 to 8 Decoder îy îy¥zly!îû Ø%þ xQy¡ !’þöì†þy’þyîûÐ (ii) 4 to 10 Decoder îy îy¥zly!îû Ø%þ ö’þ!¤öìô¡ !’þöì†þy’þyîûÐ ~†þ!Øþ îy¥zly!îû Ø%þ xQy¡ !’þöì†þy’þyöìîûîû Truth Table, î%¡#ëû îûy!¢ôy¡y G Block Diagram : ~†þ!Øþ 3 to 8 !’þöì†þy’þyöìîû ¥zlþ›%Øþ ¡y¥zöìlîû ¤‚‡Äy ! þl!Øþ G xy’þzØþþ›%Øþ ¡y¥zöìlîû ¤‚‡Äy 8!ØþÐ Input Output A B C D0 D1 D2 D3 D4 D5 D6 D7 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1 î%¡#ëû îûy!¢ôy¡y: D0 = A. B. C D4 = A. B. C D1 = A. B. C D5 = A. B. C D2 = A. B. C D6 = A. B. C D3 = A. B. C D7 = A. B. C D0 A D1 D2 3×8 D3 B Decoder D4 D5 C D6 D7 9 Class-10 my˜¢ ö×!” |†þ!Á›’þz Bengali | Chapter Øþyîû xÄy!²Õ Name öì†þ¢l ¡!?†þ öˆØþ ~î‚ †þ!Áºöìl¢ly¡ ¤y!†ÅþØäþ¤ 1.16 ~löì†þy’þyîû (PEncoder): ~löì†þy’þyîûéŸé~îû †þyëÅþ›m*! þ !’þöì†þy’þyöìîûîû !‘þ†þ !îþ›îû# þÐ xíÅyê ~¥z î Åþl# ¤öìîÅyF‹þ 2n ¤‚‡Ä†þ ¥zlþ›%Øþ ¡y¥zl öíöì†þ þíÄ @ýÌ¥” †þöìîû n ¤‚‡Ä†þ xy’þzØþþ›%Øþ ¡y¥zöìlîû ôy™Äöìô ¤ô %þ¡ îy¥zly!îû þíÄ ²ÌéÝ þ †þöìîûÐ !î!èþ§¬ ~löì†þy’þyîû=!¡ xQy¡éŸéØ%þéŸéîy¥zly!îû ~löì†þy’þyîû– ö’þ!¤öìô¡éŸéØ%þéŸéîy¥zly!îû ~löì†þy’þyîû ¥z þÄy!˜Ð ~†þ!Øþ xQy¡éŸéØ%þéŸéîy¥zly!îû ~löì†þy’þyîû Input Output E0 E1 E2 E3 E4 E5 E6 E7 A B C 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 Truth Table î%¡#ëû îûy!¢ôy¡y韟Ÿé A = E4 + E5 + E6 + E7 B = E2 + E3 + E6 + E7 C = E1 + E3 + E5 + E7 E0 E1 E2 Octal A E3 to E4 B E5 binary E6 C E7 Encloder Key Notes !îþ›îû# þÐ îy¥zly!îû ¤‚‡Äyîû öëyˆæþ¡ !l”Åëû †þîûöì þ Adder ¤‚ë%_« ¡!?†þ î Åþl# x¤‚‡Ä ¡!?†þ öˆöìØþîû îÄî¥yîû †þîûy ¥ëûÐ ¤ô§ºöìëû ÷ þ!îû ¥ëûÐ xÄy’þyîû ˜%éŸé²Ì†þyîûÐ Half Adder Œ2!Øþ !îØþ öëyˆ ~¥z î Åþl#îû xy’þzØþþ›%Øþ þyêÇþ!”†þ ¥zlþ›%öìØþîû Gþ›îû †þöìîûŠ G Full Adder Œ3!Øþ !îØþ öëyˆ †þöìîûŠ !lèÅþîû †þöìîûÐ îy¥z l y!îû ¤‚‡Äyîû !îöì ë û y ˆæþ¡ !l”Å ë û †þîû ö ì þ ~öì þ ö†þyöìly öôöìôy!îû ~!¡öìôrØþ íyöì†þ lyÐ ¤yîØþÆÄyQîû îÄî¥* þ ¥ëûÐ AND, OR, NOT-ö†þ öî!¤†þ öˆØþ î¡y ¥ëûÐ ¤yîØþÆ Ä yQîû G ˜% ¥ z ²Ì†þyîû Ð Half G Full NAND G NOR ö†þ ¤îÅ?l#l îy Universal Subtractor. Gate î¡y ¥ëûÐ ~öì˜îû ¤y¥yöìëÄ ¤†þ¡ öî!¤†þ ôy!ÎØþöìæÏþ:yîû î Åþl#öì þ 2n ¤‚‡Ä†þ Input line öˆØþ ÷ þ!îû †þîûy ëyëûÐ öíöì†þ n ¤‚‡Ä†þ Control line-~îû ôy™Äöìô þíÄ Nand ¥¡ AND öˆöìØþîû !îþ›îû# þ G NOR ¥¡ ~†þ!Øþ xy’þzØþþ›%öìØþ ëyëûÐ OR gateéŸé~îû !îþ›îû# þ îy þ›!îûþ›)îû†þÐ !’þéŸéôy!ÎØþöìæÏþ:yîû î Åþl#öì þ ~†þ!Øþôye ¥zlþ›%Øþ XOR öˆöìØþîû xy’þzØþþ›%Øþ !îöì?y’þü ¤‚‡Ä†þ ‘1’ ¡y¥zöìlîû þíÄ n ¤‚‡Ä†þ Control line-~îû ¥zlþ›%öìØþîû ?lÄ ‘1’ ¥ëûÐ ôy™Äöìô 2n ¤‚‡Ä†þ xy’þzØþþ›%Øþ ¡y¥zöìlîû ö†þyöìly XNOR öˆöìØþîû †þyëÅþ›m*! þ XOR gateéŸé~îû 10 Class-10 my˜¢ ö×!” |†þ!Á›’þz Bengali | Chapter Øþyîû xÄy!²Õ Name öì†þ¢l ¡!?†þ öˆØþ ~î‚ †þ!Áºöìl¢ly¡ ¤y!†ÅþØäþ¤ ~†þ!Øþöì þ þ›y‘þyöìly ¥ëûÐ A B A·B !’þöì † þy’þyîû î Å þ l# îy¥z l y!îû þíÄöì † þ ¤ô % þ ¡ 0 0 1 A.B ö’þ!¤öìô¡ îy xlÄ ö†þyöìly þöìíÄ îû*þ›yhsý!îû þ †þöìîûÐ 0 1 0 ~löì†þy’þyîû î Åþl# ö’þ!¤öìô¡ îy xlÄ ö†þyöìly 1 0 0 þöìíÄîû ¤ô %þ¡ îy¥zly!îû þíÄ ÷ þ!îû †þöìîûÐ 1 1 1 A.B Unknown Facts \ A · B = A.B + AB AND gate ö†þ ‘All or Nothing’ öˆØþ î¡y A F ¥ëûÐ 2. B OR gate ö†þ ‘Any or All gates’ î¡y ¥ëûÐ NOT gate ö†þ ‘Inverter’ î¡y ¥ëûÐ [HS-22, HS-19] XOR Gate ö†þ ‘anti-coincidence’ öˆØþ îy ’þzþ›öìîûy_« ’þyëûy@ýÌyô!Øþöì þ FéŸé~îû ôyl †þ# ¥öìîÚ Inequality detector î¡y ¥ëûÐ aŠ AB bŠ AB XNOR gate ö†þ ‘Coincidence gate’ îy cŠ A+B dŠ A+B Equality detector î¡y ¥ëûÐ aŠ AB NAND gate-~îû ¤y¥yöìëÄ OR gate ÷ þ!îûöì þ A A.B A.B = A.B 3!Øþ NAND gate ²Ìöìëûy?l ¥ëûÐ B NOR gate-~îû ¤y¥yöìëÄ AND gate ÷ þ!îûöì þ 3. 8:1Ÿé~ Selection lineŸé~îû ¤‚‡Äy ¥¡éŸŸŸé 3!Øþ NOR gate ˜îû†þyîû ¥ëûÐ aŠ 2 bŠ 3 NAND gate-~îû îÄî¥yîû †þöìîû XOR gate ÷ þ!îûöì þ 4!Øþ NAND gate G NOR gate cŠ 4 dŠ 5 îÄî¥yîû †þöìîû XOR gate ÷ þ!îûöì þ 5!Øþ NOR bŠ 3 gate ²Ìöìëûy?l ¥ëûÐ 2 ¤‚‡Ä†þ ¥zlþ›%Øþ ¡y¥zöìlîû ?lÄ n ¤‚‡Ä†þ n Multiplexer ö†þ ‘Date selector’ G De- selection lineŸé~îû ²Ìöìëûy?l ¥ëûÐ Multiplexer ö†þ Data Distributor î¡y ¥ëûÐ \ 2n = 8 öë¤ôhßì !’þ!?Øþy¡ î Åþl#öì þ ¡!?†þ öˆØþ=!¡ ˜%!Øþ îy– 2n = 23 hßìöìîû !îlÄhßì íyöì†þ þyöì†þ !mhßìîû#ëû î Åþl# îy Two îy– n = 3 Level Circuit îöì¡Ð ~!Øþ ¤y™yîû” þ ˜%²Ì†þyîûÐ (i) 4. ~†þ!Øþ ¤y!†ÅþöìØþîû ò¤ôyhsýîûy¡ ÷î˜%Ä! þ†þ Switch’ ~îû AND-OR circuit G (ii) OR-AND circuitÐ ’þz˜y¥îû” ¥¡éŸŸŸé aŠ logical AND ¤½þyîÄ ²ÌÙÀyî!¡ bŠ logical NOT îà!î†þÒ!èþ!_†þ ²ÌöìÙÀy_îû 1 cŠ Logical OR dŠ ~öì˜îû ö†þyöìly!Øþ¥z lëû 1. 2-input !î!¢ÜT XNOR gate-~ ˜%!Øþ input A G cŠ Logical OR B ¥öì¡ þyöì˜îû xy’þzØþþ›%Øþ !†þ ¥öìîÚ [HS-22] ~†þy!™†þ ¥zö졆þ!ØþƆþÄy¡ ¤%¥z‹þ ö×!” ¤ôîyöìëû ë%_« aŠ AB bŠ A.B +A.B íy†þöì¡ þ‡l þyöì†þ AND ¤%¥z!‹þ‚ ¡!?†þ îöì¡Ð cŠ A.B + A.B dŠ A+B ~†þy!™†þ ¥zö졆þ!ØþƆþÄy¡ ¤%¥z‹þ ¤ôyhsýîûy¡ ¤ôîyöìëû bŠ A. B + A.B ë%_« íy†þöì¡ þyöì†þ OR ¤%¥z!‹þ‚ ¡!?†þ îöì¡Ð XNOR gate-~ Truth Table 11 Class-10 my˜¢ ö×!” |†þ!Á›’þz Bengali | Chapter Øþyîû xÄy!²Õ Name öì†þ¢l ¡!?†þ öˆØþ ~î‚ †þ!Áºöìl¢ly¡ ¤y!†ÅþØäþ¤ 5. NOR gate l#öì‹þîû ö†þylä!Øþîû Complement? cŠ AND dŠ XOR aŠ AND bŠ OR bŠ NAND cŠ NOT dŠ NAND NAND ¥¡ ¤îÅ?l#l öˆØþÐ þy¥z ~¥z öˆØþéŸé~îû bŠ OR ¤y¥yöìëÄ öëéŸéö†þyöìly Basic gate ÷ þ!îû †þîûy ëyëûÐ NOR ¥¡ NOT-OR xíÅyê ORéŸé~îû þ›!îûþ›)îû†þ îy inversion †þîûy ëyëû NOT gateŸé~îû ¤y¥yöìëÄÐ †þô!²ÕöìôrØþÐ xyîyîû NAND gateŸé~îû ¤y¥yöìëÄ NOT öˆØþ ÷ þ!îû †þîûy ëyëûÐ 6. Octal-to-Binary EncoderŸé~ xy’þzØþþ›%Øþ †þ þ bitéŸé~îû ¥ëûÚ 10. !löìÁ¬y_« ö†þylä Combination circuit!Øþ data aŠ 7 bŠ 8 selectorŸé~îû †þy? †þöìîûÚ aŠ Adder bŠ Encoder cŠ 3 dŠ 15 cŠ 3 cŠ Multiplexer dŠ Half-Subtractor EncoderŸé~îû 2n ¤‚‡Ä†þ ¥zlþ›%Øþ ¡y¥zöìlîû ?lÄ n cŠ Multiplexer ¤‚‡Ä†þ xy’þzØþþ›%Øþ ¡y¥zl íyöì†þÐ Octal-to-Binary ôy!ÎØþöì²Õ:yîû xöìl†þ=!¡ ¥zlþ›%Øþ ¡y¥zléŸé~îû ôöì™Ä EncoderŸé~ Input LineŸé~îû ¤‚‡Äy 8!ØþÐ ö†þyöìly ~†þ!Øþ öíöì†þ þíÄ !löìëû ~îû ~†þ!Øþôye \ xy’þzØþþ›%Øþ ¡y¥zöìlîû ¤‚‡Äy 3!ØþÐ xy’þzØþþ›%Øþ ¡y¥zöìl ö²Ìîû” †þöìîû îöì¡ ~öì†þ Data Selector îöì¡Ð xyîyîû ~îû !îþ›îû# þ þ›!îû!ßi! þ 23 = 8 ¤,!ÜT ¥ëû De-Multiplexer-~îû öÇþöìeÐ þy¥z De- 7. NAND gate îÄî¥yîû †þöìîû OR gate ÷ þ!îû †þîûöì þ Multiplexer ö†þ Data Distributor îöì¡Ð †þéŸé!Øþ NAND gateŸé~îû ²Ìöìëûy?lÚ [HS-2016, 2019] ¤‚!Çþ® ²ÌöìÙÀy_îû 1 aŠ 3 bŠ 4 cŠ 5 dŠ 6 1. XOR gateŸé~îû Truth table !Øþ ö¡öì‡yÐ aŠ 3 [HS-22] 1 A A A.B=A+B=A+B A B AÅB 0 0 0 B 3 0 1 1 B 1 0 1 2 1 1 0 8. Multiplexer ÷ þ!îû †þîûöì þ l#öì‹þîû ö†þylä öˆØþ!Øþ ²Ìöìëûy?l#ëû lëûÚ [HS-2016, 2018] 2. 4×1 MUXéŸé~îû block Diagram ÷ þ!îû †þöìîûyÐ aŠ AND bŠ OR [HS-22] cŠ NOT dŠ ¤î=!¡ ¤î=!¡ dŠ ôy!ÎØþöì²Õ:yîû ¥¡ ~†þôye †þ!Áºöìl¢ly¡ î Åþl# ëyîû I0 I1 4 × 1 MUX O öÇþöìe ! þl!Øþ Basic Logic gate xíÅyê– AND, I2 OR, NOT îÄî¥* þ ¥ëûÐ I3 9. l#öì‹þîû ö†þylä gate !Øþîû ¤y¥yöìëÄ inversion †þîûy ëyëûÚ [HS-2016] 3. Decoder Circuit-~îû †þy? †þ#Ú aŠ NAND bŠ OR îy¥zly!îû þíÄ öíöì†þ ¤ô %þ¡ ö’þ!¤öìô¡ îy xQy¡ 12 Class-10 my˜¢ ö×!” |†þ!Á›’þz Bengali | Chapter Øþyîû xÄy!²Õ Name öì†þ¢l ¡!?†þ öˆØþ ~î‚ †þ!Áºöìl¢ly¡ ¤y!†ÅþØäþ¤ þíÄ !l”Åëû †þîûyîû ?lÄ Decoder î Åþl# îÄî¥yîû AB = A.B + A.B †þîûy ¥ëûÐ A B 4. 1×4 De-MUX- ~îû Truth table !Øþ ö¡öì‡yÐ A.B [HS-22] A.B + A.B = AB Input Output A.B S0 S1 O0 O1 O2 O3 0 0 1 0 0 0 0 1 0 1 0 0 9. Decimal-to-Binary EncoderŸé~îû output 1 0 0 0 1 0 line-~îû ¤‚‡Äy †þ þÚ 1 1 0 0 0 1 Decimal-to-Binary EncoderéŸé~îû xy’þzØþþ›%Øþ 5. Half-Subtractor-~îû Truth table !Øþ ¡y¥zöìlîû ¤‚‡Äy ¥¡éŸŸŸé 4. ö¡öì‡yÐ [HS-20] 10. Decoder G Encoder éŸé~îû þ›yíņþÄ ö¡öì‡yÐ Decoder îy¥zly!îû þíÄöì†þ ¤ô %þ¡ xQy¡ îy Input Output ö’þ!¤öìô¡ þöìíÄ îû*þ›yhsý!îû þ †þöìîûÐ !†þév Encoder A B Sum Borrow ö’þ!¤öìô¡ îy xQy¡ ¥z þÄy!˜ þíÄöì†þ ¤ô %þ¡ 0 0 0 0 îy¥zly!îû þöìíÄ îû*þ›yhsý!îû þ †þöìîûÐ 0 1 1 1 DecoderéŸé~ ¤öìîÅyF‹þ 2n ¤‚‡Ä†þ xy’þzØþþ›%Øþ ¡y¥zöìlîû 1 0 1 0 ?lÄ n ¤‚‡Ä†þ ¥zlþ›%Øþ ¡y¥zl íyöì†þÐ EncoderéŸé~ 1 1 0 0 2n ¤‚‡Ä†þ ¥zlþ›%Øþ ¡y¥zöìlîû ?lÄ n ¤‚‡Ä†þ xy’þzØþþ›%Øþ ¡y¥zl íyöì†þÐ 6. ~†þ!Øþ 2×4 Decoder-~îû block Diagram xBþl †þöìîûyÐ [HS-19] ˜#‰Å’þz_îû™ôÅ# ²ÌöìÙÀy_îû 7 I0 O0 1. (a) Half-Adder CircuitéŸé~îû Sum ~î‚ 2×4 O1 O2 Carry-é~îû Logical Expression =!¡ derive Decoder I1 O3 †þöìîûy ~î‚ Logic diagram!Øþ xBþl †þöìîûyÐ (b) ~†þ!Øþ 2×4 Decoder Ÿé ~ îû Circuit 7. MUX G DEMUXéŸé~îû ôöì™Ä ~†þ!Øþ þ›yíņþÄ diagarm !Øþ xBþl †þöìîûyÐ ö¡öì‡yÐ [HS-18] [4+3][HS-22] MUX-~îû xöìl†þ=!¡ Input G ~†þ!Øþ Output (a) Half-Adder-~îû Sum G Carry-~îû Truth íyöì†þÐ DeMUX-~îû 1!Øþ Input G xöìl†þ=!¡ Table!Øþ ¥¡éŸŸŸé Output íyöì†þÐ Input Output MUXéŸéö†þ Data Selector î¡y ¥ëû G De- A B Sum Carry MUX ö†þ Data Distributer î¡y ¥ëûÐ 0 0 0 0 8. Besic logic gate îÄî¥yîû †þöìîû XOR gate ÷ þ!îû †þöìîûyÐ [HS-19] 13 Class-10 my˜¢ ö×!” |†þ!Á›’þz Bengali | Chapter Øþyîû xÄy!²Õ Name öì†þ¢l ¡!?†þ öˆØþ ~î‚ †þ!Áºöìl¢ly¡ ¤y!†ÅþØäþ¤ 0 1 1 0 I0 I1 1 0 1 0 I0 I1 1 1 0 1 I0 I1 Logical Expression : Sum = A.B + A.B = AÅB I0 I1 Carry = AB. Logic Diagram : A B I0 I1 AB(sum) I0 I1 AB(carry) 2. (a) Multi plexor ö†þ Data Selector îöì¡ ö†þlÚ (b) Encoder G DedcoderŸé~îû þ›yíņþÄ ö¡öì‡yÐ Half-Adder (c) ˜%!Øþ Half-Adder îÄî¥yîû †þöìîû ~†þ!Øþ Full Adder ˆ‘þll †þöìîûyÐ [2+2+3] [HS-20] (a) ôy!ÎØþöì²Õ:yîû xöìl†þ=!¡ ¥zlþ›%Øþ ¡y¥zöìlîû ôöì™Ä (b) ~†þ!Øþ 2 × 4 Decoder-~îû Logical ö†þyöìly ~†þ!Øþ öíöì†þ þíÄ !löìëû ~îû ~†þ!Øþôye Expression ¥¡éŸŸŸé xy’þzØþþ›%Øþ ¡y¥zöìl ö²Ìîû” †þöìîû îöì¡ ~öì†þ Data D0 = I0 I1 Selector îöì¡Ð xyîyîû ~îû !îþ›îû# þ þ›!îû!ßi! þ D1 = I0 I ¤,!ÜT ¥ëû De-Multiplexer-~îû öÇþöìeÐ þy¥z De- D2 = I0 I1 Multiplexer ö†þ Data Distributor îöì¡Ð D3 = I0 I1 (b) Decoder îy¥zly!îû þíÄöì†þ ¤ô %þ¡ xQy¡ îy ö’þ!¤öìô¡ þöìíÄ îû*þ›yhsý!îû þ †þöìîûÐ !†þév Encoder ö’þ!¤öìô¡ îy xQy¡ ¥z þÄy!˜ þíÄöì†þ ¤ô %þ¡ îy¥zly!îû þöìíÄ îû*þ›yhsý!îû þ †þöìîûÐ DecoderéŸé~ ¤öìîÅyF‹þ 2n ¤‚‡Ä†þ xy’þzØþþ›%Øþ ¡y¥zöìlîû ?lÄ n ¤‚‡Ä†þ ¥zlþ›%Øþ ¡y¥zl íyöì†þÐ EncoderéŸé~ 2n ¤‚‡Ä†þ ¥zlþ›%Øþ ¡y¥zöìlîû ?lÄ n ¤‚‡Ä†þ xy’þzØþþ›%Øþ ¡y¥zl íyöì†þÐ (c) ˜%!Øþ Half-Adder îÄî¥yîû †þöìîû ~†þ!Øþ Full- Addar ÷ þ!îû韟Ÿé Full Adder ~îû Sum-~îû î%¡#ëû îûy!¢ôy¡y = (AÅB)Å Cin Carry-~îû î%¡#ëû îûy!¢ôy¡y = Cin (AÅB)+AB 14 Class-10 my˜¢ ö×!” |†þ!Á›’þz Bengali | Chapter Øþyîû xÄy!²Õ Name öì†þ¢l ¡!?†þ öˆØþ ~î‚ †þ!Áºöìl¢ly¡ ¤y!†ÅþØäþ¤ A AB (AB).Cin B AB (AB).Cin (AB).Cin+AB Cin Half-Adder 1 Half-Adder 2 3. (a) Full Adder Circuit éŸé~îû Sum G Carry-~îû Logical expression =!¡ derive †þöìîûyÐ ~î‚ Logic diagram!Øþ xBþl †þöìîûyÐ (b) 4× 1 MUX-~îû Circuit diagram !Øþ xBþl †þöìîûyÐ (c) Multiplexer G De-Multiplexer-~îû ôöì™Ä ˜%!Øþ þ›yíņþÄ ö¡öì‡yÐ (a) Full Adder-~îû Truth Table : Input Output A B Cin Sum Carry 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Sum = A.B.Cin+A.B. Cin +A.B. Cin +A.B.Cin = A(B.Cin+B. Cin )+A(B.Cin+B.Cin) [Distributive Law] = A(BÅCin)+A(B · Cin) [XOR G XNOR gate ~îû î%!¡ëû xöìþ›Çþ†þ xl%ëyëû#] = A(BÅCin)+A( BÅCin ) = AÅ(BÅCin) = AÅBÅCin Carry = A.B.Cin + A.B.Cin + A.B. Cin +A.B.Cin = Cin(AÅB)+A.B( Cin +Cin) [Distributive Law] = Cin(AÅB)+A.B.1[Complement Law G XOR gate-~îû î%!¡ëû xöìþ›Çþ†þ xl%ëyëû#] = Cin(AÅB)+A.B Logic diagram-~îû ?lÄ ˜#‰Å ’þz_îû!èþ!_†þ ²ÌöìÙÀîû 2(c)~îû ’þz_îû ö˜öì‡yÐ 15 Class-10 my˜¢ ö×!” |†þ!Á›’þz Bengali | Chapter Øþyîû xÄy!²Õ Name öì†þ¢l ¡!?†þ öˆØþ ~î‚ †þ!Áºöìl¢ly¡ ¤y!†ÅþØäþ¤ (b) 4×1 MUXéŸé~îû î%¡#ëû îûy!¢ôy¡y ¥¡ !lÁ¬îû*þ›éŸŸŸé Y = S 0 S 1 I0+ S 0 S1 I1 + S0 S 1 I2 + S0 S1 I3 ~‡yöìl– S0 G S1 ¥¡ !¤ö졆þ¢yl ¡y¥zl I0, I1, I2 G I3 ¥¡ ¥zlþ›%Øþ ¡y¥zl S0 S1 S0 S1 I0 I0 S0 S1 I1 I1 Y S0 S1 I2 I2 S0 S1 I3 I3 4 × 1 Multiplexer (c) ¤‚!Çþ® ’þz_îû!èþ!_†þ ²ÌöìÙÀîû 7 l‚éŸé~îû ²ÌöìÙÀy_îû ö˜öì‡yÐ 4. (a) Decoder G De-Encoder-~îû ôöì™Ä þ›yíņþÄ ö¡öì‡yÐ (b) Decimal to Binary Encoder-~îû Truth Table!Øþ ö¡öì‡y G Circuit diagram xBþl †þöìîûyÐ [2+(2+3)][HS-2018] (a) ¤‚!Çþ® ’þz_îû!èþ!_†þ ²ÌöìÙÀîû 10 l‚ ²ÌöìÙÀy_îû ö˜öì‡yÐ (b) Decimal to Binary Encoder-~îû Truth Table Input Output I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 O3 O2 O1 O0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 16 Class-10 my˜¢ ö×!” |†þ!Á›’þz Bengali | Chapter Øþyîû xÄy!²Õ Name öì†þ¢l ¡!?†þ öˆØþ ~î‚ †þ!Áºöìl¢ly¡ ¤y!†ÅþØäþ¤ î%¡#ëû îûy!¢ôy¡y 韟Ÿé O0 = I1 + I3 + I5 + I7 + I9 O1 = I2 + I3 + I6 + I7 O2 = I4 + I5 + I6 + I7 O3 = I8 + I9 ²Ìöì þĆþ!Øþ xy’þzØþþ›%Øþ xíÅyê O0,O1, O2, O3-~¥z xy’þzØþþ›%Øþ=!¡îû î%¡#ëû îûy!¢ôy¡y ÷ þ!îûîû öÇþöìe ¤‚!ÙÕÜT Column- =!¡îû öë ôyl=!¡öì þ 1 ¥öìëûöìSé ö¤¥z RowéŸé~îû 1 ôylë%_« ¥zlþ›%Øþ=!¡öì†þ OR myîûy ë%_« †þîûöì¡ ²Ì! þ!Øþ xy’þzØþþ›%öìØþîûþ› î%¡#ëû îûy!¢ôy¡y þ›yGëûy ëyëûÐ ~löì†þy’þyîû î Åþl#öì þ n ¤‚‡Ä†þ xy’þzØþþ›%Øþ ¡y¥zöìlîû ?lÄ ¤öìîÅyF‹þ 2n ¤‚‡Ä†þ ¥zlþ›%Øþ ¡y¥zl íy†þöì þ þ›yöìîûÐ !†þév ö’þ!¤öìô¡ Ø%þ îy¥zly!îû ~löì†þy’þyöìîû– ö’þ!¤öìô¡ ¤‚‡Äy þ›m*! þöì þ ߺ þsf ¤‚‡Äy 0-9 xíÅyê 10!Øþ– þy¥z ¥zlþ›%Øþ ¡y¥zöìlîû ¤‚‡Äy 10 ~î‚ ¤öìîÅyF‹þ ¤‚‡Äy 9éŸéö†þ îy¥zly!îûöì þ ²Ì†þy¢ †þîûöì þ 4-!Øþ !îöìØþîû ²Ìöìëûy?l ¥ëûÐ þy¥z xy’þzØþþ›%Øþ ¡y¥zöìlîû ¤‚‡Äy 4!ØþÐ I9 I8 I 7 I6 I5 I4 I3 I2 I1 I0 O0 O1 O2 O3 ~löì†þy’þyîû ¥¡ ~ôl ~†þ!Øþ ¤‚ë%_« ¡!?†þ î Åþl# öë‡yöìl ö†þî¡ôye OR-gate îÄî¥* þ ¥ëûÐ xlÄ ö†þyöìly öˆØþ îÄî¥* þ ¥ëû lyÐ !¢Çþ†þô[þ¡#îû þ›îûyô¢Å ~¥z x™Äyëû öíöì†þ 15 lÁºöìîûîû ²ÌÙÀ íy†þöìîÐ þyîû ôöì™Ä 5 lÁºöìîûîû MCQ, 3 lÁºöìîûîû SAQ G 7 lÁºöìîûîû Descriptive ²ÌÙÀ íy†þöìîÐ MCQ G SAQéŸé~îû ?lÄ ¤yîû¤‚öìÇþþ› G x?yly þíÄ ‡%„!Øþöìëû þ›’þüöì þ ¥öìîÐ ~ Séy’þüyG ~¥z x™Äyöìëûîû x!™†þy‚¢ ²ÌÙÀ¥z öîy™ô)¡†þ îy ²Ìöìëûyˆô)¡†þÐ þy¥z !î£ìëûîéÝîû ™yîû”yîû þ›!îûÜñyîû íy†þöì þ ¥öìîÐ þy¥z ²Ì˜_ !î£ìëûîéÝîû ²Ì! þ!Øþ ØþÆ$í öØþ!î¡ ’þyëûy@ýÌyô ôl !˜öìëû x™Äëûl †þîûöì þ ¥öìîÐ ¤öìîÅyþ›!îû ~¥z x™Äyëû èþyöì¡yèþyöìî þ›’þüöì þ ¥öì¡ ~†þy˜¢ ö×!”îû î%¡#ëû î#?ˆ!” þ èþyöì¡yèþyöìî þ›’þüöì þ G î%Vþöì þ ¥öìîÐ 17