Lec22-4471029-MIPS Pipelining (Contd) PDF

Pipelining : Data and Control Dependence Handling 471029: Introduction to Computer Architecture 22th Lecture Disclaimer: Slides are mainly based on COD 5th textbook and also developed in part by Profs. Dohyung Kim @ KNU and Computer architecture course @ KAIST and SKKU...

Pipelining : Data and Control Dependence Handling 471029: Introduction to Computer Architecture 22th Lecture Disclaimer: Slides are mainly based on COD 5th textbook and also developed in part by Profs. Dohyung Kim @ KNU and Computer architecture course @ KAIST and SKKU 1 Data Forwarding/Bypassing  Problem: A consumer (dependent) instruction has to wait in decode stage until the producer instruction writes its value in the register file  Goal: We do not want to stall the pipeline unnecessarily  Observation: The data value needed by the comsumer instruction can be supplied directly from a later stage in the pipeline (instead of only from the register file)  Idea: Add additional dependence check logic and data forwarding paths (buses) to supply the producer’s value to the consumer right after the value is available  Benefit: Consumer can move in the pipeline until the point the value can be supplied  less stalling 2 A Special Case of Data Dependence  Control dependence  Data dependence on the Instruction Pointer / Program Counter 3 Control Dependence  Question: What should fetch PC be in the next cycle?  Answer: The address of the next instruction  All instructions are control dependent on previous ones. Why?  If the fetched instruction is a non-control-flow instruction:  Next Fetch PC is the address of the next-sequential instruction  Easy to determine if we know the size of the fetched instruction  If the instruction that is fetched is a control-flow instruction:  How do we determine the next Fetch PC?  In fact, how do we know whether or not the fetched instruction is a control-flow instruction? 4 Pipelining : Data Dependence Handling (More Depth & Implementation) 471029: Introduction to Computer Architecture 22th Lecture Disclaimer: Slides are mainly based on COD 5th textbook and also developed in part by Profs. Dohyung Kim @ KNU and Computer architecture course @ KAIST and SKKU 5 Remember: Data Dependence Types Flow dependence r3  r1 op r2 Read-after-Write r5  r3 op r4 (RAW) Anti dependence r3  r1 op r2 Write-after-Read r1  r4 op r5 (WAR) Output-dependence r3  r1 op r2 Write-after-Write r5  r1 op r4 (WAW) r3  r6 op r7 6 RAW Dependence Handling  Which one of the following flow dependences lead to conflicts in the 5-stage pipeline? addi ra r- - IF ID EX MEM WB addi r- ra - IF ID EX MEM WB addi r- ra - IF ID EX MEM addi r- ra - IF ID EX addi r- ra - IF ?ID addi r- ra - IF 7 Register Data Dependence Analysis R/I-Type LW SW Br J Jr IF ID read RF read RF read RF read RF read RF EX MEM WB write RF write RF  For a given pipeline, when is there a potential conflict between two data dependent instructions?  dependency type: RAW, WAR, WAW?  instruction types involved?  distance between the two instructions? 8 Safe and Unsafe Movement of Pipeline stage X j:_rk Reg Read j:rk_ Reg Write j:rk_ Reg Write (young) iFj iAj iOj stage Y i:rk_ Reg Write i:_rk Reg Read i:rk_ Reg Write (old) RAW Dependence WAR Dependence WAW Dependence dist(i,j)  dist(X,Y)  Unsafe ?? to keep j moving dist(i,j) > dist(X,Y)  Safe ?? 9 RAW Dependence Analysis Example R/I-Type LW SW Br J Jr IF ID read RF read RF read RF read RF read RF EX MEM WB write RF write RF  Instructions IA and IB (where IA comes before IB) have RAW dependence iff  IB (R/I, LW, SW, Br or JR) reads a register written by IA (R/I or LW)  dist(IA, IB)  dist(ID, WB) = 3 10  Pipeline Stall: Resolving Data Dependence t0 t1 t2 t3 t4 t5 Insth IF ID ALU MEM WB Insti i IF ID ALU MEM WB Instj j IF ID ALU ID MEM ALU ID ID WB MEM ALU ALU WB MEM Instk IF ID IF ALU ID IF MEM ALU ID IF WB MEM ALU ID Instl IF ID IF ALU ID IF MEM ALU ID IF IF ID IF ALU ID IF i: rx  _ j: _  rx bubble dist(i,j)=1 Stall: make the dependent instruction IF IF ID wait j: _  rx bubble dist(i,j)=2 IF until its source data value is available j: _  rx bubble dist(i,j)=3 1. stop all up-stream stages j: _  rx dist(i,j)=4 2. drain all down-stream 11 stages 11 Pipeline Stall 12 How to Implement StallingPCSrc ID/EX 0 M u WB x EX/MEM 1 Control M WB MEM/WB EX M WB IF/ID Add Add 4 Add result RegWrite Branch Shift left 2 MemWrite ALUSrc Read MemtoReg Instruction PC Address register 1 Read data 1 Read register 2 Zero Instruction Registers Read ALU ALU memory Write 0 Read data 2 result Address 1 register M data u Data M Write x memory u data x 1 0 Write data Instruction 16 32 6 [15– 0] Sign ALU MemRead extend control Instruction [20– 16] 0 ALUOp M Instruction u [15– 11] x 1 Stall RegDst   disable PC and IR latching; ensure stalled instruction stays in its stage  Insert “invalid” instructions/nops into the stage following the stalled one (called “bubbles”) 13 When to Stall?  Instructions IA and IB (where IA comes before IB) have RAW dependence iff  IB (R/I, LW, SW, Br or JR) reads a register written by IA (R/I or LW)  dist(IA, IB)  dist(ID, WB) = 3  Must stall the ID stage when IB in ID stage wants to read a register to be written by IA in EX, MEM or WB stage 14 Stall Condition Evaluation Logic  Helper functions  rs(I) returns the rs field of I  use_rs(I) returns true if I requires RF[rs] and rs!=r0  Stall when  (rs(IRID)==destEX) && use_rs(IRID) && RegWriteEX or  (rs(IRID)==destMEM) && use_rs(IRID) && RegWriteMEM or  (rs(IRID)==destWB) && use_rs(IRID) && RegWriteWB or  (rt(IRID)==destEX) && use_rt(IRID) && RegWriteEX or  (rt(IRID)==destMEM) && use_rt(IRID) && RegWriteMEM or  (rt(IRID)==destWB) && use_rt(IRID) && RegWriteWB  It is crucial that the EX, MEM and WB stages continue to advance normally during stall cycles 15 Impact of Stall on Performance  Each stall cycle corresponds to one lost cycle in which no instruction can be completed  For a program with N instructions and S stall cycles, Average CPI=(N+S)/N  S depends on  frequency of RAW dependences  exact distance between the dependent instructions Suppose I1,I2 and I3 all depend on I0, once I1’s hazard is resolved, I2 and I3 must be okay too! 16 Sample Assembly  for (j=i-1; j>=0 && v[j] > v[j+1]; j-=1) { …… } addi $s1, $s0, -1 3 stalls for2tst: slti $t0, $s1, 0 3 stalls bne $t0, $zero, exit2 sll $t1, $s1, 2 3 stalls add $t2, $a0, $t1 3 stalls lw $t3, 0($t2) lw $t4, 4($t2) 3 stalls slt $t0, $t4, $t3 3 stalls beq $t0, $zero, exit2......... addi $s1, $s1, -1 j for2tst exit2: 17