Verilog Basics Quiz
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Questions and Answers

Which of the following is NOT a type of concurrent block in Verilog?

  • initial
  • assign
  • case (correct)
  • always

    • In Verilog, the 'X' state represents a high impedance value.

    False (B)

    What keyword is used to define the beginning of a module in Verilog?

    module

    The Verilog statement $display("Hello World!"); is commonly found inside an _______ block.

    <p>initial</p> Signup and view all the answers

    Match the Verilog signal values with their meanings:

    <p>0 = Logic low or False 1 = Logic high or True X = Unknown Z = High impedance</p> Signup and view all the answers

    What does a 'Z' value represent in Verilog?

    <p>High impedance (A)</p> Signup and view all the answers

    Modules in Verilog do not communicate with the outside world.

    <p>False (B)</p> Signup and view all the answers

    What keyword is used to denote the end of the module in Verilog?

    <p>endmodule</p> Signup and view all the answers

    In the module port declaration module dff (q, qn, d, clk);, 'd' and 'clk' are declared as _____.

    <p>input</p> Signup and view all the answers

    What are the basic building blocks in Verilog?

    <p>Modules (D)</p> Signup and view all the answers

    Flashcards

    Module

    The basic building block for Verilog designs, defining logic.

    Concurrent Blocks

    Three types: always, initial, and assign, executed simultaneously.

    Always Block

    A block that runs continuously in response to events.

    Initial Block

    Runs once at the start of simulation for setup.

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    Assign Block

    Used for continuous assignments in Verilog.

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    Signal Values

    Represent logical states: 0, 1, X, Z with specific meanings.

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    Hi-Z State

    High impedance state, indicating a disconnected signal.

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    Module Ports

    Communication pathways for modules, similar to hardware pins.

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    Reset Signal

    A signal used to set elements to a known state during initialization.

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    posedge clk

    Indicates an event triggered at the positive edge of a clock signal.

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    Study Notes

    Agenda: Day Two

    • Unit 1 covers Modules and Blocks.
    • Unit 2 covers Numbers, Data types and Operators.
    • Unit 3 covers Control Constructs.
    • Labs are assigned for each unit.

    Verilog Overview

    • Basic unit is a module.
    • Three types of concurrent blocks.
      • always
      • initial
      • assign
    • Supports clocks, time progression, registers, and wires.
    • Supports 4 states: 0, 1, x, z.

    Signal Values and Resolution

    • '0': Zero, Low, False, Logic low, Ground, VSS, Negative Assertion
    • '1': One, High, True, Logic High, Power, VDD, VCC, Positive Assertion
    • 'X': Unknown: Occurs at Logical Conflict which cannot be resolved.
    • 'Z': Hi-Z: High Impedance, Tristated, Disabled Driver.

    Module

    • Modules are basic building blocks.
    • Logic is placed inside modules.
    • Module definitions start with the keyword module.
    • Modules end with the keyword endmodule.
    • Example: module hello; initial $display("Hello World!"); endmodule

    Module Ports

    • Modules communicate with the outside world through ports.
    • Module ports are the same as pins in hardware.
    • Example: module dff (q, qn, d, clk); input d, clk; output q, qn; reg q, qn; always @(posedge clk) begin q <= d; qn <= ~d; end endmodule

    Port Types

    • Inputs are always used as wires.
    • Outputs are by default wires but can also be used as registers.
    • Inouts are a combination of input and output.

    Module Instances

    • Modules can be instantiated within other modules to create a hierarchy.
    • Example: module top; reg data_in, clock; wire data_out, data_outb; dff D_flipflop(data_out, data_outb, data_in, clock); endmodule

    Concurrent Blocks

    • Two types of procedural blocks, initial and always.
    • initial executes once at time zero.
    • always blocks are active throughout the simulation.
    • All statements within a block are executed sequentially.
    • Continuous assignments (assign) are continuously driven.

    Concurrent Execution

    • All procedural blocks execute concurrently, modelling concurrency found in hardware.
    • All procedural blocks are active at time zero, waiting to be executed upon conditions.

    Initial Block

    • Syntax: initial begin ... end.
    • Example: module test; reg a, b; wire out; 2inputAND (out, a, b); initial begin a = 0; b = 0; end endmodule

    Always Block

    • Syntax: always @(event) begin ... end.
    • Example: module ANDgate; wire a, b; reg qout; always @(a or b) begin qout = a & b; end endmodule

    Sensitivity List

    • The sensitivity list controls when statement execution begins within an always block.
    • Verilog-1995 uses the keyword or to separate signals.
    • Verilog-2001 uses commas to separate signals in a sensitivity list, which is more intuitive.
    • List all input signals in an always block for accurate simulations and synthesis.
    • @* token adds all nets and/or variables read in the always block to sensitivity list.
    • Example: always @(posedge Clk or negedge Reset)

    Lab 1-2: Concurrency of Procedural Blocks

    • Specification includes RESET, LOAD, ADD and CLK operations

    Continuous assignment

    • Continuous assignments are blocks that run concurrently.
    • Syntax: assign [net_name] = [expression];
    • Can be explicit (e.g., assign a = b + c;) or implicit (e.g., wire inv = ~in;)

    Lab 1-3: Continuous assignment

    • Objective: Write a 2:1 mux using the assign statement.
    • Specification includes input signals (in1, in2, sel) and output signal (out).

    Numbers in Verilog

    • Number of bits and radix (e.g., binary, hexadecimal) are optional.
    • Default bits = 32, radix = decimal.
    • Letters for radix: b (binary), d (decimal), o (octal), h (hexadecimal). Case insensitive.
    • Examples: 8'b10100101 (8-bit binary), 16'habcd(16-bit hex).

    Data Types in Verilog

    • Wire: Connects modules/primitives, cannot retain a value.
    • Register: Can hold a value, commonly used in sequential logic.
    • Integers: 32-bit wide, signed.

    Data Types in Verilog: Wire

    • Wires connect modules or primitives in a design.
    • Wires do not hold values.
    • Example: wire a;, wire x, y, z;, wire [7:0] b, c, d; are valid wire declarations.

    Data Types in Verilog: Register

    • Registers can hold values.
    • They are often used to represent state information in sequential logic circuits.
    • Examples: reg a;, reg x, y;, reg [4:0] b;.

    Data Types in Verilog: Integer

    • Integers are 32 bit wide, signed.
    • Often not recommended for synthesis.
    • Example: integer j, k, l;

    Control Constructs in Verilog

    • if-else
    • case
    • while
    • for

    Control constructs (if-else)

    • if (condition) procedural_block1 else procedural_block2
    • Condition can be an expression or a value.
    • No then or endif in Verilog.

    Lab 2-1: If-else

    • Objective: Create an if-else block to compare 8-bit inputs, a and b.
    • Output includes g (greater than), l (less than), and e (equal to).

    Control constructs (case)

    • case (condition) value1: procedural_block1; value2: procedural_block2; ... endcase.
    • Default statement is executed if no match case values.

    Lab 2-2: Case

    • Objective: Create an 8-bit counter using a case construct.
    • Inputs include c (2-bit control), din (8-bit data input).
    • Output is dout (8-bit data output).

    Control constructs (while loop)

    • while (condition) procedural_block1.
    • Executed as long as condition TRUE.
    • Not synthesizable for some conditions.

    Lab 2-3: While Loop

    • Objective: Use while loops to divides a 16-bit input by 3 in a circuit.

    Control constructs (for loop)

    • for (expr1; expr2; expr3) procedural_block1.
    • expr1: Initialization.
    • expr2: Condition.
    • expr3: Increment/Decrement.

    Lab 2-4: For Loop

    • Objective: Detect the number of times a given bit pattern is found within a 32-bit input.

    Operators in Verilog

    • Includes shift, logical, conditional, negation, relational, replication, concatenation, equality, unary, reduction, and bitwise operators, explained further in the notes.

    Lab 2-5: Design 2-bit Shifter

    • Objective: Design an 8-bit shifter with three inputs: CLK, SHL (Shift Left), SHR (Shift Right), Load.

    Conditional operator (? :)

    • Also known as the ternary operator.
    • Syntax: (conditional_expression) ? (true_expression) : (false_expression).

    Lab 2-6:

    • Objective: Copy/explain a Verilog module that uses an assignment with a condition.

    Lab 2-7: Ternary Operator

    • Objective: Build an 8-to-1 multiplexer (MUX) module using the ternary operator.

    Negation, Relational, Replication, and Concatenation Operators

    • Detailed explanations and examples.

    Other Operators

    • Detailed explanation of logical equality (==), case equality (===), case inequality (!==) operators, and examples.

    Review

    • Question about scalar and vector values
    • Question about ~ and !.
    • Question about & and &&.

    Operator Precedence

    • Table outlining the precedence levels of various Verilog operators.

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    Description

    Test your knowledge of Verilog with this quiz focusing on fundamental concepts such as concurrent blocks, signal states, and module definitions. Perfect for students learning hardware description languages looking to reinforce their understanding of Verilog syntax and structure.

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