csc25-lecture-notes-173-177_part3.pdf

Buses Figure 9.6: System, i.e., memory and I/O, bus simplified view. Definitions A bus is a shared communication link to carry address, data, and control signals. It is basica...

Buses Figure 9.6: System, i.e., memory and I/O, bus simplified view. Definitions A bus is a shared communication link to carry address, data, and control signals. It is basically a set of wires used to connect multiple subsystems. A bus is a basic tool for putting together large and complex systems. Fig. 9.7 shows a memory bus and an I/O bus. Figure 9.7: A simple example of a bus connecting memory and I/O devices to the processor. The address bus (or address lines) identifies the source of a data flow. The address bus bandwidth gives the maximum addressing capacity of a device. The data bus (or data lines) carries data or instructions, i.e., it does not matter on that level of abstraction. This bus is typically bidirectional, and its bandwidth is determinant to performance. The control bus (or control lines) is responsible for handling control signals such as read/write, interruptions, and also the bus clock. Pros & Cons A considerable advantage of buses is related to its versatility. On it, new devices can be easily integrated to the system, and peripherals can be moved around different computers with the same bus standard. Another point in favor of buses is the low cost they have. A bus is basically a single set of wires shared in different ways, following different standards according to the requirements of an application (Fig. 9.8). However, when it comes to communication, the bus becomes a bottleneck in the system. The bus bandwidth can limit the maximum I/O throughput. Moreover, the maximum bus speed is largely limited by the bus length and number of devices on the bus. Besides, a bus needs to support a range of devices with widely differences in latencies and data transfer rates. 167 9 Storage and I/O Systems Figure 9.8: A bus: single set of wires connecting different devices together. Bus Design Overview Both bus speed and bandwidth are greatly impacted by four main points: 1. bus width; 2. bus clocking scheme; 3. operation; and 4. arbitration method. Bus Width Generally, the number of address lines determines the size of the addressable memory. The greater the number of lines, more wires and larger connectors will be necessary. And, in this case, the hardware becomes more expensive. Some examples of processors are the 8088 with 20 address lines, and the 80286 with four more lines, followed by the 80386 with 8 lines in addition. The trend to increase the bus width to increase bus capacity creates physical connection problems. Thus, designers often make multiplexing of data and addresses in different phases/time to reduce the number of lines. But this also reduces the performance of the bus. Bus Clocking Scheme Regarding the clocking scheme, buses can be either synchronous or asynchronous. The synchronous bus includes a clock in the control lines. This is based on a fixed protocol for communication, with respect to the clock. An advantage is that it involves very little logic and can run fast. A disadvantage is that all devices on the bus must run at the same clock rate. Finally, to avoid clock skew, buses cannot be long if they are fast. The other option is the asynchronous bus which is not clocked. It can accommodate a wide devices’ range and can be lengthened without caring about the clock skew issue. However, an asynchronous bus requires a handshake protocol. Operation Buses often consider a master device in control of a couple of slave devices. Fig. 9.9 illustrates this concept showing a unidirectional control bus (from master to slave), and a bidirectional data bus between them. There is a two-part bus transaction. One is related to the request, where the master issues a command and an address to the slave. And the other is the action, comprising the actual command execution, e.g., transferring the data. The master starts the bus transaction by issuing the requests to the slave. Then, the slave, responds to the master by sending or receiving data, accordingly. 168  Bus Design Figure 9.9: A simple example of a master and slave bus scheme. Obtaining Access to the Bus How is the bus reserved by a device that wants to use it? The chaos is avoided by using a master-slave scheme. In this case, only the bus master controls the access to the bus. It starts and handles all bus requests. The slave just responds to the read or write requests. In the simplest system, the processor is the only bus master. All bus requests must be controlled by the processor. But this is a big drawback, i.e., processor is involved in everything. In this aspect, it is possible to use an arbitration method to minimize the negative impacts in the system. Arbitration Method In the arbitration, it is possible to accommodate multiple bus masters in a same bus. However, with multiple bus masters it is needed to define means of assuring that only one device will be selected as master at a time. This given method must consider the priority among devices, and the fairness, i.e., even the lowest priority device must operate. Next, four possible arbitration classes are enumerated. 1. a distributed arbitration by self-selection, i.e., each device that waits for the bus places its own code, i.e., indicating its identity; 2. a distributed arbitration by collision detection, e.g., Ethernet; 3. an authorization given in sequence, e.g., daisy chain; and 4. an authorization given in a central manner, e.g., centralized arbitration. Daisy Chain The daisy chain scheme is considered simple, but cannot assure fairness. In this case, a low-priority device may be locked out forever and never get access to the bus. The use of daisy chain grant signal also impacts bus speed. Here, considering the devices are serialized (connected sequentially), the propagation delay tends to increase as it goes farther from the bus arbiter. Fig. 9.10 illustrates this concept. Centralized Arbitration with a Bus Arbiter The centralized arbitration with a bus arbiter considers that the arbiter will handle all the requests and give access to the devices according to their priorities. This concept is illustrated in Fig. 9.11. 169 9 Storage and I/O Systems Figure 9.10: The bus arbiter sends the grant signal to the highest priority device. When that device finishes its computation, it then sends the grant signal to the next priority level device following the sequence. This goes until the lowest priority device is served and has access to the request and release signals. A possible problem is when a device fails and never sends the grant signal back to the chain. Figure 9.11: The bus arbiter receives all devices’ requests (ReqA, ReqB, and ReqC) to give the grant signals (GrantA, GrantB, and GrantC) to them following a fixed priority-based policy. The signal/timing diagram (in the bottom) depicts the internal operation of the arbiter. There, it shows that the signal ReqA is received together with ReqB. As the first has the highest priority, the signal GrantA is given from the arbiter so that DeviceA is served. When the signal ReqA becomes inactive (meaning the device no longer needs the bus), GrantA is removed and GrantB is given. Examples of Common Buses Some examples of common buses very well-known and used in the consumer and aeronautical industries are mentioned next. Peripheral Component Interconnect - PCI Express (PCI-e) The PCI-e was created by Intell, Dell, HP, and IBM. It connects HDD, SSD, Ethernet, graphics, and other cards in personal computers. The PCI-e is based on point-to-point topology, considering separate serial links connecting all devices. PCI-e replaces other standards, e.g., Accelerated Graphics Port - AGP, PCI, and PCI-eXtended. InfiniBand - IB The InfiniBand was originated by Compaq, Dell, Hewlett-Packard, IBM, Intel, Microsoft, and Sun. It is typically used in clusters and racks. InfiniBand has a very high throughput and very low latency. 170  Bus Design MIL-STD-1553 This avionic data bus is mainly used with military avionics, and also in spacecraft, as a dual technology. The bus controller handles multiple remote terminals connected with redundant links. ARINC 429 ARINC stands for Aeronautical Radio INC. The ARINC 429 is the predominant avionics data bus used on most commercial aircraft. There, a pair of wires accommodates one transmitter and up to 20 receivers. Avionics Full-Duplex Switched Ethernet - AFDX The AFDX is an implementation of deterministic Ethernet, defined by ARINC to address real-time issues. 171