Digital Systems TCE1111 Counters PDF

DIGITAL SYSTEMS TCE1111 Asynchronous and Synchronous Counters 1 DIGITAL SYSTEMS TCE1111 Counters * Counters are important digital electronic circuits. * They are Sequential logic circuits because timing...

DIGITAL SYSTEMS TCE1111 Asynchronous and Synchronous Counters 1 DIGITAL SYSTEMS TCE1111 Counters * Counters are important digital electronic circuits. * They are Sequential logic circuits because timing is obviously important and they need a memory characteristic. * Digital counters have the following important characteristics, 1. Maximum number of count 2. Up-Down Count 3. Asynchronous or Synchronous Operation 4. Free-Running or Self-Stopping 2 DIGITAL SYSTEMS TCE1111 Asynchronous/Ripple Counter Asynchronous counter are commonly referred to as ripple counter because the effect of the input clock pulse is first “felt” by first flip-flop (FF0). Cannot get to the second flip-flop (FF1) immediately because of the propagation delay through FF0. So the effect of an input clock pulse “ripples” through the counter, taking some time, due to propagation delays, to reach the last flip-flop. Only the first FF receive clock pulse from the source ( clock genarator), others FFs receive clock pulse from either Q or Q’ 3 of prior FF DIGITAL SYSTEMS TCE1111 Asynchronous/Ripple Counter Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter. 4 DIGITAL SYSTEMS TCE1111 Asynchronous/Ripple Counter Three-bit asynchronous binary counter and its timing diagram for one cycle. Clk Q2 Q1 Q0 pulse 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 0 0 0 (REPEAT ) RIPPLE COUNTER UP – PGT AND ALL NON FIRST CLK RECEIVE CLK PLUSE FROM Q’ 5 DIGITAL SYSTEMS TCE1111 Asynchronous/Ripple Counter Four-bit asynchronous binary counter and its timing diagram. CLK Q3 Q2 Q1 Q0 PLUSE 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 10 1 0 1 0 11 1 0 1 1 12 1 1 0 0 13 1 1 0 1 14 1 1 1 0 15 1 1 1 1 16 0 0 0 0 REPEAT RIPPLE COUNTER UP – NGT AND ALL NON FIRST CLK 6 RECEIVE CLK PLUSE FROM Q DIGITAL SYSTEMS TCE1111 Asynchronous Decade Counter The Modulus of a counter is the number of unique states that the counter will sequence through. Counter can also be designed to have a number of states in their sequence that is less than the maximum of 2n. Counters with the states in their sequence are called decade counters. To obtain a truncated sequence, it is necessary to force the counter to recycle before going through all of its possible states. One way to make the counter recycle after the count of nine (1001) is to decode count ten (1010) with a NAND gate and connect the output of the NAND gate to the clear (CLR) inputs of the flip-flops. The inputs the NAND gate are from the Q output from FF1 and FF3 ( from 1010 -- FF3FF2FF1FF0) 7 DIGITAL SYSTEMS TCE1111 Asynchronous Decade Counter An asynchronously clocked decade counter with asynchronous recycling. CLK Q3 Q2 Q1 Q0 PLUSE 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 10 0 0 0 0 GLITCH 11 0 0 0 1 12 0 0 1 0 13 0 0 1 1 14 0 1 0 0 15 0 1 0 1 16 0 1 1 0 MOD 10 RIPPLE UP COUNTER – NGT AND ALL NON FIRST CLK RECEIVE CLK PLUSE FROM Q 8 MOD 10 AS RESET / CLITCH AT 1010. The inputs the NAND gate are from the Q output from FF1 and FF3 ( from 1010 -- FF3FF2FF1FF0) DIGITAL SYSTEMS TCE1111 Synchronous binary Counter The term Synchronous refers to events that have a fixed time relationship with each other AND receive cllock pulse from a common source 2-bit synchronous binary counter. 9 DIGITAL SYSTEMS TCE1111 Synchronous binary Counter A 3-bit synchronous binary counter. Clk Q2 Q1 Q0 pulse 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 0 0 0 (REPEAT ) 10 DIGITAL SYSTEMS TCE1111 Synchronous binary Counter CLK Q3 Q2 Q1 Q0 PLUSE 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 A 4-bit 9 1 0 0 1 synchronous 10 1 0 1 0 binary counter 11 1 0 1 1 and timing 12 1 1 0 0 diagram. Points where the AND 13 1 1 0 1 gate outputs are 14 1 1 1 0 HIGH are 15 1 1 1 1 indicated by the 16 0 0 0 0 shaded areas. REPEAT 11 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design Several methods are available that follow arbitrary sequence. Here we will learn one common method using JK flip-Flops. In synchronous counters all the FF’s are clocked at the same time. J-K Excitation Table Before begin the designing we must know the operation of the J-K FF, let us analysis Truth table for 74LS76 IC (JK flip- flop) and its excitation table. 12 DIGITAL SYSTEMS TCE1111 Truth table for 74LS76 IC (JK flip-flop) PRESET CLEAR J K CLK Qt Qt’ 0 0 0 0 x 1 1 0 1 x 1 1 1 0 x 1 1 1 1 x 1 1 0 1 0 0 x 1 0 0 1 x 1 0 1 0 x 1 0 1 1 x 1 0 1 0 0 0 x 0 1 0 1 x 0 1 1 0 x 0 1 1 1 x 0 1 1 1 0 0 ↓ Q0 Q0 ’ 0 1 ↓ 0 1 1 0 ↓ 1 0 13 1 1 ↓ TOGGLE TOGGLE DIGITAL SYSTEMS TCE1111 JK FF Excitation Table: PRESENT NEXT J K 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0 14 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design J-K Excitation Table TRANSITION PRESENT NEXT AT OUTPUT STATE STATE J K Q(N) Q(N+1) 0 0 0 0 0 X 0 1 0 1 1 X 1 0 1 0 X 1 1 1 1 1 X 0 0 0 TRANSITION; FF’s Present status is 0 and it should remain in 0 when a clock pulse is applied. That can be either J=K=0 status or J=0,K=1. That mean J=0 and K=0 or 1 That’s J=0 and K=X(don’t care) 15 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design 0 1 TRANSITION: The present state is 0 and it has to change to 1. This can happen either J=1 and K=0 or J=K=1. That mean always J=1 and K=0 or1 J=1 and K=X( don’t care) 1 0 TRANSITION; The present state is 1 and it has to change to 0. This can happen either J=0 and K=1 or J=K=1. That mean always K=1 and J=0 or1 K=1 and J=X( don’t care) 1 1 TRANSITION; The present state is 1 and it has to change to 1. This can happen either J=K=0 or J=1 and K=0. That mean always K=0 and J can be either level K=0 and J=X( don’t care) 16 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design Design Procedure Given a Counter sequence, C B A 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 0 0 0 1 etc. 17 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (1) STEP -1 Draw the state transition diagram showing all the possible states, including those that are not part of the desired counting sequence 18 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (1) ….cont. STEP -2 Use the state transition diagram to set up a table that lists all PRESENT states and their NEXT states Present state Next state C B A C B A 1 0 0 0 0 0 1 2 0 0 1 0 1 0 3 0 1 0 0 1 1 4 0 1 1 1 0 0 5 1 0 0 0 0 0 6 1 0 1 0 0 0 7 1 1 0 0 0 0 8 1 1 1 0 0 0 19 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (1) ….cont. STEP -3 Add a column to this table for each J and K input. For each PRESENT state, indicate the level required at each J and K input in order to produce the transition to the NEXT state. Present state Next state C B A C B A jC kC jB kB jA kA 1 0 0 0 0 0 1 0 X 0 X 1 X 2 0 0 1 0 1 0 0 X 1 X X 1 3 0 1 0 0 1 1 0 X X 0 1 X 4 0 1 1 1 0 0 1 X X 1 X 1 5 1 0 0 0 0 0 X 1 0 X 0 X 6 1 0 1 0 0 0 X 1 0 X X 1 7 1 1 0 0 0 0 X 1 X 1 0 X 8 1 1 1 0 0 0 X 1 X 1 X 1 20 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (1) ….cont. STEP- 4 Design the logic expression to generate the level required at each J and K, using K-maps. A A Present state C B A jA kA BC 1 X A A 0 0 0 1 X BC X 1 BC 0 X 0 0 1 X 1 0 1 0 1 X 0 X BC X 1 BC BC X X 0 1 1 X 1 BC 1 X 1 0 0 0 X BC X 1 1 0 1 X 1 1 1 0 0 X jA= C kA = 1 1 1 1 X 1 21 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (1) ….cont. STEP- 4 …..cont. Present state C B A jB kB A A 0 0 0 0 X BC 0 1 0 0 1 1 X BC 0 0 0 1 0 X 0 A A BC X X 0 1 1 X 1 BC X X BC X X 1 0 0 X X BC X X jB = A C 1 0 1 X X BC 1 1 1 1 0 X 1 1 1 1 X 1 BC 0 1 kB = A+C 22 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (1) ….cont. STEP- 4 …..cont. Present state C B A jC kC 0 0 0 0 X 0 0 1 0 X 0 1 0 0 X 0 1 1 1 X 1 0 0 0 1 A A A A 1 0 1 X 1 1 1 0 0 1 BC X X BC 0 0 1 1 1 X 1 BC 1 1 BC X X BC 1 1 BC X X BC X X BC 0 1 jC = AB kC = 1 23 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (1) ….cont. SETP -5 Finally to implement the final expressions. 24 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (2) Design a JK synchronous counter that has the following ? sequence:000,010,101,110 and repeat. The undesired states 001,011,100 and 111 must always go to 000 on the next clock pulse. STEP -1 :State Transition Diagram 25 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (2) ….cont. STEP- 2 : Table to list PRESENT and NEXT status 26 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (2) ….cont. STEP- 3 : Table indicate the Level required at each J and K inputs in order to produce the transition to the NEXT 27 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (2) ….cont. STEP- 4 :Design the logic circuits to generate the levels required at each J and K inputs 28 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (2) ….cont. STEP- 5 :Simplify the SOP expression using K-maps 29 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (2) ….cont. 30 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (3) Design a JK synchronous counter that has the following ? sequence:000,010,101,110 and repeat. For undesired states their NEXT states can be DON’T CARES. STEP -1 :State Transition Diagram 31 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (3) ….cont. STEP- 2 : Table to list PRESENT and NEXT status 32 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (3) ….cont. STEP- 3 : Table indicate the Level required at each J and K inputs in order to produce the transition to the NEXT 33 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (3) ….cont. STEP- 4 :Design the logic circuits to generate the levels required at each J and K inputs 34 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (3) ….cont. STEP- 5 :Simplify the SOP expression using K-maps 35 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (3) ….cont. 36 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (4) ….cont. Objective: To design a 3 bit counter (D FF) with the following count sequence 7,6,5,4,1. All unwanted stages go to 7. Output sequence 7,6,5,4,1 In 3 bits format: 111,110, 101, 100, 001 State transition diagram: 000 010 111 011 110 101 001 100 37 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (4) ….cont. Truth table for NGT D flip-flop CLK Q Qt Qt’ PRESET CLEAR D 1 1 0 ↓ 0 0 1 0 ↓ 1 0 1 1 ↓ 0 1 0 1 ↓ 1 1 0 D Flip Flop Excitation Table: PRESENT NEXT D 0 0 0 0 1 1 1 0 0 1 1 1 38 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (4) ….cont. OUTPUT INPUT PRESENT STATE NEXT STATE C B A C B A C B A D DB DA C 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 1 1 0 1 1 0 0 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1 1 0 1 1 0 39 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (4) ….cont. K- Map A A A A A A CB 1 1 CB 1 1 CB 1 1 CB 1 1 CB 1 1 CB 1 1 CB 1 1 0 1 CB 0 1 CB CB 1 0 CB 0 0 DC CB 1 0 =A+ DB = AB C’ + B DA = A’ + + C’ C’ Pls draw the cct as a home work 40 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (5) ….cont. Objective: To design a 3 bit counter (T FF) with the following count sequence 7,6,5,4,1. All unwanted stages go to 7. SOLUTION Output sequence 7,6,5,4,1 In 3 bits format: 111,110, 101, 100, 001 State transition diagram: 010 000 111 011 110 101 001 100 41 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (5) ….cont. Truth table for NGT T flip-flop PRESET CLEAR CL Q Qt Qt’ T K 1 1 0 ↓ 0 0 1 No change 0 ↓ 1 1 0 No change 1 ↓ 0 1 0 Toggle 1 ↓ 1 0 1 Toggle 42 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (5) ….cont. T Flip Flop Excitation Table: PRESENT NEXT T 0 0 0 0 1 1 1 0 1 1 1 0 43 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (5) ….cont. T Flip Flop Input Function Table OUTPUT INPUT PRESENT STATE NEXT STATE C B A C B A C B A TC TB TA 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 0 0 1 0 0 0 0 1 1 0 1 1 0 1 1 0 0 0 0 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 0 0 0 1 44 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Example (5) ….cont. K- Map A A A A A A 1 1 1 1 1 0 CB CB CB CB 1 1 CB 0 0 1 0 CB CB 0 0 CB 1 0 CB 1 1 CB 1 0 CB 0 0 CB 1 1 TC =A’B’ TB = + C’ B’C’ + TA = A’ A’BC +C Pls draw the cct as a home work 45 DIGITAL SYSTEMS TCE1111 Synchronous Counter Design / Execise Objective: To design a 3 bit counter (JK FF) with the following count sequence 4,5,7,1,3. All unwanted stages go to 4. 46