GCSE Electronics: Component 2 - Sequential Systems PDF

GCSE Electronics: Component 2 Unit 3: Sequential systems (Page 1) Sequential systems 2. Latch 3. Binary counters Sequential logic systems involve feedback so that the pre...

GCSE Electronics: Component 2 Unit 3: Sequential systems (Page 1) Sequential systems 2. Latch 3. Binary counters Sequential logic systems involve feedback so that the previous As well as transferring data from one terminal to another on Often, we need to count events, such as the number of boxes state of the output of the logic system also has an impact the rising edge of the clock pulse, a D-type flip-flop can also be moving along a conveyor belt or the number of cars entering on whether a change in the inputs produces a change in the used to make a latch. a car park. We can use electronic counters to perform the output(s). counting. In this section, we will examine how the D-type can be The circuit diagram for this application is shown below. used to make a counting system. D-type flip-flops Configuring the D-type flip-flop to produce a divide-by-two A monostable timer has one stable state, and an astable has function no stable states. A bistable, or flip-flop, has two stable states. This means that an output can be switched from logic 0 to 1 or logic 1 to 0 when required. However, once set into either of these states, it will remain there indefinitely, so long as the power is maintained. There are many uses for D-type flip-flops in electronics such as data transfer, latches and counters. 1. Data transfer When a logic 1 signal is applied to Clock (>) input,whatever logic state is present at the ‘D’ Notice that the D input is permanently connected to the input will be transferred to the ‘Q’ output. Special positive of the power supply (logic level 1). A momentary Notice that the only connection is the link between Q and D. A circuitry inside the D-Type ensures that this press on switch S1 provides a rising edged clock pulse to the pulse generator is connected to the clock input. Initially, Q and transfer only occurs when the clock signal is D-type. The logic 1 from the D input is passed through to the Q clock are at logic 0 and Q and D at logic 1. changing from logic 0 and logic 1. output which will remain at logic 1 until the D-type is reset by momentarily pressing switch S2. The timing diagram is shown below. This action is usually referred to as rising edge triggered. Once the clock signal reaches logic 1, any further changes at the D-input will not be transferred to the output until another rising The action of the latch is summarised in the following graph. edge signal is applied to the clock input. S2 This pattern would continue in the same way for further clock cycles. Notice that the output from Q has exactly half the frequency of the clock pulse, so this circuit could also be used as a simple The rising edged clock pulse could also be provided by a frequency divider (the divide-by-two function). sensing sub-system or the output from a logic gate.  GCSE Electronics: Component 2 Unit 1: Sequential systems (Page 2) A 2-bit binary up counter Counter ICs The binary digit in the ‘A’ column is referred to as the least significant bit (LSB) as it is the one that changes the most The divide-by-two action forms the basic building block of a In principle, we could keep adding D-type flip-flops to extend often. binary counter. Another name for this circuit is a 1-bit counter. the counter to 3, 4, 5, 6, 7 or 8 bits. In practice, this requires a lot of connections, which would take up a lot of space in a circuit. The binary digit in the ‘D’ column is referred to as the most Two 1-bit counters can be joined together as shown below to Instead, these counters are available as single chip devices significant bit (MSB) as it is the one that changes the least form a 2-bit binary up counter. called counter ICs. often. A 2-bit counter is probably easier to build from D-type flip-flops. Types of counter For 3 bits or more, counter ICs will be more suitable, as fewer connections will need to be made. The number of bits (binary digits) in the counter determines the highest number it can count up to before resetting. A 4-bit counter can count from 0 to 15 in binary, whereas an 8-bit counter can count from 0 to 255 in binary. Different varieties of Notice that the clock input of the second counter is connected counter are available: up, down, up/down, rising edge triggered, to the Q output of the first. Initially, QA and QB are at logic 0 falling edge triggered, binary coded decimal (BCD), decade (Clock In = logic 0, QA = DA = logic 1, QB = DB = 1). counters, etc. Resetting a counter at a given value Note: Sometimes we need a counter that counts only up to five or six i. The single clock input. for example. In this case, we need to apply an external reset to ii. The circle on the clock terminal of the right-hand diagram the counter IC at the correct point in the counting sequence. indicating falling edge triggered. To achieve this, we need to reset the counter on the binary number that is one higher than the last number required in the iii. The outputs A, B, C, D (A being the least significant bit). sequence. iv. The reset terminal, which is active high, i.e. a logic 1 causes the counter to reset. (Alternatively, if the reset terminal is labelled R, then it is active low, i.e. a logic 0 is needed to cause the counter to reset.) The output of a 4-bit counter is shown below. Looking at the values of QB and QA after each clock pulse shows us that we are counting up in binary. The QA output is represented by the right-hand digit and is The effect this has on the display is that it does not have time referred to as the least significant bit (LSB) as it is the one that to show the number 9 before it is reset to zero. The sequence changes the most often. shown on the display will be 0, 1, 2, 3, 4, 5, 6, 7, 8, 0, 1, 2, etc.