Computer Organization and Architecture Notes & Ebook PDF

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Studynama.com powers Engineers, Doctors, Managers & Lawyers in India by providing 'free' resources for aspiring students of these courses as well as students in colleges. You get FREE Lecture notes, Seminar presentations, guides, major and minor projects. Also, discuss your career prospects and other queries with an ever-growing community. Visit us for more FREE downloads: www.studynama.com ALL FILES ON STUDYNAMA.COM ARE UPLOADED BY RESPECTIVE USERS WHO MAY OR MAY NOT BE THE OWNERS OF THESE FILES. FOR ANY SUGGESTIONS OR FEEDBACK, EMAIL US AT [email protected]  CS1252 – COMPUTER ORGANIZATION AND ARCHITECTURE (Common to CSE and IT) LTPC 3104 UNIT I BASIC STRUCTURE OF COMPUTERS 9 Functional units – Basic operational concepts – Bus structures – Performance and metrics – Instructions and instruction sequencing – Hardware – Software interface – Instruction set architecture – Addressing modes – RISC – CISC – ALU design – Fixed point and floating point operations. UNIT II BASIC PROCESSING UNIT 9 Fundamental concepts – Execution of a complete instruction – Multiple bus organization – Hardwired control – Micro programmed control – Nano programming. UNIT III PIPELINING 9 Basic concepts – Data hazards – Instruction hazards – Influence on instruction sets – Data path and control considerations – Performance considerations – Exception handling. UNIT IV MEMORY SYSTEM 9 Basic concepts – Semiconductor RAM – ROM – Speed – Size and cost – Cache memories – Improving cache performance – Virtual memory – Memory management requirements – Associative memories – Secondary storage devices. UNIT V I/O ORGANIZATION 9 Accessing I/O devices – Programmed I/O – Interrupts – Direct memory access – Buses – Interface Circuits – Standard I/O interfaces (PCI, SCSI, and USB) – I/O Devices and processors. L: 45 T: 15 Total: 60 TEXT BOOKS 1. Carl Hamacher, Zvonko Vranesic and Safwat Zaky, “Computer Organization”, 5th Edition, Tata Mc-Graw Hill, 2002. 2. Heuring, V.P. and Jordan, H.F., “Computer Systems Design and Architecture”, 2nd Edition, Pearson Education, 2004. REFERENCES 1. Patterson, D. A., and Hennessy, J.L., “Computer Organization and Design:The Hardware/Software Interface”, 3rd Edition, Elsevier, 2005. 2. William Stallings, “Computer Organization and Architecture – Designing for Performance”, 6th Edition, Pearson Education, 2003. 3. Hayes, J.P., “Computer Architecture and Organization”, 3rd Edition, Tata Mc-Graw Hill, 1998.  UNIT I BASIC STRUCTURE OF COMPUTERS  Functional units  Basic operational concepts  Bus structures  Performance and metrics  Instructions and instruction sequencing  Hardware  Software interface  Instruction set architecture  Addressing modes  RISC  CISC  ALU design  Fixed point and floating point operations BASIC STRUCTURE OF COMPUTERS: Computer Organization: It refers to the operational units and their interconnections that realize the architectural specifications. It describes the function of and design of the various units of digital computer that store and process information. Computer hardware: Consists of electronic circuits, displays, magnetic and optical storage media, electromechanical equipment and communication facilities. Computer Architecture:  It is concerned with the structure and behaviour of the computer.  It includes the information formats, the instruction set and techniques for addressing memory. Functional Units A computer consists of 5 main parts.  Input  Memory  Arithmetic and logic  Output  Control Units Functional units of a Computer   Input unit accepts coded information from human operators, from electromechanical devices such as keyboards, or from other computers over digital communication lines.  The information received is either stored in the computers memory for later reference or immediately used by the arithmetic and logic circuitry to perform the desired operations.  The processing steps are determined by a program stored in the memory.  Finally the results are sent back to the outside world through the output unit.  All of these actions are coordinated by the control unit.  The list of instructions that performs a task is called a program.  Usually the program is stored in the memory.  The processor then fetches the instruction that make up the program from the memory one after another and performs the desire operations. 1.1 Input Unit:  Computers accept coded information through input units, which read the data.  Whenever a key is pressed, the corresponding letter or digit is automatically translated into its corresponding binary code and transmitted over a cable to either the memory or the processor. Some input devices are  Joysticks  Trackballs  Mouses  Microphones (Capture audio input and it is sampled & it is converted into digital codes for storage and processing). 1.2.Memory Unit: It stores the programs and data. There are 2 types of storage classes  Primary  Secondary Primary Storage:  It is a fast memory that operates at electronic speeds.  Programs must be stored in the memory while they are being executed.  The memory contains large no of semiconductor storage cells.  Each cell carries 1 bit of information.  The Cells are processed in a group of fixed size called Words.  To provide easy access to any word in a memory,a distinct address is associated with each word location.   Addresses are numbers that identify successive locations.  The number of bits in each word is called the word length.  The word length ranges from 16 to 64 bits.  There are 3 types of memory.They are  RAM(Random Access Memory)  Cache memory  Main Memory RAM: Memory in which any location can be reached in short and fixed amount of time after specifying its address is called RAM. Time required to access 1 word is called Memory Access Time. Cache Memory: The small,fast,RAM units are called Cache. They are tightly coupled with processor to achieve high performance. Main Memory: The largest and the slowest unit is called the main memory. 1.3. ALU: Most computer operations are executed in ALU. Consider a example, Suppose 2 numbers located in memory are to be added. They are brought into the processor and the actual addition is carried out by the ALU. The sum may then be stored in the memory or retained in the processor for immediate use. Access time to registers is faster than access time to the fastest cache unit in memory. 1.4. Output Unit: Its function is to send the processed results to the outside world. eg.Printer Printers are capable of printing 10000 lines per minute but its speed is comparatively slower than the processor. 1.5. Control Unit: The operations of Input unit, output unit, ALU are co-ordinate by the control unit. The control unit is the Nerve centre that sends control signals to other units and senses their states. Data transfers between the processor and the memory are also controlled by the control unit through timing signals. The operation of computers are,  The computer accepts information in the form of programs and data through an input unit and stores it in the memory.   Information stored in the memory is fetched, under program control into an arithmetic and logic unit, where it is processed.  Processed information leaves the computer through an output unit.  All activities inside the machine are directed by the control unit. BASIC OPERATIONAL CONCEPTS: The data/operands are stored in memory. The individual instruction are brought from the memory to the processor, which executes the specified operation. Eg:1 Add LOC A ,R1 Instructions are fetched from memory and the operand at LOC A is fetched. It is then added to the contents of R0, the resulting sum is stored in Register R0. Eg:2 Load LOC A, R1 Transfer the contents of memory location A to the register R1. Eg:3 Add R1 ,R0 Add the contents of Register R1 & R0 and places the sum into R0. Fig:Connection between Processor and Main Memory  Instruction Register(IR)  Program Counter(PC)   Memory Address Register(MAR)  Memory Data Register(MDR) Instruction Register (IR):  It holds the instruction that is currently being executed.  It generates the timing signals. Program Counter (PC): It contains the memory address of the next instruction to be fetched for execution. Memory Address Register (MAR): It holds the address of the location to be accessed. Memory Data Register (MDR):  It contains the data to written into or read out of the address location.  MAR and MDR facilitates the communication with memory. Operation Steps:  The program resides in memory. The execution starts when PC is point to the first instruction of the program.  MAR read the control signal.  The Memory loads the address word into MDR.The contents are transferred to Instruction register. The instruction is ready to be decoded & executed. Interrupt:  Normal execution of the program may be pre-empted if some device requires urgent servicing.  Eg...Monitoring Device in a computer controlled industrial process may detect a dangerous condition.  In order to deal with the situation immediately, the normal execution of the current program may be interrupted & the device raises an interrupt signal.  The processor provides the requested service called the Interrupt Service Routine(ISR).  ISR save the internal state of the processor in memory before servicing the interrupt because interrupt may alter the state of the processor.  When ISR is completed, the state of the processor is restored and the interrupted program may continue its execution. BUS STRUCTURES: A group of lines that serves as the connection path to several devices is called a Bus. A Bus may be lines or wires or one bit per line. The lines carry data or address or control signal. There are 2 types of Bus structures. They are Single Bus Structure Multiple Bus Structure 3.1.Single Bus Structure: It allows only one transfer at a time. It costs low. It is flexible for attaching peripheral devices. Its Performance is low. 3.2.Multiple Bus Structure: It allows two or more transfer at a time. It costs high. It provides concurrency in operation. Its Performance is high. Devices Connected with Bus Speed Electro-mechanical decvices (Keyboard,printer) Slow Magnetic / optical disk High Memory & processing units Very High The Buffer Register when connected with the bus, carries the information during transfer. The Buffer Register prevents the high speed processor from being locked to a slow I/O device during a sequence of data transfer. SOFTWARE: System Software is a collection of programs that are executed as needed to perform function such as,  Receiving & Interpreting user commands.  Entering & editing application program and storing them as files in secondary Storage devices.  Managing the storage and retrieval of files in Secondary Storage devices.  Running the standard application such as word processor, games, and spreadsheets with data supplied by the user.  Controlling I/O units to receive input information and produce output results.  Translating programs from source form prepared by the user into object form.  Linking and running user-written application programs with existing standard library routines. Software is of 2 types.They are  Application program  System program Application Program: It is written in high level programming language(C,C++,Java,Fortran) The programmer using high level language need not know the details of machine program instruction. System Program:(Compiler,Text Editor,File) Compiler: It translates the high level language program into the machine language program. Text Editor: It is used for entering & editing the application program. System software Component ->OS(OPERATING SYSTEM) Operating System : It is a large program or a collection of routines that is used to control the sharing of and interaction among various computer units. Functions of OS:  Assign resources to individual application program.  Assign memory and magnetic disk space to program and data files.   Move the data between the memory and disk units.  Handles I/O operation. Fig:User Program and OS routine sharing of the process Steps: 1. The first step is to transfer the file into memory. 2. When the transfer is completed, the execution of the program starts. 3. During time period ‘t0’ to ‘t1’ , an OS routine initiates loading the application program from disk to memory, wait until the transfer is complete and then passes the execution control to the application program & print the results. 4. Similar action takes place during ‘t2’ to ‘t3’ and ‘t4’ to ‘t5’. 5. At ‘t5’, Operating System may load and execute another application program. 6. Similarly during ‘t0’ to ‘t1’ , the Operating System can arrange to print the previous program’s results while the current program is being executed. 7. The pattern of managing the concurrent execution of the several application programs to make the best possible use of computer resources is called the multi- programming or multi-tasking. PERFORMANCE: For best performance, it is necessary to design the compiler, machine instruction set and hardware in a co-ordinate way. Elapsed Timethe total time required to execute the program is called the elapsed time. It depends on all the units in computer system. Processor TimeThe period in which the processor is active is called the processor time. It depends on hardware involved in the execution of the instruction. Fig: The Processor Cache A Program will be executed faster if the movement of instruction and data between the main memory and the processor is minimized, which is achieved by using the Cache. Processor clock: ClockThe Processor circuits are controlled by a timing signal called a clock. Clock CycleThe cycle defines a regular time interval called clock cycle. Clock Rate,R =1/P Where, PLength of one clock cycle. Basic Performance Equation: T = (N*S)/R Where, TPerformance Parameter RClock Rate in cycles/sec  NActual number of instruction execution SAverage number of basic steps needed to execute one machine instruction. To achieve high performance, N,S0.During each pass,the address of the next list entry is determined and the entry is fetched and added to R0. Decrement R1   It reduces the contents of R1 by 1 each time through the loop. Branch >0 Loop  A conditional branch instruction causes a branch only if a specified condition is satisfied. Fig:Using loop to add ‘n’ numbers: Conditional Codes: Result of various operation for user by subsequent conditional branch instruction is accomplished by recording the required information in individual bits often called Condition code Flags. Commonly used flags:   N(Negative)set to 1 if the result is –ve ,otherwise cleared to 0.  Z(Zero) set to 1 if the result is 0 ,otherwise cleared to 0.  V(Overflow) set to 1 if arithmetic overflow occurs ,otherwise cleared to 0.  C(Carry)set to 1 if carry and results from the operation ,otherwise cleared to 0. ADDRESSING MODES The different ways in which the location of an operand is specified in an instruction is called as Addressing mode. Generic Addressing Modes:  Immediate mode  Register mode  Absolute mode  Indirect mode  Index mode  Base with index  Base with index and offset  Relative mode  Auto-increment mode  Auto-decrement mode Implementation of Variables and Constants: Variables: The value can be changed as needed using the appropriate instructions. There are 2 accessing modes to access the variables. They are  Register Mode  Absolute Mode Register Mode: The operand is the contents of the processor register. The name(address) of the register is given in the instruction. Absolute Mode(Direct Mode):  The operand is in new location.  The address of this location is given explicitly in the instruction. Eg: MOVE LOC,R2 The above instruction uses the register and absolute mode. The processor register is the temporary storage where the data in the register are accessed using register mode. The absolute mode can represent global variables in the program. Mode Assembler Syntax Addressing Function Register mode Ri EA=Ri Absolute mode LOC EA=LOC Where EA-Effective Address Constants: Address and data constants can be represented in assembly language using Immediate Mode. Immediate Mode. The operand is given explicitly in the instruction. Eg: Move 200 immediate ,R0 It places the value 200 in the register R0.The immediate mode used to specify the value of source operand. In assembly language, the immediate subscript is not appropriate so # symbol is used. It can be re-written as Move #200,R0 Assembly Syntax: Addressing Function Immediate #value Operand =value Indirection and Pointers: Instruction does not give the operand or its address explicitly.Instead it provides information from which the new address of the operand can be determined.This address is called effective Address(EA) of the operand. Indirect Mode:  The effective address of the operand is the contents of a register.  We denote the indirection by the name of the register or new address given in the instruction. Fig:Indirect Mode Add (A),R0 Add (R1),R0 B … Operand Operand Address of an operand(B) is stored into R1 register.If we want this operand,we can get it through register R1(indirection). The register or new location that contains the address of an operand is called the pointer. Mode Assembler Syntax Addressing Function Indirect Ri , LOC EA=[Ri] or EA=[LOC] Indexing and Arrays: Index Mode:  The effective address of an operand is generated by adding a constant value to the contents of a register.  The constant value uses either special purpose or general purpose register.  We indicate the index mode symbolically as, X(Ri) Where X – denotes the constant value contained in the instruction Ri – It is the name of the register involved. The Effective Address of the operand is, EA=X + [Ri] The index register R1 contains the address of a new location and the value of X defines an offset(also called a displacement). To find operand,  First go to Reg R1 (using address)-read the content from R1-1000  Add the content 1000 with offset 20 get the result.  1000+20=1020  Here the constant X refers to the new address and the contents of index register define the offset to the operand.  The sum of two values is given explicitly in the instruction and the other is stored in register. Eg: Add 20(R1) , R2 (or) EA=>1000+20=1020 Index Mode Assembler Syntax Addressing Function Index X(Ri) EA=[Ri]+X Base with Index (Ri,Rj) EA=[Ri]+[Rj] Base with Index and offset X(Ri,Rj) EA=[Ri]+[Rj] +X Relative Addressing: It is same as index mode. The difference is, instead of general purpose register, here we can use program counter(PC). Relative Mode:  The Effective Address is determined by the Index mode using the PC in place of the general purpose register (gpr).  This mode can be used to access the data operand. But its most common use is to specify the target address in branch instruction.Eg. Branch>0 Loop  It causes the program execution to goto the branch target location. It is identified by the name loop if the branch condition is satisfied. Mode Assembler Syntax Addressing Function Relative X(PC) EA=[PC]+X Additional Modes: There are two additional modes. They are   Auto-increment mode  Auto-decrement mode Auto-increment mode:  The Effective Address of the operand is the contents of a register in the instruction.  After accessing the operand, the contents of this register is automatically incremented to point to the next item in the list. Mode Assembler syntax Addressing Function Auto-increment (Ri)+ EA=[Ri]; Increment Ri Auto-decrement mode:  The Effective Address of the operand is the contents of a register in the instruction.  After accessing the operand, the contents of this register is automatically decremented to point to the next item in the list. Mode Assembler Syntax Addressing Function Auto-decrement -(Ri) EA=[Ri]; Decrement Ri CISC Pronounced sisk, and stands for Complex Instruction Set Computer. Most PC's use CPU based on this architecture. For instance Intel and AMD CPU's are based on CISC architectures. Typically CISC chips have a large amount of different and complex instructions. The philosophy behind it is that hardware is always faster than software, therefore one should make a powerful instruction set, which provides programmers with assembly instructions to do a lot with short programs. In common CISC chips are relatively slow (compared to RISC chips) per instruction, but use little (less than RISC) instructions. RISC Pronounced risk, and stands for Reduced Instruction Set Computer. RISC chips evolved around the mid-1980 as a reaction at CISC chips. The philosophy behind it is that almost no one uses complex assembly language instructions as used by CISC, and people mostly use compilers which never use complex instructions. Apple for instance uses RISC chips. Therefore fewer, simpler and faster instructions would be better, than the large, complex and slower CISC instructions. However, more instructions are needed to accomplish a task. An other advantage of RISC is that - in theory - because of the more simple instructions, RISC chips require fewer transistors, which makes them easier to design and cheaper to produce. Finally, it's easier to write powerful optimised compilers, since fewer instructions exist. RISC vs CISC There is still considerable controversy among experts about which architecture is better. Some say that RISC is cheaper and faster and therefor the architecture of the future. Others note that by making the hardware simpler, RISC puts a greater burden on the software. Software needs to become more complex. Software developers need to write more lines for the same tasks. Therefore they argue that RISC is not the architecture of the future, since conventional CISC chips are becoming faster and cheaper anyway. RISC has now existed more than 10 years and hasn't been able to kick CISC out of the market. If we forget about the embedded market and mainly look at the market for PC's, workstations and servers I guess a least 75% of the processors are based on the CISC architecture. Most of them the x86 standard (Intel, AMD, etc.), but even in the mainframe territory CISC is dominant via the IBM/390 chip. Looks like CISC is here to stay … Is RISC than really not better? The answer isn't quite that simple. RISC and CISC architectures are becoming more and more alike. Many of today's RISC chips support just as many instructions as yesterday's CISC chips. The PowerPC 601, for example, supports more instructions than the Pentium. Yet the 601 is considered a RISC chip, while the Pentium is definitely CISC. Further more today's CISC chips use many techniques formerly associated with RISC chips. ALU Design In computing an arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and logical operations. The ALU is a fundamental building block of the central processing unit (CPU) of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers. The processors found inside modern CPUs and graphics processing units (GPUs) accommodate very powerful and very complex ALUs; a single component may contain a number of ALUs. Mathematician John von Neumann proposed the ALU concept in 1945, when he wrote a report on the foundations for a new computer called the EDVAC. Research into ALUs remains an important part of computer science, falling under Arithmetic and logic structures in the ACM Computing Classification System Numerical systems An ALU must process numbers using the same format as the rest of the digital circuit. The format of modern processors is almost always the two's complement binary number representation. Early computers used a wide variety of number systems, including ones' complement, Two's complement sign-magnitude format, and even true decimal systems, with ten tubes per digit. ALUs for each one of these numeric systems had different designs, and that influenced the current preference for two's complement, as this is the representation that makes it easier for the ALUs to calculate additions and subtractions. The ones' complement and Two's complement number systems allow for subtraction to be accomplished by adding the negative of a number in a very simple way which negates the need for specialized circuits to do subtraction; however, calculating the negative in Two's complement requires adding a one to the low order bit and propagating the carry. An alternative way to do Two's complement subtraction of A-B is present a 1 to the carry input of the adder and use ~B rather than B as the second input. Practical overview Most of a processor's operations are performed by one or more ALUs. An ALU loads data from input registers, an external Control Unit then tells the ALU what operation to perform on that data, and then the ALU stores its result into an output register. Other mechanisms move data between these registers and memory. Simple operations A simple example arithmetic logic unit (2-bit ALU) that does AND, OR, XOR, and addition Most ALUs can perform the following operations:  Integer arithmetic operations (addition, subtraction, and sometimes multiplication and division, though this is more expensive)  Bitwise logic operations (AND, NOT, OR, XOR)  Bit-shifting operations (shifting or rotating a word by a specified number of bits to the left or right, with or without sign extension). Shifts can be interpreted as multiplications by 2 and divisions by 2. Complex operations Engineers can design an Arithmetic Logic Unit to calculate any operation. The more complex the operation, the more expensive the ALU is, the more space it uses in the processor, the more power it dissipates. Therefore, engineers compromise. They make the ALU powerful enough to make the processor fast, but yet not so complex as to become prohibitive. For example, computing the square root of a number might use: 1. Calculation in a single clock Design an extraordinarily complex ALU that calculates the square root of any number in a single step. 2. Calculation pipeline Design a very complex ALU that calculates the square root of any number in several steps. The intermediate results go through a series of circuits arranged like a factory production line. The ALU can accept new numbers to calculate even before having finished the previous ones. The ALU can now  produce numbers as fast as a single-clock ALU, although the results start to flow out of the ALU only after an initial delay. 3. interactive calculation Design a complex ALU that calculates the square root through several steps. This usually relies on control from a complex control unit with built-in microcode 4. Co-processor Design a simple ALU in the processor, and sell a separate specialized and costly processor that the customer can install just beside this one, and implements one of the options above. 5. Software libraries Tell the programmers that there is no co-processor and there is no emulation, so they will have to write their own algorithms to calculate square roots by software. 6. Software emulation Emulate the existence of the co-processor, that is, whenever a program attempts to perform the square root calculation, make the processor check if there is a co-processor present and use it if there is one; if there isn't one, interrupt the processing of the program and invoke the operating system to perform the square root calculation through some software algorithm. The options above go from the fastest and most expensive one to the slowest and least expensive one. Therefore, while even the simplest computer can calculate the most complicated formula, the simplest computers will usually take a long time doing that because of the several steps for calculating the formula. Powerful processors like the Intel Core and AMD64 implement option #1 for several simple operations, #2 for the most common complex operations and #3 for the extremely complex operations. Inputs and outputs The inputs to the ALU are the data to be operated on (called operands) and a code from the control unit indicating which operation to perform. Its output is the result of the computation. In many designs the ALU also takes or generates as inputs or outputs a set of condition codes from or to a status register. These codes are used to indicate cases such as carry-in or carry-out, overflow, divide-by-zero, etc. ALUs vs. FPUs A Floating Point Unit also performs arithmetic operations between two values, but they do so for numbers in floating point representation, which is much more complicated than the two's complement representation used in a typical ALU. In order to do these calculations, a FPU has several complex circuits built-in, including some internal ALUs. In modern practice, engineers typically refer to the ALU as the circuit that performs integer arithmetic operations (like two's complement and BCD). Circuits that calculate more complex formats like floating point, complex numbers, etc. usually receive a more specific name such as FPU. FIXED POINT NUMBER AND OPERATION In computing, a fixed-point number representation is a real data type for a number that has a fixed number of digits after (and sometimes also before) the radix point (e.g., after the decimal point '.' in English decimal notation). Fixed-point number representation can be compared to the more complicated (and more computationally demanding) floating point number representation. Fixed-point numbers are useful for representing fractional values, usually in base 2 or base 10, when the executing processor has no floating point unit (FPU) or if fixed-point provides improved performance or accuracy for the application at hand. Most low-cost embedded microprocessors and microcontrollers do not have an FPU. Representation A value of a fixed-point data type is essentially an integer that is scaled by a specific factor determined by the type. For example, the value 1.23 can be represented as 1230 in a fixed-point data type with scaling factor of 1/1000, and the value 1230000 can be represented as 1230 with a scaling factor of 1000. Unlike floating-point data types, the scaling factor is the same for all values of the same type, and does not change during the entire computation. The scaling factor is usually a power of 10 (for human convenience) or a power of 2 (for computational efficiency). However, other scaling factors may be used occasionally, e.g. a time value in hours may be represented as a fixed-point type with a scale factor of 1/3600 to obtain values with one-second accuracy. The maximum value of a fixed-point type is simply the largest value that can be represented in the underlying integer type, multiplied by the scaling factor; and similarly for the minimum value. For example, consider a fixed-point type represented as a binary integer with b bits in two's complement format, with a scaling factor of 1/2f (that is, the last f bits are fraction bits): the minimum representable value is −2b-1/2f and the maximum value is (2b-1-1)/2f. Operations To convert a number from a fixed point type with scaling factor R to another type with scaling factor S, the underlying integer must be multiplied by R and divided by S; that is, multiplied by the ratio R/S. Thus, for example, to convert the value 1.23 = 123/100 from a type with scaling factor R=1/100 to one with scaling factor S=1/1000, the underlying integer 123 must be multiplied by (1/100)/(1/1000) = 10, yielding the representation 1230/1000. If S does not divide R (in particular, if the new scaling factor R is less than the original S), the new integer will have to be rounded. The rounding rules and methods are usually part of the language's specification. To add or subtract two values the same fixed-point type, it is sufficient to add or subtract the underlying integers, and keep their common scaling factor. The result can be exactly represented in the same type, as long as no overflow occurs (i.e. provided that the sum of the two integers fits in the underlying integer type.) If the numbers have different fixed- point types, with different scaling factors, then one of them must be converted to the other before the sum. To multiply two fixed-point numbers, it suffices to multiply the two underlying integers, and assume that the scaling factor of the result is the product of their scaling factors. This operation involves no rounding. For example, multiplying the numbers 123 scaled by 1/1000 (0.123) and 25 scaled by 1/10 (2.5) yields the integer 123×25 = 3075 scaled by (1/1000)×(1/10) = 1/10000, that is 3075/10000 = 0.3075. If the two operands belong to the same fixed-point type, and the result is also to be represented in that type, then the product of the two integers must be explicitly multiplied by the common scaling factor; in this case the result may have to be rounded, and overflow may occur. For example, if the common scaling factor is 1/100, multiplying 1.23 by 0.25 entails multiplying 123 by 25 to yield 3075 with an intermediate scaling factor if 1/10000. This then must be multiplied by 1/100 to yield either 31 (0.31) or 30 (0.30), depending on the rounding method used, to result in a final scale factor of 1/100. To divide two fixed-point numbers, one takes the integer quotient of their underlying integers, and assumes that the scaling factor is the quotient of their scaling factors. The first division involves rounding in general. For example, division of 3456 scaled by 1/100 (34.56) by 1234 scaled by 1/1000 (1.234) yields the integer 3456÷1234 = 3 (rounded) with scale factor (1/100)/(1/1000) = 10, that is, 30. One can obtain a more accurate result by first converting the dividend to a more precise type: in the same example, converting 3456 scaled by 1/100 (34.56) to 3456000 scaled by 1/100000, before dividing by 1234 scaled by 1/1000 (1.234), would yield 3456000÷1234 = 2801 (rounded) with scaling factor (1/100000)/(1/1000) = 1/100, that is 28.01 (instead of 290). If both operands and the desired result are represented in the same fixed-point type, then the quotient of the two integers must be explicitly divided by the common scaling factor. Precision loss and overflow Because fixed point operations can produce results that have more bits than the operands there is possibility for information loss. For instance, the result of fixed point multiplication could potentially have as many bits as the sum of the number of bits in the two operands. In order to fit the result into the same number of bits as the operands, the answer must be rounded or truncated. If this is the case, the choice of which bits to keep is very important. When multiplying two fixed point numbers with the same format, for instance with I integer bits, and Q fractional bits, the answer could have up to 2I integer bits, and 2Q fractional bits. For simplicity, fixed-point multiply procedures use the same result format as the operands. This has the effect of keeping the middle bits; the I-number of least significant integer bits, and the Q-number of most significant fractional bits. Fractional bits lost below this value represent a precision loss which is common in fractional multiplication. If any integer bits are lost, however, the value will be radically inaccurate. Some operations, like divide, often have built-in result limiting so that any positive overflow results in the largest possible number that can be represented by the current format. Likewise, negative overflow results in the largest negative number represented by the current format. This built in limiting is often referred to as saturation. Some processors support a hardware overflow flag that can generate an exception on the occurrence of an overflow, but it is usually too late to salvage the proper result at this point. FLOATING POINT NUMBERS & OPERATIONS Floating point Representation: To represent the fractional binary numbers, it is necessary to consider binary point.If binary point is assumed to the right of the sign bit ,we can represent the fractional binary numbers as given below, B= (b0 * 20 +b-1 * 2-1 + b-2 * 2-2 +….+ b-(n-1) * 2-(n-1) ) With this fractional number system,we can represent the fractional numbers in the following range, -1 < F threshold value -> Bit line will have logic value ‘1’. If charge on capacitor < threshold value -> Bit line will set to logic value ‘0’. Fig:Internal organization of a 2M X 8 dynamic Memory chip. DESCRIPTION:  The 4 bit cells in each row are divided into 512 groups of 8.  21 bit address is needed to access a byte in the memory(12 bitTo select a row,9 bitSpecify the group of 8 bits in the selected row). A8-0 Row address of a byte. A20-9 Column address of a byte.  During Read/ Write operation ,the row address is applied first. It is loaded into the row address latch in response to a signal pulse on Row Address Strobe(RAS) input of the chip.  When a Read operation is initiated, all cells on the selected row are read and refreshed.  Shortly after the row address is loaded,the column address is applied to the address pins & loaded into Column Address Strobe(CAS).  The information in this latch is decoded and the appropriate group of 8 Sense/Write circuits are selected.  R/W =1(read operation)The output values of the selected circuits are transferred to the data lines D0 - D7.  R/W =0(write operation)The information on D0 - D7 are transferred to the selected circuits.   RAS and CAS are active low so that they cause the latching of address when they change from high to low. This is because they are indicated by RAS & CAS.  To ensure that the contents of a DRAM ‘s are maintained, each row of cells must be accessed periodically.  Refresh operation usually perform this function automatically.  A specialized memory controller circuit provides the necessary control signals RAS & CAS, that govern the timing.  The processor must take into account the delay in the response of the memory. Such memories are referred to as Asynchronous DRAM’s. Fast Page Mode:  Transferring the bytes in sequential order is achieved by applying the consecutive sequence of column address under the control of successive CAS signals.  This scheme allows transferring a block of data at a faster rate. The block of transfer capability is called as Fast Page Mode. Synchronous DRAM:  Here the operations e directly synchronized with clock signal.  The address and data connections are buffered by means of registers.  The output of each sense amplifier is connected to a latch.  A Read operation causes the contents of all cells in the selected row to be loaded in these latches. Fig:Synchronous DRAM   Data held in the latches that correspond to the selected columns are transferred into the data output register, thus becoming available on the data output pins. Fig:Timing Diagram Burst Read of Length 4 in an SDRAM  First ,the row address is latched under control of RAS signal.  The memory typically takes 2 or 3 clock cycles to activate the selected row.  Then the column address is latched under the control of CAS signal.  After a delay of one clock cycle,the first set of data bits is placed on the data lines.  The SDRAM automatically increments the column address to access the next 3 sets of bits in the selected row, which are placed on the data lines in the next 3 clock cycles. Latency & Bandwidth:  A good indication of performance is given by two parameters.They are,  Latency  Bandwidth Latency:  It refers to the amount of time it takes to transfer a word of data to or from the memory.  For a transfer of single word,the latency provides the complete indication of memory performance.  For a block transfer,the latency denote the time it takes to transfer the first word of data. Bandwidth:  It is defined as the number of bits or bytes that can be transferred in one second.   Bandwidth mainly depends upon the speed of access to the stored data & on the number of bits that can be accessed in parallel. Double Data Rate SDRAM(DDR-SDRAM):  The standard SDRAM performs all actions on the rising edge of the clock signal.  The double data rate SDRAM transfer data on both the edges(loading edge, trailing edge).  The Bandwidth of DDR-SDRAM is doubled for long burst transfer.  To make it possible to access the data at high rate , the cell array is organized into two banks.  Each bank can be accessed separately.  Consecutive words of a given block are stored in different banks.  Such interleaving of words allows simultaneous access to two words that are transferred on successive edge of the clock. Larger Memories: Dynamic Memory System:  The physical implementation is done in the form of Memory Modules.  If a large memory is built by placing DRAM chips directly on the main system printed circuit board that contains the processor ,often referred to as Motherboard;it will occupy large amount of space on the board.  These packaging consideration have led to the development of larger memory units known as SIMM’s & DIMM’s. SIMM-Single Inline memory Module DIMM-Dual Inline memory Module  SIMM & DIMM consists of several memory chips on a separate small board that plugs vertically into single socket on the motherboard. MEMORY SYSTEM CONSIDERATION:  To reduce the number of pins, the dynamic memory chips use multiplexed address inputs.  The address is divided into two parts.They are,  High Order Address Bit(Select a row in cell array & it is provided first and latched into memory chips under the control of RAS signal).  Low Order Address Bit(Selects a column and they are provided on same address pins and latched using CAS signals).  The Multiplexing of address bit is usually done by Memory Controller Circuit.  Fig:Use of Memory Controller  The Controller accepts a complete address & R/W signal from the processor, under the control of a Request signal which indicates that a memory access operation is needed.  The Controller then forwards the row & column portions of the address to the memory and generates RAS &CAS signals.  It also sends R/W &CS signals to the memory.  The CS signal is usually active low, hence it is shown as CS. Refresh Overhead:  All dynamic memories have to be refreshed.  In DRAM ,the period for refreshing all rows is 16ms whereas 64ms in SDRAM. Eg:Given a cell array of 8K(8192). Clock cycle=4 Clock Rate=133MHZ No of cycles to refresh all rows =8192*4 =32,768 Time needed to refresh all rows=32768/133*106 =246*10-6 sec =0.246sec Refresh Overhead =0.246/64 Refresh Overhead =0.0038 Rambus Memory:  The usage of wide bus is expensive.  Rambus developed the implementation of narrow bus.  Rambus technology is a fast signaling method used to transfer information between chips.   Instead of using signals that have voltage levels of either 0 or Vsupply to represent the logical values, the signals consists of much smaller voltage swings around a reference voltage Vref. .The reference Voltage is about 2V and the two logical values are represented by 0.3V swings above and below Vref..  This type of signaling is generally is known as Differential Signalling.  Rambus provides a complete specification for the design of communication links(Special Interface circuits) called as Rambus Channel.  Rambus memory has a clock frequency of 400MHZ.  The data are transmitted on both the edges of the clock so that the effective data transfer rate is 800MHZ.  The circuitry needed to interface to the Rambus channel is included on the chip.Such chips are known as Rambus DRAM’s(RDRAM).  Rambus channel has,  9 Data lines(1-8Transfer the data,9th lineParity checking).  Control line  Power line  A two channel rambus has 18 data lines which has no separate address lines.It is also called as Direct RDRAM’s.  Communication between processor or some other device that can serves as a master and RDRAM modules are serves as slaves ,is carried out by means of packets transmitted on the data lines.  There are 3 types of packets.They are,  Request  Acknowledge  Data READ ONLY MEMORY:  Both SRAM and DRAM chips are volatile,which means that they lose the stored information if power is turned off.  Many application requires Non-volatile memory (which retain the stored information if power is turned off).  Eg:Operating System software has to be loaded from disk to memory which requires the program that boots the Operating System ie. It requires non-volatile memory.  Non-volatile memory is used in embedded system.  Since the normal operation involves only reading of stored data ,a memory of this type is called ROM. Fig:ROM cell At Logic value ‘0’  Transistor(T) is connected to the ground point(P). Transistor switch is closed & voltage on bitline nearly drops to zero. At Logic value ‘1’  Transistor switch is open. The bitline remains at high voltage.  To read the state of the cell,the word line is activated.  A Sense circuit at the end of the bitline generates the proper output value. Types of ROM:  Different types of non-volatile memory are,  PROM  EPROM  EEPROM  Flash Memory PROM:-Programmable ROM:  PROM allows the data to be loaded by the user.  Programmability is achieved by inserting a ‘fuse’ at point P in a ROM cell.  Before it is programmed, the memory contains all 0’s  The user can insert 1’s at the required location by burning out the fuse at these locations using high-current pulse.  This process is irreversible. Merit:  It provides flexibility.  It is faster.  It is less expensive because they can be programmed directly by the user. EPROM:-Erasable reprogrammable ROM:  EPROM allows the stored data to be erased and new data to be loaded.   In an EPROM cell, a connection to ground is always made at ‘P’ and a special transistor is used, which has the ability to function either as a normal transistor or as a disabled transistor that is always turned ‘off’.  This transistor can be programmed to behave as a permanently open switch, by injecting charge into it that becomes trapped inside.  Erasure requires dissipating the charges trapped in the transistor of memory cells. This can be done by exposing the chip to ultra-violet light, so that EPROM chips are mounted in packages that have transparent windows. Merits:  It provides flexibility during the development phase of digital system.  It is capable of retaining the stored information for a long time. Demerits:  The chip must be physically removed from the circuit for reprogramming and its entire contents are erased by UV light. EEPROM:-Electrically Erasable ROM: Merits:  It can be both programmed and erased electrically.  It allows the erasing of all cell contents selectively. Demerits:  It requires different voltage for erasing ,writing and reading the stored data. Flash Memory:  In EEPROM, it is possible to read & write the contents of a single cell.  In Flash device, it is possible to read the contents of a single cell but it is only possible to write the entire contents of a block.  Prior to writing,the previous contents of the block are erased.  Eg.In MP3 player,the flash memory stores the data that represents sound.  Single flash chips cannot provide sufficient storage capacity for embedded system application.  There are 2 methods for implementing larger memory modules consisting of number of chips.They are,  Flash Cards  Flash Drives. Merits:  Flash drives have greater density which leads to higher capacity & low cost per bit.  It requires single power supply voltage & consumes less power in their operation. Flash Cards:  One way of constructing larger module is to mount flash chips on a small card.  Such flash card have standard interface.   The card is simply plugged into a conveniently accessible slot.  Its memory size are of 8,32,64MB.  Eg:A minute of music can be stored in 1MB of memory. Hence 64MB flash cards can store an hour of music. Flash Drives:  Larger flash memory module can be developed by replacing the hard disk drive.  The flash drives are designed to fully emulate the hard disk.  The flash drives are solid state electronic devices that have no movable parts. Merits:  They have shorter seek and access time which results in faster response.  They have low power consumption which makes them attractive for battery driven application.  They are insensitive to vibration. Demerit:  The capacity of flash drive (1GB).  It leads to higher cost perbit.  Flash memory will deteriorate after it has been written a number of times(typically atleast 1 million times.) SPEED,SIZE COST: Characteristics SRAM DRAM Magnetis Disk Speed Very Fast Slower Much slower than DRAM Size Large Small Small Cost Expensive Less Expensive Low price Magnetic Disk:  A huge amount of cost effective storage can be provided by magnetic disk;The main memory can be built with DRAM which leaves SRAM’s to be used in smaller units where speed is of essence. Memory Speed Size Cost Registers Very high Lower Very Lower Primary cache High Lower Low Secondary cache Low Low Low Main memory Lower than High High Seconadry cache Secondary Very low Very High Very High Memory Fig:Memory Hierarchy Types of Cache Memory:  The Cache memory is of 2 types.They are,  Primary /Processor Cache(Level1 or L1 cache)  Secondary Cache(Level2 or L2 cache) Primary Cache  It is always located on the processor chip. Secondary CacheIt is placed between the primary cache and the rest of the memory.  The main memory is implemented using the dynamic components(SIMM,RIMM,DIMM).  The access time for main memory is about 10 times longer than the access time for L1 cache. CACHE MEMORIES  The effectiveness of cache mechanism is based on the property of ‘Locality of reference’. Locality of Reference:  Many instructions in the localized areas of the program are executed repeatedly during some time period and remainder of the program is accessed relatively infrequently.  It manifests itself in 2 ways.They are,  Temporal(The recently executed instruction are likely to be executed again very soon.)  Spatial(The instructions in close proximity to recently executed instruction are also likely to be executed soon.)  If the active segment of the program is placed in cache memory, then the total execution time can be reduced significantly.   The term Block refers to the set of contiguous address locations of some size.  The cache line is used to refer to the cache block. Fig:Use of Cache Memory  The Cache memory stores a reasonable number of blocks at a given time but this number is small compared to the total number of blocks available in Main Memory.  The correspondence between main memory block and the block in cache memory is specified by a mapping function.  The Cache control hardware decide that which block should be removed to create space for the new block that contains the referenced word.  The collection of rule for making this decision is called the replacement algorithm.  The cache control circuit determines whether the requested word currently exists in the cache.  If it exists, then Read/Write operation will take place on appropriate cache location. In this case Read/Write hit will occur.  In a Read operation, the memory will not involve.  The write operation is proceed in 2 ways.They are,  Write-through protocol  Write-back protocol Write-through protocol:  Here the cache location and the main memory locations are updated simultaneously. Write-back protocol:  This technique is to update only the cache location and to mark it as with associated flag bit called dirty/modified bit.  The word in the main memory will be updated later,when the block containing this marked word is to be removed from the cache to make room for a new block.  If the requested word currently not exists in the cache during read operation,then read miss will occur.  To overcome the read miss Load –through / Early restart protocol is used. Read Miss: The block of words that contains the requested word is copied from the main memory into cache. Load –through:  After the entire block is loaded into cache,the particular word requested is forwarded to the processor.  If the requested word not exists in the cache during write operation,then Write Miss will occur.  If Write through protocol is used,the information is written directly into main memory.  If Write back protocol is used then block containing the addressed word is first brought intothe cache and then the desired word in the cache is over-written with the new information. Mapping Function: Direct Mapping:  It is the simplest technique in which block j of the main memory maps onto block ‘j’ modulo 128 of the cache.  Thus whenever one of the main memory blocks 0,128,256 is loaded in the cache,it is stored in block 0.  Block 1,129,257 are stored in cache block 1 and so on.  The contention may arise when,  When the cache is full  When more than one memory block is mapped onto a given cache block position.  The contention is resolved by allowing the new blocks to overwrite the currently resident block.  Placement of block in the cache is determined from memory address. Fig: Direct Mapped Cache   The memory address is divided into 3 fields.They are, Low Order 4 bit field(word)Selects one of 16 words in a block. 7 bit cache block fieldWhen new block enters cache,7 bit determines the cache position in which this block must be stored. 5 bit Tag fieldThe high order 5 bits of the memory address of the block is stored in 5 tag bits associated with its location in the cache.  As execution proceeds, the high order 5 bits of the address is compared with tag bits associated with that cache location.  If they match,then the desired word is in that block of the cache.  If there is no match,then the block containing the required word must be first read from the main memory and loaded into the cache. Merit:  It is easy to implement. Demerit:  It is not very flexible. Associative Mapping: In this method, the main memory block can be placed into any cache block position. Fig:Associative Mapped Cache.  12 tag bits will identify a memory block when it is resolved in the cache.  The tag bits of an address received from the processor are compared to the tag bits of each block of the cache to see if the desired block is persent.This is called associative mapping.  It gives complete freedom in choosing the cache location.  A new block that has to be brought into the cache has to replace(eject)an existing block if the cache is full.   In this method,the memory has to determine whether a given block is in the cache.  A search of this kind is called an associative Search. Merit:  It is more flexible than direct mapping technique. Demerit:  Its cost is high. Set-Associative Mapping:  It is the combination of direct and associative mapping.  The blocks of the cache are grouped into sets and the mapping allows a block of the main memory to reside in any block of the specified set.  In this case,the cache has two blocks per set,so the memory blocks 0,64,128……..4032 maps into cache set ‘0’ and they can occupy either of the two block position within the set.  6 bit set fieldDetermines which set of cache contains the desired block. 6 bit tag fieldThe tag field of the address is compared to the tags of the two blocks of the set to clock if the desired block is present. Fig: Set-Associative Mapping: No of blocks per set no of set field 2 6 3 5 8 4 128 no set field   The cache which contains 1 block per set is called direct Mapping.  A cache that has ‘k’ blocks per set is called as ‘k-way set associative cache’.  Each block contains a control bit called a valid bit.  The Valid bit indicates that whether the block contains valid data.  The dirty bit indicates that whether the block has been modified during its cache residency. Valid bit=0When power is initially applied to system Valid bit =1When the block is loaded from main memory at first time.  If the main memory block is updated by a source & if the block in the source is already exists in the cache,then the valid bit will be cleared to ‘0’.  If Processor & DMA uses the same copies of data then it is called as the Cache Coherence Problem. Merit:  The Contention problem of direct mapping is solved by having few choices for block placement.  The hardware cost is decreased by reducing the size of associative search. Replacement Algorithm:  In direct mapping, the position of each block is pre-determined and there is no need of replacement strategy.  In associative & set associative method,the block position is not pre- determined;ie..when the cache is full and if new blocks are brought into the cache, then the cache controller must decide which of the old blocks has to be replaced.  Therefore,when a block is to be over-written,it is sensible to over-write the one that has gone the longest time without being referenced.This block is called Least recently Used(LRU) block & the technique is called LRU algorithm.  The cache controller track the references to all blocks with the help of block counter. Eg: Consider 4 blocks/set in set associative cache,  2 bit counter can be used for each block.  When a ‘hit’ occurs,then block counter=0;The counter with values originally lower than the referenced one are incremented by 1 & all others remain unchanged.  When a ‘miss’ occurs & if the set is full,the blocks with the counter value 3 is removed,the new block is put in its place & its counter is set to ‘0’ and other block counters are incremented by 1. Merit:  The performance of LRU algorithm is improved by randomness in deciding which block is to be over-written. PERFORMANCE CONSIDERATION:  Two Key factors in the commercial success are the performance & cost ie the best possible performance at low cost.  A common measure of success is called the Pricel Performance ratio.  Performance depends on how fast the machine instruction are brought to the processor and how fast they are executed.  To achieve parallelism(ie. Both the slow and fast units are accessed in the same manner),interleaving is used. Interleaving: Fig:Consecutive words in a Module VIRTUAL MEMORY:  Techniques that automatically move program and data blocks into the physical main memory when they are required for execution is called the Virtual Memory.  The binary address that the processor issues either for instruction or data are called the virtual / Logical address.  The virtual address is translated into physical address by a combination of hardware and software components.This kind of address translation is done by MMU(Memory Management Unit).  When the desired data are in the main memory ,these data are fetched /accessed immediately.  If the data are not in the main memory,the MMU causes the Operating system to bring the data into memory from the disk.   Transfer of data between disk and main memory is performed using DMA scheme. Fig:Virtual Memory Organisation Address Translation:  In address translation,all programs and data are composed of fixed length units called Pages.  The Page consists of a block of words that occupy contiguous locations in the main memory.  The pages are commonly range from 2K to 16K bytes in length.  The cache bridge speed up the gap between main memory and secondary storage and it is implemented in software techniques.  Each virtual address generated by the processor contains virtual Page number(Low order bit) and offset(High order bit) Virtual Page number+ OffsetSpecifies the location of a particular byte (or word) within a page. Page Table:  It contains the information about the main memory address where the page is stored & the current status of the page. Page Frame:  An area in the main memory that holds one page is called the page frame. Page Table Base Register:   It contains the starting address of the page table. Virtual Page Number+Page Table Base registerGives the address of the corresponding entry in the page table.ie)it gives the starting address of the page if that page currently resides in memory. Control Bits in Page Table:  The Control bits specifies the status of the page while it is in main memory. Function:  The control bit indicates the validity of the page ie)it checks whether the page is actually loaded in the main memory.  It also indicates that whether the page has been modified during its residency in the memory;this information is needed to determine whether the page should be written back to the disk before it is removed from the main memory to make room for another page. Fig:Virtual Memory Address Translation  The Page table information is used by MMU for every read & write access.  The Page table is placed in the main memory but a copy of the small portion of the page table is located within MMU.  This small portion or small cache is called Translation LookAside Buffer(TLB).  This portion consists of the page table enteries that corresponds to the most recently accessed pages and also contains the virtual address of the entry. Fig:Use of Associative Mapped TLB  When the operating system changes the contents of page table ,the control bit in TLB will invalidate the corresponding entry in the TLB.  Given a virtual address,the MMU looks in TLB for the referenced page.  If the page table entry for this page is found in TLB,the physical address is obtained immediately.  If there is a miss in TLB,then the required entry is obtained from the page table in the main memory & TLB is updated.  When a program generates an access request to a page that is not in the main memory ,then Page Fault will occur.  The whole page must be broght from disk into memry before an access can proceed.  When it detects a page fault,the MMU asks the operating system to generate an interrupt.  The operating System suspend the execution of the task that caused the page fault and begin execution of another task whose pages are in main memory because the long delay occurs while page transfer takes place.  When the task resumes,either the interrupted instruction must continue from the point of interruption or the instruction must be restarted.  If a new page is brought from the disk when the main memory is full,it must replace one of the resident pages.In that case,it uses LRU algorithm which removes the least referenced Page.   A modified page has to be written back to the disk before it is removed from the main memory. In that case,write –through protocol is used. MEMORY MANAGEMENT REQUIREMENTS:  Management routines are part of the Operating system.  Assembling the OS routine into virtual address space is called ‘System Space’.  The virtual space in which the user application program reside is called the ‘User Space’.  Each user space has a separate page table.  The MMU uses the page table to determine the address of the table to be used in the translation process.  Hence by changing the contents of this register, the OS can switch from one space to another.  The process has two stages. They are,  User State  Supervisor state. User State:  In this state,the processor executes the user program. Supervisor State:  When the processor executes the operating system routines,the processor will be in supervisor state. Privileged Instruction:  In user state,the machine instructions cannot be executed.Hence a user program is prevented from accessing the page table of other user spaces or system spaces.  The control bits in each entry can be set to control the access privileges granted to each program.  Ie)One program may be allowed to read/write a given page,while the other programs may be given only red access. SECONDARY STORAGE:  The Semi-conductor memories donot provide all the storage capability.  The Secondary storage devices provide larger storage requirements.  Some of the Secondary Storage devices are,  Magnetic Disk  Optical Disk  Magnetic Tapes. Magnetic Disk:  Magnetic Disk system consists o one or more disk mounted on a common spindle.  A thin magnetic film is deposited on each disk, usually on both sides.   The disk are placed in a rotary drive so that the magnetized surfaces move in close proximity to read /write heads.  Each head consists of magnetic yoke & magnetizing coil.  Digital information can be stored on the magnetic film by applying the current pulse of suitable polarity to the magnetizing coil.  Only changes in the magnetic field under the head can be sensed during the Read operation.  Therefore if the binary states 0 & 1 are represented by two opposite states of magnetization, a voltage is induced in the head only at 0-1 and at 1-0 transition in the bit stream.  A consecutive (long string) of 0’s & 1’s are determined by using the clock which is mainly used for synchronization.  Phase Encoding or Manchester Encoding is the technique to combine the clocking information with data.  The Manchester Encoding describes that how the self-clocking scheme is implemented. Fig:Mechanical Structure  The Read/Write heads must be maintained at a very small distance from the moving disk surfaces in order to achieve high bit densities.  When the disk are moving at their steady state, the air pressure develops between the disk surfaces & the head & it forces the head away from the surface.  The flexible spring connection between head and its arm mounting permits the head to fly at the desired distance away from the surface. Wanchester Technology:  Read/Write heads are placed in a sealed, air –filtered enclosure called the Wanchester Technology.   In such units, the read/write heads can operate closure to magnetic track surfaces because the dust particles which are a problem in unsealed assemblies are absent. Merits:  It have a larger capacity for a given physical size.  The data intensity is high because the storage medium is not exposed to contaminating elements.  The read/write heads of a disk system are movable.  The disk system has 3 parts.They are,  Disk Platter(Usually called Disk)  Disk Drive(spins the disk & moves Read/write heads)  Disk Controller(controls the operation of the system.) Fig:Organizing & Accessing the data on disk  Each surface is divided into concentric tracks.  Each track is divided into sectors.  The set of corresponding tracks on all surfaces of a stack of disk form a logical cylinder.  The data are accessed by specifying the surface number,track number and the sector number.  The Read/Write operation start at sector boundaries.  Data bits are stored serially on each track.  Each sector usually contains 512 bytes. Sector header -> contains identification information. It helps to find the desired sector on the selected track. ECC (Error checking code)- used to detect and correct errors.  An unformatted disk has no information on its tracks.  The formatting process divides the disk physically into tracks and sectors and this process may discover some defective sectors on all tracks.  The disk controller keeps a record of such defects.   The disk is divided into logical partitions. They are,  Primary partition  Secondary partition  In the diag, Each track has same number of sectors.  So all tracks have same storage capacity.  Thus the stored information is packed more densely on inner track than on outer track. Access time  There are 2 components involved in the time delay between receiving an address and the beginning of the actual data transfer. They are,  Seek time  Rotational delay / Latency Seek time – Time required to move the read/write head to the proper track. Latency – The amount of time that elapses after the head is positioned over the correct track until the starting position of the addressed sector passes under the read/write head. Seek time + Latency = Disk access time Typical disk One inch disk- weight=1 ounce, size -> comparable to match book Capacity -> 1GB Inch disk has the following parameter Recording surface=20 Tracks=15000 tracks/surface Sectors=400. Each sector stores 512 bytes of data Capacity of formatted disk=20x15000x400x512=60x109 =60GB Seek time=3ms Platter rotation=10000 rev/min Latency=3ms Internet transfer rate=34MB/s Data Buffer / cache  A disk drive that incorporates the required SCSI circuit is referred as SCSI drive.  The SCSI can transfer data at higher rate than the disk tracks.  An efficient method to deal with the possible difference in transfer rate between disk and SCSI bus is accomplished by including a data buffer.  This buffer is a semiconductor memory.  The data buffer can also provide cache mechanism for the disk (ie) when a read request arrives at the disk, then controller first check if the data is available in the cache(buffer).  If the data is available in the cache, it can be accessed and placed on SCSI bus. If it is not available then the data will be retrieved from the disk. Disk Controller  The disk controller acts as interface between disk drive and system bus.  The disk controller uses DMA scheme to transfer data between disk and main memory.   When the OS initiates the transfer by issuing Read/Write request, the controllers register will load the following information. They are,  Main memory address(address of first main memory location of the block of words involved in the transfer)  Disk address(The location of the sector containing the beginning of the desired block of words) (number of words in the block to be transferred). Sector header -> contains identification information. It helps to find the desired sector on the selected track. ECC (Error checking code)- used to detect and correct errors. An unformatted disk has no information on its tracks. The formatting process divides the disk physically into tracks and sectors and this process may discover some defective sectors on all tracks. The disk controller keeps a record of such defects. The disk is divided into logical partitions. They are, Primary partition Secondary partition In the diag, Each track has same number of sectors. So all tracks have same storage capacity. Thus the stored information is packed more densely on inner track than on outer track. Access time There are 2 components involved in the time delay between receiving an address and the beginning of the actual data transfer. They are, Seek time Rotational delay / Latency Seek time – Time required to move the read/write head to the proper track. Latency – The amount of time that elapses after the head is positioned over the correct track until the starting position of the addressed sector passes under the read/write head. Seek time + Latency = Disk access time Typical disk One inch disk- weight=1 ounce, size -> comparable to match book Capacity -> 1GB 3.5 inch disk has the following parameter Recording surface=20 Tracks=15000 tracks/surface Sectors=400. Each sector stores 512 bytes of data Capacity of formatted disk=20x15000x400x512=60x109 =60GB Seek time=3ms Platter rotation=10000 rev/min Latency=3ms Internet transfer rate=34MB/s Data Buffer / cache A disk drive that incorporates the required SCSI circuit is referred as SCSI drive. The SCSI can transfer data at higher rate than the disk tracks. An efficient method to deal with the possible difference in transfer rate between disk and SCSI bus is accomplished by including a data buffer. This buffer is a semiconductor memory. The data buffer can also provide cache mechanism for the disk (ie) when a read request arrives at the disk, then controller first check if the data is available in the cache(buffer). If the data is available in the cache, it can be accessed and placed on SCSI bus. If it is not available then the data will be retrieved from the disk. Disk Controller The disk controller acts as interface between disk drive and system bus. The disk controller uses DMA scheme to transfer data between disk and main memory. When the OS initiates the transfer by issuing Read/Write request, the controllers register will load the following information. They are, Main memory address(address of first main memory location of the block of words involved in the transfer) Disk address(The location of the sector containing the beginning of the desired block of words) (number of words in the block to be transferred). UNIT V MEMORY SYSTEM PART-A 1) Write about the functions of memory organization? 2) Draw the block diagram for memory unit? 3) What re the key characteristics of memories? 4) What are the types of access method? 5) What is meant by memory cycle time? 6) Define transfer rate 7) What are the memory operations? 8) Define throughput 9) What is memory bus? 10) What are the types of memory? 11) Write about RAM 12) What is static RAM? 13) Write short notes on ROM 14) What is error detection and correction code? 15) Explain parity bit? 16) What is hamming error-correcting codes? 17) What is cache memory? 18) What is fully associative mapping? 19) What is block replacement? 20) What is meant by LRU? 21) Explain write strategy? 22) Define bit ratio  23) Explain cache update policies? 24) What is direct mapped cache? 25) What is associative mapping? 26) Explain cache organization? 27) What is cache miss rate? 28) Write about cache directories? 29) What is a write-protect bit? 30) What is multilevel cache? 31) What is virtual memory? 32) What is segmented memory? 33) Write about block access time? 34) What is page mode? 35) Write about I/O-address strobe (RA )? 36) What is column-address strobe (CA )? 37) What is access time myth? 38) How can hits or misses myth? 39) How are memory blocks mapped into cache lines? 40) What is secondary storages? PART – B 1) Explain the memory organization? 2) Write about the following a. Memory bus b. Byte storage methods 3) Write about memory hierarchy 4) Explain semi conductor RAM? 5) Write about semi conductor ROM? 6) Explain error detection and correction codes?  UNIT V I/O ORGANIZATION  Accessing I/O devices  Programmed I/O  Interrupts  Direct memory access  Buses  Interface Circuits  Standard I/O interfaces (PCI, SCSI, and USB)  I/O Devices and processors ACCESSING I/O DEVICES  A simple arrangement to connect I/O devices to a computer is to use a single bus structure. It consists of three sets of lines to carry  Address  Data  Control Signals.  When the processor places a particular address on address lines, the devices that recognize this address responds to the command issued on the control lines.  The processor request either a read or write operation and the requested data are transferred over the data lines.  When I/O devices & memory share the same address space, the arrangement is called memory mapped I/O. Single Bus Structure Processor Memory Bus I/O device 1..… I/O device n Eg:- Move DATAIN, Ro  Reads the data from DATAIN then into processor register Ro. Move Ro, DATAOUT  Send the contents of register Ro to location DATAOUT. DATAIN  Input buffer associated with keyboard. DATAOUT  Output data buffer of a display unit / printer. Fig: I/O Interface for an Input Device Address line Data line Control line Address Control Data & status I/O interface decoder circuits register Input device. Address Decoder:  It enables the device to recognize its address when the address appears on address lines. Data register  It holds the data being transferred to or from the processor. Status register  It contains infn/. Relevant to the operation of the I/O devices.  The address decoder, data & status registers and the control circuitry required to co-ordinate I/O transfers constitute the device’s I/F circuit.  For an input device, SIN status flag in used SIN = 1, when a character is entered at the keyboard.  For an output device, SOUT status flag is used SIN = 0, once the char is read by processor. Eg DIR Q  Interrupt Request for display. KIR Q Interrupt Request for keyboard. KEN  keyboard enable. DEN  Display Enable. SIN, SOUT  status flags. The data from the keyboard are made available in the DATAIN register & the data sent to the display are stored in DATAOUT register. Program: WAIT K Move # Line, Ro Test Bit #0, STATUS Branch = 0 WAIT K Move DATAIN, R1 WAIT D Test Bit #1, STATUS Branch = 0 WAIT D Move R1, DATAOUT Move R1, (Ro)+ Compare #OD, R1 Branch = 0 WAIT K Move #DOA, DATAOUT Call PROCESS EXPLANATION:  This program, reads a line of characters from the keyboard & stores it in a memory buffer starting at locations LINE.  Then it calls the subroutine “PROCESS” to process the input line.  As each character is read, it is echoed back to the display.  Register Ro is used as a updated using Auto – increment mode so that successive characters are stored in successive memory location.  Each character is checked to see if there is carriage return (CR), char, which has the ASCII code 0D(hex).  If it is, a line feed character (on) is sent to more the cursor one line down on the display & subroutine PROCESS is called. Otherwise, the program loops back to wait for another character from the keyboard. PROGRAM CONTROLLED I/O Here the processor repeatedly checks a status flag to achieve the required synchronization between Processor & I/O device.(ie) the processor polls the device. There are 2 mechanisms to handle I/o operations. They are,  Interrupt, -  DMA (Synchronization is achieved by having I/O device send special over the bus where is ready for data transfer operation) DMA:  Synchronization is achieved by having I/O device send special over the bus where is ready for data transfer operation)  It is a technique used for high speed I/O device.  Here, the input device transfer data directly to or from the memory without continuous involvement by the processor. INTERRUPTS  When a program enters a wait loop, it will repeatedly check the device status. During this period, the processor will not perform any function.  The Interrupt request line will send a hardware signal called the interrupt signal to the processor.  On receiving this signal, the processor will perform the useful function during the waiting period.  The routine executed in response to an interrupt request is called Interrupt Service Routine.  The interrupt resembles the subroutine calls. Fig:Transfer of control through the use of interrupts  The processor first completes the execution of instruction i Then it loads the PC(Program Counter) with the address of the first instruction of the ISR.  After the execution of ISR, the processor has to come back to instruction i + 1.  Therefore, when an interrupt occurs, the current contents of PC which point to i +1 is put in temporary storage in a known location.  A return from interrupt instruction at the end of ISR reloads the PC from that temporary storage location, causing the execution to resume at instruction i+1.  When the processor is handling the interrupts, it must inform the device that its request has been recognized so that it remove its interrupt requests signal.  This may be accomplished by a special control signal called the interrupt acknowledge signal.  The task of saving and restoring the information can be done automatically by the processor.  The processor saves only the contents of program counter & status register (ie) it saves only the minimal amount of information to maintain the integrity of the program execution.   Saving registers also increases the delay between the time an interrupt request is received and the start of the execution of the ISR. This delay is called the Interrupt Latency.  Generally, the long interrupt latency in unacceptable.  The concept of interrupts is used in Operating System and in Control Applications, where processing of certain routines must be accurately timed relative to external events. This application is also called as real-time processing. Interrupt Hardware: Fig:An equivalent circuit for an open drain bus used to implement a common interrupt request line  A single interrupt request line may be used to serve ‘n’ devices. All devices are connected to the line via switches to ground.  To request an interrupt, a device closes its associated switch, the voltage on INTR line drops to 0(zero).  If all the interrupt request signals (INTR1 to INTRn) are inactive, all switches are open and the voltage on INTR line is equal to Vdd.  When a device requests an interrupts, the value of INTR is the logical OR of the requests from individual devices. (ie) INTR = INTR1+…………+INTRn INTR  It is used to name the INTR signal on common line it is active in the low voltage state.  Open collector (bipolar ckt) or Open drain (MOS circuits) is used to drive INTR line.  The Output of the Open collector (or) Open drain control is equal to a switch to the ground that is open when gates input is in ‘0’ state and closed when the gates input is in ‘1’ state.  Resistor ‘R’ is called a pull-up resistor because it pulls the line voltage upto the high voltage state when the switches are open. Enabling and Disabling Interrupts:  The arrival of an interrupt request from an external device causes the processor to suspend the execution of one program & start the execution of another because the interrupt may alter the sequence of events to be executed.  INTR is active during the execution of Interrupt Service Routine.  There are 3 mechanisms to solve the problem of infinite loop which occurs due to successive interruptions of active INTR signals.  The following are the typical scenario.  The device raises an interrupt request.  The processor interrupts the program currently being executed.  Interrupts are disabled by changing the control bits is PS (Processor Status register)  The device is informed that its request has been recognized & in response, it deactivates the INTR signal.  The actions are enabled & execution of the interrupted program is resumed. Edge-triggered: The processor has a special interrupt request line for which the interrupt handling circuit responds only to the leading edge of the signal. Such a line said to be edge- triggered. Handling Multiple Devices:  When several devices requests interrupt at the same time, it raises some questions. They are.  How can the processor recognize the device requesting an interrupt?  Given that the different devices are likely to require different ISR, how can the processor obtain the starting address of the appropriate routines in each case?  Should a device be allowed to interrupt the processor while another interrupt is being serviced?  How should two or more simultaneous interrupt requests be handled? Polling Scheme:  If two devices have activated the interrupt request line, the ISR for the selected device (first device) will be completed & then the second request can be serviced.  The simplest way to identify the interrupting device is to have the ISR polls all the encountered with the IRQ bit set is the device to be serviced  IRQ (Interrupt Request) -> when a device raises an interrupt requests, the status register IRQ is set to 1. Merit:  It is easy to implement. Demerit: The time spent for interrogating the IRQ bits of all the devices that may not be requesting any service. Vectored Interrupt:  Here the device requesting an interrupt may identify itself to the processor by sending a special code over the bus & then the processor start executing the ISR.  The code supplied by the processor indicates the starting address of the ISR for the device.  The code length ranges from 4 to 8 bits.  The location pointed to by the interrupting device is used to store the staring address to ISR.  The processor reads this address, called the interrupt vector & loads into PC.  The interrupt vector also includes a new value for the Processor Status Register.  When the processor is ready to receive the interrupt vector code, it activate the interrupt acknowledge (INTA) line. Interrupt Nesting: Multiple Priority Scheme:  In multiple level priority scheme, we assign a priority level to the processor that can be changed under program control.  The priority level of the processor is the priority of the program that is currently being executed.  The processor accepts interrupts only from devices that have priorities higher than its own.  At the time the execution of an ISR for some device is started, the priority of the processor is raised to that of the device.  The action disables interrupts from devices at the same level of priority or lower. Privileged Instruction:  The processor priority is usually encoded in a few bits of the Processor Status word. It can also be changed by program instruction & then it is write into PS. These instructions are called privileged instruction. This can be executed only when the processor is in supervisor mode.  The processor is in supervisor mode only when executing OS routines.  It switches to the user mode before beginning to execute application program. Privileged Exception:  User program cannot accidently or intentionally change the priority of the processor & disrupts the system operation.   An attempt to execute a privileged instruction while in user mode, leads to a special type of interrupt called the privileged exception. Fig: Implementation of Interrupt Priority using individual Interrupt request acknowledge lines  Each of the interrupt request line is assigned a different priority level.  Interrupt request received over these lines are sent to a priority arbitration circuit in the processor.  A request is accepted only if it has a higher priority level than that currently assigned to the processor, Simultaneous Requests: Daisy Chain:  The interrupt request line INTR is common to all devices. The interrupt acknowledge line INTA is connected in a daisy chain fashion such that INTA signal propagates serially through the devices.  When several devices raise an interrupt request, the INTR is activated & the processor responds by setting INTA line to 1. this signal is received by device.   Device1 passes the signal on to device2 only if it does not require any service.  If devices1 has a pending request for interrupt blocks that INTA signal & proceeds to put its identification code on the data lines.  Therefore, the device that is electrically closest to the processor has the highest priority. Merits: It requires fewer wires than the individual connections. Arrangement of Priority Groups:  Here the devices are organized in groups & each group is connected at a different priority level.  Within a group, devices are connected in a daisy chain. Controlling Device Requests: KEN  Keyboard Interrupt Enable DEN  Display Interrupt Enable KIRQ / DIRQ  Keyboard / Display unit requesting an interrupt.  There are two mechanism for controlling interrupt requests.  At the devices end, an interrupt enable bit in a control register determines whether the device is allowed to generate an interrupt requests.  At the processor end, either an interrupt enable bit in the PS (Processor Status) or a priority structure determines whether a given interrupt requests will be accepted. Initiating the Interrupt Process:  Load the starting address of ISR in location INTVEC (vectored interrupt).  Load the address LINE in a memory location PNTR. The ISR will use this location as a pointer to store the i/p characters in the memory.  Enable the keyboard interrupts by setting bit 2 in register CONTROL to 1.  Enable interrupts in the processor by setting to 1, the IE bit in the processor status register PS. Exception of ISR:  Read the input characters from the keyboard input data register. This will cause the interface circuits to remove its interrupt requests.  Store the characters in a memory location pointed to by PNTR & increment PNTR.  When the end of line is reached, disable keyboard interrupt & inform program main.  Return from interrupt. Exceptions:  An interrupt is an event that causes the execution of one program to be suspended and the execution of another program to begin.  The Exc