Intel 80286/80386 Microprocessor (Protected Mode) - COEN 3212

Intel 80286/80386 Microprocessor (Protected Mode and Flat Mode Memory Systems) COEN 3212 – Microprocessors (Lecture) Lesson 3 Instructor: Engr. Ricrey E. Marquez, CpE, MSCS  Lecture Objectives Upon completion of this lecture, stud...

Intel 80286/80386 Microprocessor (Protected Mode and Flat Mode Memory Systems) COEN 3212 – Microprocessors (Lecture) Lesson 3 Instructor: Engr. Ricrey E. Marquez, CpE, MSCS  Lecture Objectives Upon completion of this lecture, student will be able:  To lists the registers of the 80386,  To describe the additional features implemented on the 80386,  To state the purpose of designing two modes: real and protected into the 80286 or 80386,  To describe how memory is accessed using protected mode memory- addressing techniques,  To demonstrate the detailed operations of the memory segmentation mechanism, and  To demonstrate the operation of the memory paging mechanism Introduction to the 80386 Microprocessor Part I 386 Block Diagram 386 Registers Data Bus Selection Example  New Features The 80386 microprocessor features:  multitasking,  memory management,  virtual memory with or without paging, and  large memory system  1 - Multitasking Ability to execute more than one task at the same time (a task being a program) In multitasking, only one CPU is involved, but it switches from one program to another so quickly that it gives the appearance of executing all of the programs at the same time.  2 - Virtual Memory  Use to enlarge the address space which the set of addresses a program can utilize.  Computer could execute such a program by copying into main memory those portions of the program needed at any given point during execution.  Additional Signal Pins Some newly introduced signal pins: BE0-BE3 (Bank Enable) - signals use to select the access of a byte, word, or double word of data. ADS (Address Data Strobe) - signal that is active whenever the 80386 has issued a valid memory or I/O address. BS16 (Bus Size 16) - selects either a 32-bit data bus (1) or a 16-bit data bus (0). NA (Next Address) - causes the 80386 to output the address of the next instruction or data in the current bus cycle and it is used for pipelining the address.  Pipelining In 80386, a pipeline is used to handle memory accesses so that the memory has additional time to access data. Pipeline is realized with the help of the interleaved memory system.  3 - Memory System 80386DX has a physical memory system of 4GB in size (4GB = 232, k = 32 address lines (A31 – A0)) If virtual addressing is used, 64TB (1T = 240) are mapped into the 4G bytes of physical space by the memory management unit and descriptors Memory is divided into four (4) 8-bit wide memory called memory banks or banks. 80386DX can transfer a 32-bit datum in a single memory cycle, whereas the 8088 requires 4 cycles to accomplish the same transfer and the 80286 and 80386SX can transfer a datum in 2 cycles. 80386DX does not contain address connections A0 and A1 due to these have been encoded as the bank enable signals.  4 - Memory Interfacing There are three (3) memory interfacing techniques in 80386 which allows to interface memory devices which are slower than required without degrading the performance of the microprocessor such as:  Interleaved memory,  Caching, and  Pipelining  Real vs. Protected Modes Real Mode operation allows the microprocessor to address only the first 1MB of memory such as 8086 or 8088  Memory space -- First 1MB of memory  Physical address -- Segment Address (SA):Offset Address oSegment address -- beginning address of any 64KB memory segment (CS, DS, SS, ES) oOffset address -- any location within the 64KB memory segment (IP, SP, BP, SI, DI, BX or 16/8-bit data)  Real vs. Protected Modes Calculation of real mode memory addressing (PA = SA x 10 + OA)  Real vs. Protected Modes Protected Mode operation allows the access to data and programs located above the first 1MB of memory.  Intel 80286 and above, operates in either the real or protected mode o Memory space = above the first 1MB of memory o Physical address = Selector Address : Offset Address  About the Modes DOS (Disk Operating System) operating systems operates in real mode Windows operating systems (GUI) operates in Protected mode  Processor enters real mode first, then switch from real mode to protected mode which: o build a Global Descriptor Table (GDT), o enables protected mode in the CPU Machine Status Word (MSW)  SMM -- other Mode System Management Mode (SMM)  First introduced by Intel in October 1990 with the Intel 386SL as a way for the CPU to execute code from a separate area of memory known as SMRAM. SMRAM (System Management RAM) is only accessible by the processor and not the operating system or other programs  CPU mode that allows the processor to work transparently with the operating system and other programs to power up or down any hardware devices allowing the computer to better conserve power when idle. source: http://www.computerhope.com/jargon/s/smm.htm (18 June 2015) Protected-Mode Memory Addressing  Protected-Mode Memory Addressing In protected mode, segment register contains a selector that selects a descriptor from a descriptor table instead of a segment address Descriptor describes the memory segment's addresses such as: Base (location), Limit (length), and Access rights Protected-Mode Memory Addressing Segmentation Mechanism Protected-Mode Memory Addressing Paging Mechanism  Selectors In protected mode, segment register contains a:  Selector field -- 13-bit, o Selects one of 8192 descriptors from one of two tables of descriptors (global or local DT)  Table selector (TI) field -- 1-bit o Selects either the global descriptor table (0) or local descriptor table (1)  Requested Privilege Level (RPL) field – 2-bits o Requests the access privilege level of a memory segment (00 – highest, 11 – lowest) Selectors  Selectors descriptor 8191 Select one out of the descriptor 8190 8192 descriptors descriptor 8189 How TI bit selects descriptor (local or global) descriptor 2 descriptor 1 descriptor 0  Descriptors Descriptor describes the memory segment's base (location), limit (length), and access rights of the segment of memory Two (2) types of descriptor tables:  Global Descriptors -- contain segment definitions that apply to all programs (a.k.a. System Descriptor)  Local Descriptors -- contain segment definitions that unique to an application (a.k.a Application Descriptor) Each descriptor table contains 8192 descriptors Descriptor describes a memory segment, this allows up to 16,384 memory segments to be described for each application Memory segment can be up to 4GB in length, this means that an application could have access to (4G x 16,384) bytes of memory or 64TB 80286 through Core2 64-bit descriptors  Descriptors (Base & Limit) Intel 80286 Intel 80386 – Pentium 4  Base (24-bit) = 224 =  Base (32-bit) = 232 = 16MB (protected mode) 4GB (protected mode)  Limit (16-bit) = 216 =  Limit (20-bit) = 220 = 64KB (real mode) 1MB (real mode)  Descriptors (Base & Limit) Each descriptor is 8 bytes in length Base address -- portion of the descriptor indicates the starting location of the memory segment Limit address -- contains the last offset address found in a segment Note: paragraph boundary limitation is removed in protected mode  Descriptors (Control Bits)  G (Granularity) bit – selects memory space for real mode (0), protected mode (1)  D (Data offset) bit -- indicates how the 80386 through the Core2 instructions access register and memory data in the protected or real mode: 16-bit instruction/offset addresses (0) -- aka. DOS mode, 32-bit offset instruction/addresses (1) – aka. Win32 mode  AV (Availability of segment) bit – used by some operating systems to indicate that the segment is available (1) or not available (0)  Descriptors (Control Bits) The value of the limit will be multiplied by 4K bytes if the granularity bit (G bit) is set to be 1. Append FFF to the right  Descriptors In 64-bit protected operation, the code segment register is still used to select a section of code from the memory, and notice that the 64-bit descriptor only contains an access rights byte and the control bits but no limit or base address For 64-bit, no segment or limit in the descriptor and the base address of the segment, although not placed in the descriptor, is 00 0000 0000h which means that all code segments start at address zero operation Also, there are no limit checks for a 64-bit code segment  Descriptors (Access Right) Access Rights byte allows complete control over the segment by describing how the segment functions in the system  Null Descriptors Descriptor 0 is called the null descriptor, and may not be used for accessing memory Fig 2.9 shows how the segment register, containing a selector, chooses a descriptor from the global descriptor table  Null Descriptors 0000000000001 0 00 GDT  Improve the Performance with Program-Invisible Registers The global and local descriptor tables are placed in the memory system In 80286 and above contain program-invisible registers to access and specify the address of these tables (see Figure 2- 10) Program invisible registers are registers that control the microprocessor when operated in the protected mode, and not directly addressed by software Program-Invisible Registers TR: task register IDTR: interrupt descriptor table register Copy content of descriptor n  Copy content of descriptor m TR: task register IDTR: interrupt descriptor table register  Program-Invisible Registers Each of the segment registers contains a program-invisible portion used in the protected mode Program-invisible portion of the segment register is loaded with the base address, limit address, and access rights each time the number in the segment register is changed, which allows the microprocessor to access a memory segment repeatedly without referring back to the descriptor table for each access  Program-Invisible Registers GDTR (Global Descriptor Table Register) or IDTR (Interrupt Descriptor Table Register) contain the base address of the descriptor table and its limit.  When protected mode operation is desired, the address of the global descriptor table and its limit are loaded into the GDTR  Before using protected mode, the interrupt descriptor table and the IDTR must be initialized  Program-Invisible Registers Location of the local descriptor table is selected from the global descriptor table  One of the global descriptors is set up to address the local descriptor table  To access the local descriptor table, the LDTR (Local Descriptor Table Register) is loaded with a selector, just as a segment register is loaded with a selector  Program-Invisible Registers Task Register (TR) holds a selector that accesses a descriptor that defines a task Task switching method allows multitasking systems to switch from one task to another in a simple and orderly fashion Memory Paging Part II  Paging Paging performs logical to physical address translation Paging allows any program and data relocatable (even more powerful than the segment and offset addressing scheme)  Paging Memory Paging mechanism located within the 80386 and above allows any physical memory location to be assigned to any linear address. Linear Address is defined as the address generated by a program With the memory paging unit, the linear address is invisibly translated into any physical address  Paging How paging works in Intel’s CPU: 1. The memory space is divided into a number of pages 2. Each page is of size 4 KB 3. Any data or program is divided into pages of size 4KB each and these pages are individually loaded into the memory space 4. Any data or program byte is associated with a logical address  Paging 5. Dir, and Page or Table -- tells which page the requested data is in 6. Offset or Frame -- tells which byte in the specified page is the requested data  The ith entry tells the starting address of the ith page table A more detailed example managed by the page directory. The jth entry tells the starting address of the jth page managed by Given linear address the selected page table. =i(2) =j(1) =k(0) page 2:1 Internal control register (i+1)th page table Real physical address page 2:0 The base address tells the starting address of ith page table the page directory.  Example: Q. How to get the starting address of Logical address = 00801000H a page directory/page table/page?  Dir=2, Page=1, Offset=0 A. Append ‘000’ to the face value of address to get the real value.  Physical address = 00080000H Append 000H 80000H Given linear address =i(2) =j(1) =k(0) 20000H+1x4= 20004H Internal control register Real physical address = 00080000H +0H 00080H Append 000H 00010H 00020H 10000H+2x4= Append 000H 10008H 20000H 10000H  Paging Linear address, as it is generated by the software, is broken into three sections that are used to access the page directory entry, page table entry, and page offset address.  Page of memory (Offset) -- contains 4096 (4KB) of memory  Page directory (Dir) -- contains entries that locate the starting addresses of up to 1024 (1KB) page tables  Page table (Page) contains 1024 entries that locate the starting addresses of 1024 (1KB) pages P.A[dir][table][offset] = 1KB x 1KB x 4KB = 4GB  Paging Registers Paging unit is controlled by the contents of the microprocessor's control registers PG = 1: using the paging mechanism (protected) PG = 0: linear address = physical address (real) Paging Registers  Paging Issue Page directory plus the page tables could be a big storage overhead to the memory system. Ex. A paged memory system of 4G bytes must allocate 4K bytes of memory for the page directory and 4K x 1024 bytes for the 1024 page tables.  Solution to Paging Issue Time overhead – re-paging a 4KB section of memory requires access to the page directory and a page table, both located in memory Intel has incorporated a cache called TLB (translation look-aside buffer) to hold the most recent page translation addresses to speed up the translation  Flat Mode Memory Memory system in a Pentium-based computer (Pentium 4 or Core2) that uses the 64-bit extensions uses a flat mode memory system Flat mode memory system is one in which there is no segmentation -- address of the first byte in the memory is at 00 0000 0000h and the last location is at FF FFFF FFFFh (address is 40-bits) CS (Code Segment) segment register is used to select a descriptor from the descriptor table that defines the access rights of only a code segment Segment register still selects the privilege level of the software Flat model does not select the memory address of a segment using the base and limit in the descriptor (see Figure 2-6) Real mode system is not available if the processor operates in the 64-bit mode. but protection and paging are allowed  Flat Mode Memory In 64-bit mode the actual address is not modified by the descriptor as in 32-bit protected mode Offset address is the actual physical address in 64-bit mode (see Figure 2-15) Flat mode form of addressing is much easier to understand, but offers little protection to the system, through the hardware, as did the protected mode system  References  Brey, Barry B. (2009). The Intel microprocessors 8086/8088, 80186/80188, 80286, 80386, 80486, Pentium, Pentium Pro processor, Pentium II, Pentium III, Pentium 4, and Core2 with 64-bit extensions: architecture, programming, and interfacing. 8th Ed. Upper Saddle River, New Jersey Columbus, Ohio: Pearson Prentice Hall  Computer Hope (2015). SMM Definition. Retrieve from http://www.computerhope.com/jargon/s/smm.htm