8086 Microprocessor Architecture PDF

Chapter two 8086 Microprocessor Architecture  Issues Review of the Basic Comp. Arch The 8086 internal architecture 8086 special features Pin layout and signal descriptions Physical memory organization General bus operations I/O addressing Special processor activities ...

Chapter two 8086 Microprocessor Architecture  Issues Review of the Basic Comp. Arch The 8086 internal architecture 8086 special features Pin layout and signal descriptions Physical memory organization General bus operations I/O addressing Special processor activities  The Basic Arch. The simplest microprocessor at least contains: Program and data address bus (separate or unified) Address decoder and generator Instruction decoder Arithmetic and Logic Unit (ALU) A set of basic registers Program Counter (PC) Instruction Register (IR) Accumulator or Working Register (AC) Flag register (FR) Input and output registers General purpose (temporary)registers (GPRs) (to hold data operands and intermediate results) The Basic Arch. graphically  Overview of 8086  The 8086 is a 16-bit microprocessor  Has a 16-bit data bus, R/W data 16/8 bit at a time  Has a 20-bit address bus, so it can access..byte wide  Can generate 16-bit I/O address, it can access I/O ports  Has a multiplexed address and data bus,  Reduce the no. of pins required  But slow dawn the transfer rate  Requires one phase clock with a 33% duty cycles (minimum) to provide optimized internal  Cont’d… The 8086 can perform arithmetic and logical operations on bit, byte, word and blocks The 8086 is designed to operate in two modes o The minimum and (single processor microcomputers) o The maximum mode (multi processor appl) The 8086 supports multi-programming… time multiplexed It can fetch up to 6 instructions bytes from memory … to speed up instruction execution (pipelining) Provides powerful instruction sets with addressing modes like; o Register, Immediate, Direct, Indirect through index or base, Relative, and implied addressing mode Architecture of the 8086  Execution Unit (EU) The EU of 8086 tells the BIU where to fetch inst. or data from, decodes instructions & executes instruction EU contains; o control circuitry which directs the internal operations o decoder w/c translates the instructions fetched from memory into a series of actions o ALU w/c can add, subtract, AND, OR, XOR, increment, complement and shift binary numbers o Registers The Execution Unit…cntd Flag Register The Execution Unit…cntd Carry Flag (C) This flag is set when there is a carry out of MSB in case of addition or a borrow in case of subtraction. Zero Flag (Z) This flag is set when the result of an arithmetic operation is zero. Sign Flag (S) This flag is set when the result an arithmetic operation is negative. For signed computations, the sign flag equals the MSB of the result. The Execution Unit…cntd Parity Flag (P) This flag is set when the lower byte of the result contains even number of 1s. Overflow Flag (O) This flag is set, if an overflow occurs, i.e. if the result of a signed operation is large enough to be accommodated in a destination register. Direction Flag (D) This is used by string manipulation instructions. If this flag bit is '0’ the string is processed beginning from the lowest to the highest address (auto-incrementing mode). Otherwise, the string is processed from the highest to the lowest address (auto-decrementing mode). The Execution Unit…cntd Interrupt Flag (I) If this flag is set, the maskable interrupts are acknowledged by the CPU, otherwise they are ignored. Trap Flag (T) If this flag is set, the processor enters the single step execution mode. In other words, a trap interrupt is generated after execution of each instruction. The processor executes the current instruction and the control is transferred to the Trap interrupt service routine. Auxiliary Cary Flag (AC) This is set if there is a carry from the lowest nibble, i.e. bit three, during addition or borrow for the lowest nibble, i.e. bit three, during subtraction. exercises Give the content of the flag register after the execution of the following addition 0110 0101 1101 0001 + 0010 0011 0101 1001 1000 1001 0010 1010 The Execution Unit…cntd General Purpose Registers The EU has 8 GP registers AH, AL, BH, BL, CH, CL, DH, DL Certain pairs of these general-purpose registers can be used together to store 16-bit data words. The acceptable register pairs are AH-AL, BH-BL, CH-CL, and DH-DL. The AH-AL pair is referred to as the AX register, the BH-BL pair is referred to as the BX register, the CH-CL pair is referred to as the CX register, and the DH-DL pair is referred to as the DX register. The Execution Unit…cntd General purpose register AX - the Accumulator BX - the Base Register CX - the Count Register DX - the Data Register  Normally used for storing temporary results  Each of the registers is 16 bits wide (AX, BX, CX, DX)  Can be accessed as either 16 or 8 bits AX, AH, AL AX  Accumulator Register  Preferred register to use in arithmetic, logic and data transfer instructions because it generates the shortest Machine Language Code  Must be used in multiplication and division operations  Must also be used in I/O operations BX  Base Register  Also serves as an address register CX  Count register  Used as a loop counter  Used in shift and rotate operations DX  Data register  Used in multiplication and division  Also used in I/O operations  The Execution Unit…cntd Pointer and Index Registers  All 16 bits wide, L/H bytes are not accessible  Used as memory pointers Example: MOV AH, [SI] Move the byte stored in memory location whose address is contained in register SI to register AH  The Bus Interface Unit(BIU)  The BIU is the 8086’s interface to the external world  It provides a full bidirectional data bus and a 20-bit address bus  The BIU is responsible for performing all external operations like;  Sends the address of the memory or IO  Fetches instruction from memory  Reads data from ports/memory  Writes data to ports/memory  Helps in instruction queuing  Provides address relocation The Bus Interface Unit(BIU)...cntd Instruction Queue To speed up program execution, the BIU fetches six instruction bytes ahead of time from memory These prefetched instruction bytes are held for the execution unit in a group of register called Queue It is possible to fetch next instruction while the current instruction is in execution … Pipelining Queue operates on the principle of FIFO The Bus Interface Unit(BIU)...cntd Segment Registers The four segment registers are the code segment (CS) register, the data segment (DS) register, the stack segment (SS) register, and the extra segment (ES) register. A segment register is used to hold the upper 16 bits of the starting address for each of the segments. The four segments can be separated or for small programs, which do not need all 64 Kbytes in each segment, they can overlap. The Bus Interface Unit(BIU)...cntd Physical address generation They're two types of address generation Real Mode (8086 can only operate in this mode) Allows the μP to address the first 1MB of memory only The first 1MB of memory is called real or physical memory Protected Mode (80286 , 80386, …) Uses the segment register contents (called selector) to access a descriptor from the descriptor table. The descriptor describes the memory segment’s location, length and access rights.  The Bus Interface Unit(BIU)...cntd Memory Segmentation Memory Organization linear Segmented addressing addressing the whole 20-bit the available memory address is memory is divided provided to the into chunks called processor in a segments that are single linear array 16-bit addressable  The Bus Interface Unit(BIU)...cntd Memory Segmentation & segment Registers The 8086 have four possible active segments  The Bus Interface Unit(BIU)...cntd Memory Segmentation Physical Address FFFFFH Highest address 7FFFFH Top of Extra Segment 64 K ES 70000H Extra segment base ES=7000H 5FFFFH Top of Stack segment 64 K SS 50000H Stack segment base SS=5000H 4489FH Top of Code segment 64 K CS 348A0H Code segment base CS=348AH 2FFFFH Top of Data segment 64 K DS 20000H Data segment base DS=2000H 00000H  The Bus Interface Unit(BIU)...cntd Rules for Memory Segmentation The 4 segments can overlap for small programs The segment can start at any memory address w/c is divisible by 16 Advantages of MS Allows memory addressing capacity to be 1Mbyte Allows a portion of programs to be more than 64KB long by using more than one CS, DS, SS & ES Facilitates use of separate memory areas for program, data & stack Permits a program/its data to be put in d/t areas of memory, each time the program is executed  The Bus Interface Unit(BIU)...cntd Rules for physical address The 8086 addresses a segmented memory. The complete physical address, which is 20-bits long, is generated using segment and offset registers, each 16-bits long. The content of a segment register is shifted left bit-wise four times and to this result, content of an offset register is added, to produce a 20-bit physical address.  Example  For example, if the segment address is 1005H and the offset is 5555H, then the physical address is calculated as below. Solution:  Segment address --------- 1005H  Offset address------------- 5555H  Segment address--------- 1005H --------- 0001 0000 0000 0101  Shifted by 4 bit positions---------- 0001 0000 0000 0101 0000  Offset address--------------------- + 0101 0101 0101 0101  Physical address --------------------- 0001 0101 0101 1010 0101  1 5 5 A 5H  The Bus Interface Unit(BIU)...cntd Instruction Pointer The IP contains the distance or offset from the base address in Code Segment (CS) to the next instruction byte to be fetched. The 16-bit offset in IP is added to the 16-bit segment base address in CS to produce the 20-bit physical address. Location of the next instruction in memory is, therefore address of next ins. = (CS