ELE 3230 Microprocessors and Computer Systems Programming Model PDF

ELE 3230 Microprocessors and Computer Systems Chapter 7 Programming Model (Brey 2-1, 2-2; Hall pp27-35) ELE 3230 - Chatper 7 1  Microprocessor Programming Model z The programming model (software) summarizes all the information needed for programming the...

ELE 3230 Microprocessors and Computer Systems Chapter 7 Programming Model (Brey 2-1, 2-2; Hall pp27-35) ELE 3230 - Chatper 7 1  Microprocessor Programming Model z The programming model (software) summarizes all the information needed for programming the microprocessor. z Example: 8088 Programming Model 15 8 7 0 15 0 AX AH AL Accumulator SP Stack pointer 2 Pointer 4 Data BX BH BL Base BP Base pointer Register Register CX CH CL Count SI Source index 2 Index DX DH DL Data DI Destination index Register IP Instruction pointer 15 0 4 CS Code segment 15 0 1 Flag Segment DS Data segment Flags Register Register SS Stack segment ES Extra segment ELE 3230 - Chatper 7 2 Programming Model for Intel 80386 8-bit Names 32-bit 16-bit Name Names Names EAX AH AX AL Accumulator EBX BH BX BL Base index ECX CH CX CL Count EDX DH DX DL Data ESP SP Stack pointer EBP BP Base pointer EDI DI Destination index ESI SI Source index 32-bits 16-bits EIP IP Instruction pointer EFLAGS FLAGS Flags CS Code DS Data ES Extra SS Stack : Only available in FS 80386 or higher GS ELE 3230 - Chatper 7 3  Intel 80X86 Registers z Register in the 8088/8086 and 80286 may be grouped into 4 sets: (i) General registers (AX, BX, CX, DX) (ii) Pointer and index registers (SP, BP, SI, DI, IP) (iii) Flag Register (FLAGS) (iv) Segment Registers (CS, DS, SS, ES) z The 80386, 80486 and Pentium microprocessors have 32-bit registers and the 16-bit registers of the 8088 form a subset: ELE 3230 - Chatper 7 5  Software model of the 8088 microprocessor FFFFF16 The segment registers 8088 MPU in MPU store the initial IP Code segment (64 K bytes) address information of CS the corresponding DS memory segments. SS Data segment (64 K bytes) ES AH AL AX BH BL BX Stack segment CH CL CX (64 K bytes) DH DL DX SP BP Extra segment SI (64 K bytes) DI SR 0000016 SR: status (flag) register ELE 3230 - Chatper 7 6  General Data Registers (AX, BX, CX, DX) z AX, BX, CX, DX are 16-bit registers. z The 16-bit registers in this set may be split into two. 15 87 0 AX AH AL accumulator BX BH BL base CX CH CL count DX DH DL data z AX (accumulator) stores the result of many arithmetic and logic instructions. z BX (Base) stores the base (offset) address data in memory and the base address of a table of data referenced by the translate (XLAT) instruction. z CX stores the count for certain instructions (eg. Counter in the LOOP instruction, the shift count for shift instructions). z DX holds the most significant part of the result of a 16-bit multiplication, the most significant part of a dividend before division and I/O port number for a variable I/O instruction. ELE 3230 - Chatper 7 7  Pointer and Index Registers 15 0 SP Stack pointer BP Base pointer DI Destination Index SI Source Index IP Instruction Pointer z This set of registers usually store offset addresses of memory. IP usually stores the offset address of the next instruction in memory, SP, BP, DI and SI usually store the offset address of data in memory. z SP, BP, DI and SI may also be used for general purposes. z SP (Stack Pointer) is used in the PUSH and POP instructions for operations on a LIFO (Last-In, First-Out) stack. z BP(Base Pointer) is often used in addressing an array of data in the stack memory. z DI (Destination Index) usually stores the indirect destination address of data from an instruction. z SI (Source Index) is used when indirectly addressing source data in certain string instructions. ELE 3230 - Chatper 7 8  8086 Flag Register Format BIT 8085 COMPATIBLE FLAGS 15141312 11 10 9 8 7 6 5 4 3 2 1 0 U U U U OF DFIF TF SF ZF U AF U PFUCF U= CARRY FLAG - SET UP CARRY OUT OF MSB UNDEFINED PARITY FLAG – SET IF RESULT HAS EVEN PARITY AUXILIARY CARRY FLAG FOR BCD ZERO FLAG – SET IF RESULT = 0 SIGN FLAG = MSB OF RESULT SINGLE STEP TRAP FLAG INTERRUPT ENABLE FLAG STRING DIRECTION FLAG OVERFLOW FLAG ELE 3230 - Chatper 7 9  Flags Register z 9 of the 16 bits in FLAGS can be set to one when certain events occur (ie they flag the occurrence of an event.) The other 7 bits are unused. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FLAGS O D I T S Z A P C z All bits are set to zero on power up. z Conditional jump instructions test the O, S, Z, P and C flags. z Instructions (pushF, popF, LAHF, SAHF) are available for transferring the contents of the FLAGS register to/from the stack or to/from the AH register. Other instructions are available for manipulating certain flag bits (eg STI, CLI, STD, CLD, STC, CLC, CMC). eg. STI sets flag I to1, CLI sets flag I to 0, CMC complements flag C. For setting the flag T, see example 11-1 in Brey’s. ELE 3230 - Chatper 7 10  FLAGS FLAGS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 O D I T S Z A P C z Flags in the FLAGS register are either condition or control flags. z Condition flag consist of : y C (carry flag) - set to 1 when the result of an addition has a carry out of the most significant byte. Other instructions can also affect C (eg subtraction) y P (parity flag) - set to 1 if the low order byte of the result contains an even number of ones; otherwise it is set to zero. y A (auxiliary carry flag) - set to one if there is a carry out of bit 3 during an addition or a borrow by bit 3 during subtraction. y Z (zero flag) - set to 1 if the result is zero; Z is otherwise zero. y S (sign flag) - equal to the most significant bit of the result (ie set to 1 if the result is negative) y O (overflow flag) - set if a result is out of range (eg when adding two positive numbers and the result appears negative) ELE 3230 - Chatper 7 11  Control Flags 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 O D I T S Z A P C FLAGS z Three bits (D, I, T) in the flags register control the operation of the microprocessor under the following circumstances: yD (direction flag) - in certain string manipulation instructions, D determines whether the string is processed from the lowest address (D=0) or the highest address (D=1). D=0: auto-increment D=1: auto-decrement yI (interrupt flag) - determines whether a maskable interrupt is recognized by the microprocessor. If I=1, a maskable interrupt is possible, otherwise the interrupt is ignored. yT (trap flag) - if T=1, a trap (eg for single stepping through a program) is executed after every instruction. ELE 3230 - Chatper 7 12 Example of effect of an addition on the FLAGS register If the following addition is carried out, 0010 0011 0100 0101 + 0011 0010 0001 1001 0101 0101 0101 1110 the FLAGS register’s condition flags are set as follows: S (sign) =0, Z (zero) =0, P (parity) =0, C (carry) =0, A (aux carry) =0, O (overflow) =0 If instead the following were performed, 0101 0100 0011 1001 + 0100 0101 0110 1010 1001 1001 1010 0011 the FLAGS register’s condition flags world be set as follows: S (sign) =1, Z (zero) =0, P (parity) =1, C (carry) =0, A (aux carry) =1, O (overflow) =1 ELE 3230 - Chatper 7 13  Segment Registers 15 0 CS CODE SEGMENT DS DATA SEGMENT ES EXTRA SEGMENT SS STACK SEGMENT z Segment registers are 16-bit registers used in conjunction with the index and pointer registers to generate the physical 20-bit address. z Code segment is the section of memory used to store the program instructions and procedures. CS stores the starting address of the program code. In the 8086 (and 80286) the code segment is limited to 64Kbytes in length (in 80386 the maximum length is 4Gbytes). z Data segment (DS) contains data used by the program. DS stores the starting address of the data segment. z Extra segment is another data segment which is used by some string instructions. z Stack segment (SS) is the section in memory called stack which is used for storage of register contents and data. ELE 3230 - Chatper 7 14  Segmentation z A segment in the 8088 system is a continuous section of memory of up to 64Kbytes in length. z Since the segment address is shifted by 4 bits to form the 20-bit address, the start address of a segment can only occur at 16 data byte intervals. Addresses at every 16 data byte interval are valid for starting segments. (Increasing the segment value by 1 will increase the physical starting address by 16.) z The 64-Kbyte block defined by the start address of a segment may overlap with other segments or be completely in its own separate area of memory. z Segments allow packages of information (eg a data table, or a subroutine) to be kept separate - it is not necessary to fill all 64K of the segment and the programmer can make the segment of arbitrary size (up to 64K, in 16 byte increments). ELE 3230 - Chatper 7 15  Segments and Offsets z The 20-bit address in memory is generated by adding a 16-bit offset to a 16- bit segment address. The segment address defines the start of a 64kbyte memory block within the 1Mbyte address space, and the offset defines the exact memory location within that 64Kbyte block. z A 20-bit address is formed by shifting the 16-bit segment address by 4 bits and adding to the 16-bit offset. Bit 15 11 7 3 0 Shift 4 bits and append 0 Segment Bit 15 11 7 3 0 + Offset 20-bit physical address ELE 3230 - Chatper 7 16  Segments and Offsets (Cont.) z Advantages of the segment + offset method include 1. Program code can easily be reallocated in memory (useful for multi-tasking) 2. Most operations can be performed by changing only the 16 bit offset. The offset can be stored in 16-bit registers (20-bit registers are not necessary), allowing for easier interface to 8- and 16-bit wide memory. ELE 3230 - Chatper 7 17  Rules of combination of Segment registers and Offset z The microprocessor has a set of rules that define the segment register and offset register combination used by certain addressing modes. z However, the default can be overrode by using the segment override prefix e.g. MOV CL, [BP] or MOV CL,DS:[BP] Offset register Default Override Prefix Segment register IP CS Never SP SS Never BP SS DS, ES or CS SI, DI (not include strings) DS ES, SS or CS DI for string instructions ES Never ELE 3230 - Chatper 7 18  Addition of IP to CS to produce the physical address of the code type PHYSICAL ADDRESS MEMORY 4489FH TOP OF CODE SEGMENT Diagram 38AB4H CODE BYTE IP=4214H 348A0H START OF CODE SEGMENT CS=348AH (a) CS 3 4 8 A 0 HARDWIRED ZERO IP + 4 2 1 4 Computation PHYSICAL ADDRESS 3 8 A B 4 PHYSICAL ADDRESS (b) ELE 3230 - Chatper 7 19 Addition of SS and SP to produce the physical address of the top of the stack PHYSICAL ADDRESS MEMORY 5FFFFH TOP OF STACK SEGMENT 5FFE0H TOP OF STACK Diagram SP=FFE0H 50000H START OF STACK SEGMENT SS=5000H (a) SS 5 0 0 0 0 HARDWIRED ZERO SP + F F E 0 Computation PHYSICAL ADDRESS 5 F F E 0 (TOP OF STACK) (b) ELE 3230 - Chatper 7 20 Addition of data segment register and effective address to produce the physical address of the data byte PHYSICAL ADDRESS MEMORY 2FFFFH END OF DATA SEGMENT BX REGISTER BH BL Diagram 2437BH 2437AH MOV BX, [437AH] EA=437AH 20000H START OF DATA SEGMENT DS=2000H (a) DS 2 0 0 0 0 HARDWIRED ZERO EA + 4 3 7 A Computation PHYSICAL ADDRESS 2 4 3 7 A (b) ELE 3230 - Chatper 7 21 One way four 64-Kbyte segments might be positioned within the 1-Mbyte address space of an 8086 PHYSICAL ADDRESS MEMORY FFFFFH HIGHEST ADDRESS 7FFFFH TOP OF EXTRA SEGMENT 64K 70000H EXTRA SEGMENT BASE ES = 7000H 5FFFFH TOP OF STACK SEGMENT 64K 50000H STACK SEGMENT BASE SS = 5000H 4489FH TOP OF CODE SEGMENT 64K 348A0H CODE SEGMENT BASE CS = 348AH 2FFFFH TOP OF DATA SEGMENT 64K 20000H BOTTOM OF DATA SEGMENT ELE 3230 - Chatper 7 22