VLSI Design: CMOS Logic Gates, Amrita University PDF
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Amrita School of Engineering
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Summary
These slides cover the electronic analysis of CMOS logic gates, including topics such as DC characteristics, noise margin switching characteristics and power. It also include various VLSI design concepts such as transistor sizing and power dissipation. The slides are from Amrita School of Engineering.
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19ECE313/VLSI Design VI Semester Department of ECE Amrita School of Engineering, Bengaluru 7. Electronic Analysis of CMOS Logic Gates Goal Understand how to perform electronic analysis of CMOS logic gates. DC characteristics Noise margin Switching characteristics...
19ECE313/VLSI Design VI Semester Department of ECE Amrita School of Engineering, Bengaluru 7. Electronic Analysis of CMOS Logic Gates Goal Understand how to perform electronic analysis of CMOS logic gates. DC characteristics Noise margin Switching characteristics Power 5/5/2022 15ECE313/VLSI Design VI Semester, Department of ECE 2 PMOS and NMOS Structure 5/5/2022 15ECE313/VLSI Design VI Semester, Department of ECE 3 5/5/2022 15ECE313/VLSI Design VI Semester, Department of ECE 4 5/5/2022 15ECE313/VLSI Design VI Semester, Department of ECE 5 5/5/2022 15ECE313/VLSI Design VI Semester, Department of ECE 6 Ideal Voltage Transfer Characteristic (VTC) 5/5/2022 15ECE313/VLSI Design VI Semester, Department of ECE 7 CMOS Inverter VTC CMOS Inverter Voltage Transfer Characteristic (VTC) VIL and VIH are the two points at which Slope is equal to (dvout/dvin) = -1 5/5/2022 15ECE313/VLSI Design VI Semester, Department of ECE 8 CMOS Inverter VTC CMOS Inverter Voltage Transfer Characteristic (VTC) 5/5/2022 15ECE313/VLSI Design VI Semester, Department of ECE 9 Finding Region of Operation of MOSFETs in various regions of VTC of CMOS Inverter Region Vin Vout NMOS PMOS Operating Operating Region Region A < Vtn VDD B VIL VOH ≈ VDD (HIGH) C VM VM D VIH VOL ≈ GND (LOW) E VDD GND 5/5/2022 15ECE313/VLSI Design VI Semester, Department of ECE 10 For Region A on VTC For NMOS For PMOS VG = (