CMOS Digital Integrated Circuits: Analysis and Design PDF

Physical and Materials Constants Boltzmann's constant k 1.38 x 10-23 J/K Electron charge q 1.6 x 10-19 C Thermal voltage kT/q 0.026 V (at T= 300 K) Energ...

Physical and Materials Constants Boltzmann's constant k 1.38 x 10-23 J/K Electron charge q 1.6 x 10-19 C Thermal voltage kT/q 0.026 V (at T= 300 K) Energy gap of silicon (Si) Eg 1.12 eV (at T = 300 K) Intrinsic carrier concentration of silicon (Si) ni 1.45 x 1010 cm73 (at T = 300 K) Dielectric constant of vacuum 60 8.85 x 10-14 F/cm Dielectric constant of silicon (Si) ESi 11.7 x O F/cm Dielectric constant of silicon dioxide (SiO2 ) 6.x 3.97 x EO F/cm Commonly Used Prefixes for Units giga G 109 mega M 106 kilo k 103 milli m 10-3 In 10-6 micro nano n 10-9 pico p 10-12 femto f 10-15  second edition CMO S DIGITAL INTE GRATE D CI RCUITS Analysis and Design SUNG-MO (STEVE) ANG University of Illinois at Urbana- Champaign YUSUF LEBLEBIGI Worcester Polytechnic Institute Swiss Federal Institute of Technology-Lausanne U McGraw-Hill.* Boston Burr Ridge, IL Dubuque, IA Madison, WI New York San Francisco St. Louis Bangkok Bogota Caracas Lisbon London Madrid Mexico City Milan New Delhi Seoul Singapore Sydney Taipei Toronto  Copyrighted Material McGmlfl-Hill Higher Education sz A Division of'f1tt' M:Ora ·H ill Omtpanics CMOS DIGITAL lNTEORATEO CIRCUITS: ANALYSIS ANDD€SIGN TliJRD EDITION Pi blislled by McGr:t\\o'·HiU. a businCS.'!unil o(The McOrnw·Hill Comp:mic s. Inc.. 122 I Avenue oftheAtnericas, New YO 'k, NY 10020. Copyrighl() 2003. 1999, 1996 by The McOrsw-Hill Companies, loc. All rights !laved. No Jllll't of lhis publkation muy be reproduooc.l or di triboted in My form or by any means. or stored in l.ll.iatilbi St Of teltleval systenl. without the prior wr inw consent o(The McCr-.1w·Hill Co.npanks. Inc.. including. but oot limih!d t(), in any nctviotk or ()(her electronic SlorlgC or I.Jnnsm ssion. ()r bl'l);ui M for distance lenming. Some: ;uKiUaries, inc-luding electronic and prim compoDCnts. nl:l)' n(lt bt ;h';lll:d)IC to eusaomcrs ouiSide the United Stutt5. Tbi$ boot Is r-imed on acid·froc PQper. Jntcmational 2 J4 56 7 8 90 QPF/QP1'09 8765 4 3 Po n oestic 2 3-1 56 7 8 9 0 QPF/QPF 0 98 7 6 S 4 3 ISBN G-07-246053-9 ISBN -119644-7(1SE) PuhU:Ulet: Ell:.aMthA. Jones Senior t.])OOIIOrint,edil(lr: Crul; ePmllwlt Developmenlal editor: Mklr :.llt: 1... f.'l(»f'U'rdwfi Executive marketing manager: John UlmnemtKI!er Senior project manager: Ro. e Koos Produe1ion super '\'i.SQf': S/t crry {... Kcme Media projce1manager. Jodi K. &..rt. t1 1 0'n' Senior media technol y producer: Plt llllp MNk Coordi nato r of(l'tltliiOce design; Rick D. NOt:! COver desig ner: Sht!li(JitBorreu Co' c:r ima.ge: Dt'CAlt/Jm mif:Jt rtN.:esSI)r cltlp phologmplt, nesy /tfidwellkn-idrm. fh,it/(J Swte UnlwrsityNmiorwl 1/iglt Magnetir; fi " t:lr/ Lulwrow r. v Composi1or: lmemctRoe Compositim CorpomtiQ1t 'JYptft te:: JOI121iJ W Roman Printer: Qu(becQr %rid f'tlirfit:M, PA Library orCong.ras Cnllll(l ln ·ln-Publkation Oaca Kang, Sung· IO, 1945- CMOS digital imeyatcd ci rcuits : analysis :md d lgn I Sung-Mo (Sit' ·c) Kang. Yusur LeblebicL -3rd cd. p. c1n. lnc:ludes biblk>y.tphie:tl references and indc:.x. lSBN 0-07-24605 9- ISDN 0.00-119644-7 (ISE) 1. Metal oxide. semicondoctors. Complement.vy. 2. Digi1;d i.nc rnted circuits. t Ublebid, Yu:suf. U. TiOe. TK7871.99.M44 K36 2003 621.39'5-dcll 2002026558 CIP lNT'ERNATIONALEDITION ISBN 0-07-119644-7 Cop)'ri,a.hl 0 2003. Exclusi tighLS byThe McGraw-Hill CompaniQ.. Inc., for mOlnuf;u.:ture ;tnd expcJrL 'lnil boot cannot be rt·C.XJIOC1cd from the ooontry towtaicb it i s llold by Mc.:Gr;,w.liill. The lntemation; l Edilion1s nOi tl\'ilil: ble ln Nanh An..eric :t... www.mhhe.com Copyrighted Material CONTENTS PREFACE xi 1 INTRODUCTION 1 1.1 Historical Perspective 1 1.2 Objective and Organization of the Book 5 1.3 A Circuit Design Example 8 2 FABRICATION OF MOSFETs 20 2.1 Introduction 20 2.2 Fabrication Process Flow: Basic Steps 21 2.3 The CMOS nWell Process 29 2.4 Layout Design Rules 37 2.5 Full-Custom Mask Layout Design 40 References 44 Exercise Problems 45 3 MOS TRANSISTOR 47 3.1 The Metal Oxide Semiconductor (MOS) Structure 48 3.2 The MOS System under External Bias 52 3.3 Structure and Operation of MOS Transistor (MOSFET) 55 3.4 MOSFET Current-Voltage Characteristics 66 3.5 MOSFET Scaling and Small-Geometry Effects 81 3.6 MOSFET Capacitances 97 References 110 Exercise Problems 111 vi. 4 MODELING OF MOS TRANSISTORS USING SPICE 117 Contents 4.1 Basic Concepts 118 4.2 The LEVEL 1 Model Equations 119 4.3 The LEVEL 2 Model Equations 123 4.4 The LEVEL 3 Model Equations 130 4.5 Capacitance Models 131 4.6 Comparison of the SPICE MOSFET Models 135 References 137 Appendix: Typical SPICE Model Parameters 138 Exercise Problems 139 5 MOS INVERTERS: STATIC CHARACTERISTICS 141 5.1 Introduction 141 5.2 Resistive-Load Inverter 149 5.3 Inverters with n-Type MOSFET Load 160 5.5 CMOS Inverter 172 References 190 Exercise Problems 191 6 MOS INVERTERS: SWITCHING CHARACTERISTICS AND INTERCONNECT EFFECTS 196 6.1 Introduction 196 6.2 Delay-Time Definitions 198 6.3 Calculation of Delay Times 200 6.4 Inverter Design with Delay Constraints 210 6.5 Estimation of Interconnect Parasitics 222 6.6 Calculation of Interconnect Delay 234 6.7 Switching Power Dissipation of CMOS Inverters 242 References 250 Appendix: Super Buffer Design 251 Exercise Problems 254 7 COMBINATIONAL MOS LOGIC CIRCUITS 259 7.1 Introduction 259 7.2 MOS Logic Circuits with Depletion nMOS Loads 260 7.3 CMOS Logic Circuits 274 7.4 Complex Logic Circuits 281 7.5 CMOS Transmission Gates (Pass Gates) 295 References 305 Exercise Problems 306 8 SEQUENTIAL MOS LOGIC CIRCUITS 312 vii 8.1 Introduction 312 Contents 8.2 Behavior of Bistable Elements 314 8.3 The SR Latch Circuit 320 8.4 Clocked Latch and Flip-Flop Circuits 326 8.5 CMOS D-Latch and Edge-Triggered Flip-Flop 334 Appendix: Schmitt Trigger Circuit 341 Exercise Problems 345 9 DYNAMIC LOGIC CIRCUITS 350 9.1 Introduction 350 9.2 Basic Principles of Pass Transistor Circuits 352 9.3 Voltage Bootstrapping 365 9.4 Synchronous Dynamic Circuit Techniques 368 9.5 High-Performance Dynamic CMOS Circuits 378 References 395 Exercise Problems 396 10 SEMICONDUCTOR MEMORIES 402 10.1 Introduction 402 10.2 Read-Only Memory (ROM) Circuits 405 10.3 Static Read-Write Memory (SRAM) Circuits 417 10.4 Dynamic Read-Write Memory (DRAM) Circuits 435 References 447 Exercise Problems 447 11 LOW-POWER CMOS LOGIC CIRCUITS 451 11.1 Introduction 451 11.2 Overview of Power Consumption 452 11.3 Low-Power Design Through Voltage Scaling 463 11.4 Estimation and Optimization of Switching Activity 474 11.5 Reduction of Switched Capacitance 480 11.6 Adiabatic Logic Circuits 482 References 489 Exercise Problems 490 12 BiCMOS LOGIC CIRCUITS 491 12.1 Introduction 491 12.2 Bipolar Junction Transistor (BJT): Structure and Operation 494 viii 12.3 Dynamic Behavior of BJTs 509 12.4 Basic BiCMOS Circuits: Static Behavior 516 Contents 12.5 Switching Delay in BiCMOS Logic Circuits 519 12.6 BiCMOS Applications 524 References 529 Exercise Problems 530 13 CHIP INPUT AND OUTPUT (O) CIRCUITS 534 13.1 Introduction 534 13.2 ESD Protection 535 13.3 Input Circuits 538 13.4 Output Circuits and L(di/dt) Noise 543 13.5 On-Chip Clock Generation and Distribution 549 13.6 Latch-Up and Its Prevention 555 References 562 Exercise Problems 563 14 VLSI DESIGN METHODOLOGIES 566 14.1 Introduction 566 14.2 VLSI Design Flow 569 14.3 Design Hierarchy 570 14.4 Concepts of Regularity, Modularity and Locality 573 14.5 VLSI Design Styles 576 14.6 Design Quality 586 14.7 Packaging Technology 589 14.8 Computer-Aided Design Technology 592 References 593 Exercise Problems 594 15 DESIGN FOR MANUFACTURABILITY 598 15.1 Introduction 598 15.2 Process Variations 599 15.3 Basic Concepts and Definitions 601 15.4 Design of Experiments and Performance Modeling 608 15.5 Parametric Yield Estimation 615 15.6 Parametric Yield Maximization 621 15.7 Worst-Case Analysis 622 15.8 Performance Variability Minimization 628 References 633 Exercise Problems 633  16 DESIGN FOR TESTABILITY 638 ix 16.1 Introduction 638 Contents 16.2 Fault Types and Models 638 16.3 Controllability and Observability 642 16.4 Ad Hoc Testable Design Techniques 644 16.5 Scan-Based Techniques 646 16.6 Built-In Self Test (BIST) Techniques 648 16.7 Current Monitoring IDDQ Test 651 References 653 Exercise Problems 653 INDEX 655 ABOUT THE AUTIORS Sung-Mo (Steve) Kang received the Ph.D. degree in electrical engineering from the University of California at Berkeley. He has worked on CMOS VLSI design at AT&T Bell Laboratories at Murray Hill, N.J. as supervisor and member of technical staff of high-end CMOS VLSI microprocessor design. Currently, he is professor and head of the department of electrical and computer engineering at the University of Illinois at Urbana- Champaign. He was the founding editor-in-chief of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems and has served on editorial boards of several IEEE and international journals. He has received a Humboldt Research Award for Senior US Scientists, IEEE Graduate Teaching Technical Field Award, IEEE Circuits and Systems Society Technical Achievement Award, SRC Inventor Recognition Awards, IEEE CAS Darlington Prize Paper Award and other best paper awards. He has also co-authored DesignAutomationforTiming-DrivenLayout Synthesis, Hot- CarrierReliabilityofMOS VLSI Circuits, Physical Design for Multichip Modules, and Modeling of Electrical Overtstress in Integrated Circuits from Kluwer Academic Publishers, and Computer- Aided Design of Optoelectronic Integrated Circuits and Systems from Prentice Hall. Yusuf Leblebici received the Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign. He was a visiting assistant professor of electrical and computer engineering at the University of Illinois at Urbana- Champaign, associate professor of electrical and electronics engineering at Istanbul Technical University, and invited professor of electrical engineering at the Swiss Federal Institute of Technology in Lausanne, Switzerland. Currently, he is an associate professor of electrical and computer engineering at Worcester Polytechnic Institute. Dr. Leblebici is also a member of technical staff at the New England Center for Analog and Digital Integrated Circuit Design. His research interests include high- performance digital integrated circuit architectures, modeling and simulation of semi- conductor devices, computer-aided design of VLSI circuits, and VLSI reliability analy- sis. He has received a NATO Science Fellowship Award, has been an Horiors Scholar of the Turkish Scientific and Technological Research Council, and has received the Young Scientist Award of the same council. Dr. Leblebici has co-authored about fifty technical papers and two books. PREFACE Complementary metal oxide semiconductor (CMOS) digital integrated circuits are the enabling technology for the modern information age. Because of their intrinsic features in low-power consumption, large noise margins, and ease of design, CMOS integrated circuits have been widely used to develop random access memory (RAM) chips, microprocessor chips, digital signal processor (DSP) chips, and application- specific integrated circuit (ASIC) chips. The popular use of CMOS circuits will grow with the increasing demands for low-power, low-noise integrated electronic systems in the development of portable computers, personal digital assistants (PDAs), portable phones, and multimedia agents. Since the field of CMOS integrated circuits alone is very broad, it is conventionally divided into digital CMOS circuits and analog CMOS circuits. This book is focused on the CMOS digital integrated circuits. At the University of Illinois at Urbana-Champaign, we have tried some of the available textbooks on digital MOS integrated circuits for our senior-level technical elective course, ECE382 - Large!ScaleIntegratedCircuitDesign. Students and instructors alike realized, however, that-there was a need for a new book with more comprehensive treatment of CMOS digital circuits. Thus, our textbook project was initiated several years ago by assembling our own lecture notes. Since 1993, we have used evolving versions of this material at the University of Illinois at Urbana-Champaign, at Istanbul Technical University and at the Swiss Federal Institute of Technology in Lausanne. Both authors were very much encouraged by comments from their students, colleagues, and reviewers. The first edition of CMOS Digital Integrated Circuits: Analysis and Design was published in late 1995. xii Soon after publishing the first edition, we saw the need for updating the it to reflect many constructive comments from instructors and students who used the textbook, to Preface include the topic of low-power circuit design and provide more rigorous treatment of interconnects in high-speed circuit design as well as the deep submicron circuit design issues. We also felt that in a very rapidly developing field such as CMOS digital circuits, the quality of a textbook can only be preserved by timely updates reflecting the current state-of-the-art. This realization has led us to embark on the extensive project of revising our work, to reflect recent advances in technology and in circuit design practices. This book, CMOS Digital Integrated Circuits: Analysis and Design, is primarily intended as a comprehensive textbook at the senior level and first-year graduate level, as well as a reference for practicing engineers in the areas of integrated circuit design, digital design, and VLSI. Recognizing that the area of digital integrated circuit design is evolving at an increasingly faster pace, we have made every.possible effort to present up- to-date materials on all subjects covered. This book contains sixteen chapters; and we recognize that it would not be possible to cover rigorously all of this material in one semester. Thus, we would propose the following based on our teaching experience: At the undergraduate level, coverage of the first ten chapters would constitute sufficient material for a one-semester course on CMOS digital integrated circuits. Time permitting, some selected topics in Chapter 11, Low-Power CMOS Logic Circuits, Chapter 12, BiCMOS Logic Circuits and Chapter 13, Chip Input and Output (1/O) Circuits can also be covered. Alternatively, this book can be used for a two-semester course, allowing a more detailed treatment of advanced issues, which are presented in the later chapters. At the graduate level, selected topics from the first eleven chapters plus the last five chapters can be covered in one semester. The first eight chapters of this book are devoted to a detailed treatment of the MOS transistor with all its relevant aspects; to the static and dynamic operation principles, analysis and design of basic inverter circuits; and to the structure and operation of combinational and sequential logic gates. The issues of on-chip interconnect modeling and interconnect delay calculation are covered extensively in Chapter 6. Indeed, Chapter 6 has been significantly extended to provide a more complete view of switching characteristics in digital integrated circuits. The coverage of technology-related issues has been complemented with the addition of several color plates and graphics, which we hope will also enhance the educational value of the text. A separate chapter (Chapter 9) has been reserved for the treatment of dynamic logic circuits which are used in state-of- the-art VLSI chips. Chapter 10 offers an in-depth presentation of semiconductor memory circuits. Recognizing the increasing importance of low-power circuit design, we decided to add a new chapter (Chapter 11) on low-power CMOS logic circuits. This new chapter provides a comprehensive coverage of methodologies and design practices that are used to reduce the power dissipation of large-scale digital integrated circuits. BiCMOS digital circuit design is examined in Chapter 12, with a thorough coverage of bipolar transistor basics. Considering the on-going use of bipolar circuits and BiCMOS circuits, we believe that at least one chapter should be allocated to cover the basics of bipolar transistors. Next, Chapter 13 provides a clear insight into the important subject of chip I/O design. Critical issues such as ESD protection, clock distribution, clock buffering, and latch-up phenom- enon are discussed in detail. Design methodologies and tools for very large scale integration (VLSI) are presented in Chapter 14. Finally, the more advanced but very important topics of design for manufacturability and design for testability are covered in xiii Chapters 15 and 16, respectively, The authors have long debated the coverage of nMOS circuits in this book. We have Preface finally concluded that some coverage should be provided for pedagogical reasons. Studying nMOS circuits will better prepare readers for analysis of other field effect transistor (FET) circuits such as GaAs circuits, the topology of which is quite similar to that of depletion-load riMOS circuits. Thus, to emphasize the load concept, which is still widely used in many areas in digital circuit design, we present basic depletion-load nMOS circuits along with their CMOS counterparts in several places throughout the book. Although an immense amount of effort and attention to detail were expended to prepare the camera-ready manuscript, this book may still have some flaws and mistakes due to erring human nature. The authors would welcome and greatly appreciate sugges- tions and corrections from the readers, for the improvement of the technical content as well as the presentation style. Acknowledgements for the First Edition Our colleagues have provided many constructive comments and encouragement for the completion of the first edition. Professor Timothy N. Trick, former head of the depart- ment f electrical and computer engineering at the University of Illinois at Urbana- Champaign, has strongly supported our efforts from the very beginning. The appointment of Sung-Mo Kang as an associate in the Center for Advanced Study at the University of Illinois at Urbana-Champaign helped to start the process. Yusuf Leblebici acknowledges the full support and encouragement from the depart- ment of electrical and electronics engineering at Istanbul Technical University, where he introduced a new digital integrated circuits course based on the early version of this book and received very valuable feedback from his students. Yusuf Leblebici also thanks the ETA Advanced Electronics Technologies Research and Development Foundation at Istanbul Technical University for their generous support. Professor Elyse Rosenbaum and Professor Resve Saleh used the early versions of the manuscript as the textbook for ECE382 at Illinois and provided many helpful comments and corrections which have been fully incorporated with deep appreciation. Professor Elizabeth Brauer, currently at Northern Arizona University, has also done the same at the University of Kentucky. The authors would like to express sincere gratitude to Professor Janak Patel of the University of Illinois at Urbana-Champaign for generously mentoring the authors in writing Chapter 16, Designfor Testability. Professor Patel has provided many construc- tive comments and many of his expert views on the subject are reflected in this chapter. Professor Prith Banerjee of Northwestern University and Professor Farid Najm of the University of Illinois at Urbana-Champaign also provided many good comments. We would also like to thank Dr. Abhijit Dharchoudhury for his invaluable contribution to Chapter 15, Designfor Manufacturability. Professor Duran Leblebici of Istanbul Technical University, who is the father of the second author, reviewed the entire manuscript in its early development phase, and provided very extensive and constructive comments, many of which are reflected in the final version. Both authors gratefully acknowledge his support during all stages of this xiv venture. We also thank Professor Cem Goknar of Istanbul Technical University, who offered very detailed and valuable comments on Design for Testability, and Professor Preface Ugur Qilingiroglu of the same university, who offered many excellent suggestions for improving the manuscript, especially the chapter on semiconductor memories. Many of the authors' former and current students at the University of Illinois at Urbana-Champaign also helped in the preparation of figures and verification of circuits using SPICE simulations. In particular, Dr. James Morikuni, Dr. Weishi Sun, Dr. Pablo Mena, Dr. Jaewon Kim, Mr. Steve Ho and Mr. Sueng-Yong Park deserve recognition. Ms. Lilian Beck and the staff members of the Publications Office in the department of electrical and computer engineering at the University of Illinois at Urbana-Champaign read the entire manuscript and provided excellent editorial comments. The authors would also like to thank Dr. Masakazu Shoji of AT&T Bell Laboratories, Professor Gerold W. Neudeck of Purdue University, Professor Chin-Long Wey of Michigan State University, Professor Andrew T. Yang of the University of Washington, Professor Marwan M. Hassoun of Iowa State University, Professor Charles E. Stroud of the University of Kentucky, Professor Lawrence Pileggi of the University of Texas at Austin, and Professor Yu Hen Hu of the University of Wisconsin at Madison, who read all or parts of the manuscript and provided many valuable comments and encouragement. The editorial staff of McGraw-Hill has been an excellent source of strong support from the beginning of this textbook project. The venture was originally initiated with the enthusiastic encouragement from the previous electrical engineering editor, Ms. Anne (Brown) Akay. Mr. George Hoffman, in spite of his relatively short association, was extremely effective and helped settle the details of the publication planning. During the last stage, the new electrical engineering editor, Ms. Lynn Cox, and Mr. John Morriss, Mr. David Damstra, and Mr. Norman Pedersen of the Editing Department were superbly effective and we enjoyed dashing with them to finish the last mile. Acknowledgements for the Second Edition The authors are truly indebted to many individuals who, with their efforts and their help, made the second edition possible. We would like to thank Dr. Wolfgang Fichtner, President and CEO of ISE Integrated Systems Engineering, Inc. and the technical staff of ISE in Zurich, Switzerland for providing computer-generated cross-sectional color graphics of MOS transistors and CMOS inverters, which are featured in the color plates. The first author acknowledges the support provided by the U.S. Senior Scientist Research Award from the Alexander von Humbold Stiftung in Germany, which was very helpful for the second edition. The appointments of the second author as Associate Professor at Worcester Polytechnic Institute and as Visiting Professor at the Swiss Federal Institute of Technology in Lausanne, Switzerland have provided excellent environments for the completion of the revision project. The second author also thanks Professor Daniel Mlynek of the the Swiss Federal Institute of Technology in Lausanne for his continuous encouragement and support. Many of the authors' former and current students at the University of Illinois at Urbana-Champaign, at the Swiss Federal Institute of Technology in Lausanne and at Worcester Polytechnic Institute also helped in the preparation of figures and verification of circuits using SPICE simulations. In particular, Dr. James Stroming and Mr. Frank K. Gilrkaynak deserve special recogni- tion for their extensive and valuable efforts.  The authors would also like to thank Professor Charles Kime of the University of xv Wisconsin at Madison, Professor Gerold W. Neudeck of Purdue University, Professor D.E. oannou of George Mason University, Professor Subramanya Kalkur of the Preface University of Colorado, Professor Jeffrey L. Gray of Purdue University, Professor Jacob Abraham of the University of Texas at Austin, Professor Hisham Z. Massoud of Duke University, Professor Norman C. Tien of Cornell University, Professor Rod Beresford of Brown University, Professor Elizabeth J. Brauer of Northern Arizona University and Professor Reginald J. Perry of Florida State University, who read all or parts of the revised manuscript and provided their valuable comments and encouragement. The editorial staff of McGraw-Hill has, as always, been wonderfully supportive from the beginning of the revision project. We thankfully recognize the contributions of our previous electrical engineering editor, Ms. Lynn Cox, and we appreciate the extensive efforts of Ms. Nina Kreiden, who helped the project get off the ground in its early stages. During the final stages of this project, Ms. Kelley Butcher, Ms. Karen Nelson and Mr. Francis Owens have been extremely effective and helpful, and we enjoyed sharing this experience with them. Finally, we would like to acknowledge the support from our families, Myoung-A (Mia),,Jennifer and Jeffrey Kang, and Anl and Ebru Leblebici, for tolerating many of our physical and mental absences while we worked on the second edition of this book, and for providing us invaluable encouragement throughout the project. Sung-Mo (Steve) Kang Yusuf Leblebici Urbana, Illinois Worcester, Massachusetts August 1998 August 1998 CHAPTER 1 INTRODUCTION 1.1. Historical Perspective The electronics industry has achieved a phenomenal growth over the last few decades, mainly due to the rapid advances in integration technologies and large-scale systems design. The use of integrated circuits in high-performance computing, telecommunica- tions, and consumer electronics has been growing at a very fast pace. Typically, the required computational and information processing power of these applications is the driving force for the fast development of this field. Figure 1.1 gives an overview of the prominent trends in information technologies over the next decade. The current leading- edge technologies (such as low bit-rate video and cellular communications) already provide the end-users a certain amount of processing power and portability. This trend is expected to continue, with very important implications for VLSI and systems design. One of the most important characteristics of information services is their increasing need for very high processing power and bandwidth (in order to handle real-time video, for example). The other important characteristic is that the information services tend to become more personalized, which means that the information processing devices must be more intelligent and also be portable to allow more mobility. This trend towards portable, distributed system architectures is one of the main driving forces for system integration, even though it does not preclude a concurrent and equally important trend towards centralized, highly powerful information systems such as those required for network computing (NC) and video services. As more and more complex functions are required in various data processing and telecommunications devices, the need to integrate these functions in a small package is also increasing. The level of integration as measured by the number of logic gates in a 2 monolithic chip has been steadily rising for almost three decades, mainly due to the rapid progress in processing technology and interconnect technology. Table 1.1 shows the CHAPTER 1 evolution of logic complexity in integrated circuits over the last three decades, and marks the milestones of each era. Here, the numbers for circuit complexity should be viewed only as representative measures to indicate the order-of-magnitude. A logic block can contain anywhere from 10 to 100 transistors, depending on the function. State-of-the-art ULSI chips, such as the DEC Alpha or the INTEL Pentium, contain 3 to 6 million transistors. Note that the term VLSI has been used continuously even for chips in the ULSI (Ultra Large Scale Integration) category, not necessarily abiding by the distinction in Table 1.1. I Video-on-demand I I Speech processing/recognition | I-C Wireless/cellular data communication c I Data communication Multi-media applications | I Consumer electronics] I Portable computers | I Mainframe co I Personal computers I I Network computers I -------------- 1970 1980 1990 2000 Figure1.1. Prominent "driving" trends in information service technologies. ERA DATE COMPLEXITY (# of logic blocks per chip) Single transistor 1958 0 (small) Metal (Ai) Oxide Semiconductor (Si) MOS Transistor ~x E 4i3i:&:Ei x |Oxide Ec El EFP Depletion region p-type Si substrate Ev VB= 0 Figure 3.6. The cross-sectional view and the energy band diagram of the MOS structure operating in depletion mode, under small gate bias. dQ = -q NA dx (3.7) The change in surface potential required to displace this charge sheet dQ by a distance Xd away from the surface can be found by using the Poisson equation. do, = X Q = q NA dx (3.8) Esi Esi Integrating (3.7) along the vertical dimension (perpendicular to the surface) yields s Xd fJd.=Nq.NA.x dx (3.9) F 0 ESi qNA 22 (3.10) Esi Thus, the depth of the depletion region is X _ 2ecsj - FI X= q -NA (3.11) and the depletion region charge density, which consists solely of fixed acceptor ions in this region, is given by the following expression 54 Q--q NA d =-2q NA -E-si s,--F (3.12) CHAPTER 3 The amount of this depletion region charge plays a very important role in the analysis of threshold voltage, as we will examine shortly. To complete our qualitative overview of different bias conditions and their effects upon the MOS system, consider next a further increase in the positive gate bias. As a result of the increasing surface potential, the downward bending of the energy bands will increase as well. Eventually, the mid-gap energy level Ei becomes smaller than the Fermi level EFP on the surface, which means that the substrate semiconductor in this region becomes n-type. Within this thin layer, the electron density is larger than the majority hole density, since the positive gate potential attracts additional minority carriers (electrons) from the bulk substrate to the surface (Fig. 3.7). The n-type region created near the surface by the positive gate bias is called the inversion layer, and this condition is called surface inversion. It will be seen that the thin inversion layer on the surface with a large mobile electron concentration can be utilized for conducting current between two terminals of the MOS transistor. Metal (Al) Oxide Semiconductor (Si) EC El EFp Ev EFm Figure 3.7. The cross-sectional view and the energy band diagram of the MOS structure in surface inversion, under larger gate bias voltage. As a practical definition, the surface is said to be inverted when the density of mobile electrons on the surface becomes equal to the density of holes in the bulk (p-type) substrate. This condition requires that the surface potential has the same magnitude, but the reverse polarity, as the bulk Fermi potential OF. Once the surface is inverted, any further increase in the gate voltage leads to an increase of mobile electron concentration on the surface, but not to an increase of the depletion depth. Thus, the depletion region depth achieved at the onset of surface inversion is also equal to the maximum depletion depth, xdm, which remains constant for higher gate voltages. Using the inversion condition Os = O IF, the maximum depletion region depth at the onset of surface inversion can be found from (3.11) as follows:  cc (3.13) MOS Transistor ~~~~~~~~qNA (31) MOS Transistor The creation of a conducting surface inversion layer through externally applied lied gate bias is an essential phenomenon for current conduction in MOS transistors. In the he following section, we will examine the structure and the operation of the MOS Field Effect (MOSFET). Transistor Qv Structure and Operation of MOS Transistor (MOSFET) 3.3. StruCtL The basic str structure of an n-channel MOSFET is shown in Fig. 3.8. This four-terminal.our-terminal device consist consists of a p-type substrate, in which two n+ diffusion regions, the drain and the source, are fc formed. The surface of the substrate region between the drain and nd the source is covered wi with a thin oxide layer, and the metal (or polysilicon) gate is deposited sitedd on top of this gate di dielectric. The midsection of the device can easily be recognizedd as the basic structurewhich was examined in the previous sections. The two n+ regions MOS structui gions will be the current-c current-conducting terminals of this device. Note that the device structure is completely s, symmetrical with respect to the drain and source regions; the different different roles of these two nregions will bedefined only in conjunction with the applied terminal Linal voltages direction of the current flow. and the direc tGATE 3.8. Figure 38. The physical structure of an n-channel enhancement-type MOSFET. T. conducting channel will eventually be formed through applied gate voltage A condu voltage in the section of section of ftthedevice between the drain and the source diffusion regions. The distance between the the, drain and source diffusion regions is the channel length L, and nd the lateral extent of the channel (perpendicular to the length dimension) is the channel wel width W. Both the charnel cha length and the channel width are important parameters which which can can be control some of the electrical properties of the MOSFET. The thickness used to contr ckness of the covering the channel region, tx, is also an important parameter. oxide layer c tr. A MOS transistor which has no conducting channel region at zero gate bias is called AMM 'anenhancement-type (or enhancement-mode) MOSFET. If a conducting channel 'anenhancem annel already exists at zero zer( gate bias, on the other hand, the device is called a depletion-type (or Won-type (or 56 depletion-mode) MOSFET. In a MOSFET with p-type substrate and with n+ source and drain regions, the channel region to be formed on the surface is n-type. Thus, such a device CHAPTER 3 with p-type substrate is called an n-channel MOSFET. In a MOSFET with n-type substrate and with p+ source and drain regions, on the other hand, the channel is p-type and the device is called a p-channel MOSFET. D D D Gqd B G Gd: G H ~B G- G -~ S S S D D D 4-Terminal Simplified Simplified 4-Terminal Simplified Simplified n-channel MOSFET p-channel MOSFET Figure 3.9. Circuit symbols for n-channel and p-channel enhancement-type MOSFETs. The abbreviations used for the device terminals are: G for the gate, D for the drain, S for the source, and B for the substrate (or body). In an n-channel MOSFET, the source is defined as the n region which has a lower potential than the other n region, the drain. By convention, all terminal voltages of the device are defined with respect to the source potential. Thus, the gate-to-source voltage is denoted by VGS, the drain-to-source voltage is denoted by VDS, and the substrate-to-source voltage is denoted by VBS. Circuit symbols for both n-channel and p-channel enhancement-type MOSFETs are shown in Fig. 3.9. While the four-terminal symbolic representation shows all external terminals of the device, the simple three-terminal representation will also be used extensively. Note that in the simple MOSFET circuit symbol, the small arrow always marks the source terminal. Consider first the n-channel enhancement-type MOSFET shown in Fig. 3.8. The simple operation principle of this device is: control the current conduction between the source and the drain, using the electricfield generatedby the gate voltage as a control variable. Since the current flow in the channel is also controlled by the drain-,to-source voltage and by the substrate voltage, the current can be considered a function of these external terminal voltages. We will examine in detail the functional relationships between the channel current (also called the draincurrent) and the terminal voltages. In order to start current flow between the source and the drain regions, however, we have to form a conducting channel first. The simplest bias condition that can be applied to the n-channel enhancement-type MOSFET is shown in Fig: 3.10. The source, the drain, and the substrate terminals are all connected to ground. A positive gate-to-source voltage VGS is then applied to the gate in order to create the conducting channel underneath the gate. With this bias arrangement, the channel region between the source and the drain diffusions behaves exactly the same as for the simple MOS structure we examined in Section 3.2. For small gate voltage levels, the majority carriers (holes) are repelled back into the substrate, and the surface of the p-type substrate is depleted. Since the surface is devoid of any mobile carriers, current conduction between the source and the drain is not possible.  57 MOS Transistor Figure 3.10. Formation of a depletion region in an n-channel enhancement-type MOSFET. Now assume that the gate-to-source voltage is further increased. As soon as the surface potential in the channel region reaches - F surface inversion will be estab- lished, and a conducting n-type layer will form between the source and the drain diffusion regions (Fig. 3.11). This channel now provides an electrical connection between the two n+ regions, and it allows current flow, as long as there is a potential difference between the source and the drain terminal voltages (Fig. 3.12). The bias conditions for the onset of surface inversion and for the creation of the conducting channel are therefore very significant for MOSFET operation. The value of the gate-to-source voltage VGS needed to cause surface inversion (to create the conducting channel) is called the threshold voltage V. Any gate- Metal (Al) Oxide Semiconductor (SI) p-type Ec ---- qVTo 12 F --1:- Lk--O--F EFp Ev E Fm Figure3.11. Band diagram of the MOS structure underneath the gate, at surface inversion. Notice the band bending by 12OF1 at the surface. to-source voltage smaller than V70 is not sufficient to establish an inversion layer; thus, the MOSFET can conduct no current between its source and drain terminals unless VGS >V7. For gate-to-source voltages larger than the threshold voltage, on the other hand, 58 a larger number of minority carriers (electrons) are attracted to the surface, which ultimately contribute to channel current conduction. Also note that increasing the gate- CHAPTER 3 to-source voltage above and beyond the threshold voltage will not affect the surface potential and the depletion region depth. Both quantities will remain approximately constant and equal to their values attained at the onset of surface inversion. Vs 0 Ves > VTo VDs = 0 v v In GATE TI - 7 1 1 OXIDE I r 1 SOURCE I.. DRAIN F I I(my n+)) z / - l I: (ni.o : / LAYER (CHANNEL aINVERSION SUBSTRATE (p-Si) DEPLETION REGION L VB=O Figure 3.12. Formation of an inversion layer (channel) in an n-channel enhancement-type MOSFET. The Threshold Voltage In the following, physical parameters affecting the threshold voltage of a MOS structure will be examined by considering the various components of VTO. For all practical purposes, we can identify four physical components of the threshold voltage: (i) the work function difference between the gate and the channel, (ii) the gate voltage component to change the surface potential, (iii) the gate voltage component to offset the depletion region charge, and (iv) the voltage component to offset the fixed charges in the gate oxide and in the silicon-oxide interface. The analysis will be carried out for an n-channel device, but the results are applicable to p-channel devices as well, with minor modifications. The work function difference TGC between the gate and the channel reflects the built-in potential of the MOS system, which consists of the p-type substrate, the thin silicon dioxide layer, and the gate electrode. Depending on the gate material, the work function difference is GC = OF(substrate)-m for metal gate (3.14) 4)GC = OF(substrate)- OF(gate) for pojysilicon gate (3.15) This first component of the threshold voltage accounts for part of the voltage drop across the MOS system that is built-in. Now, the externally applied gate voltage must be changed to achieve surface inversion, i.e., to change the surface potential by - 2F. This will be the second component of the threshold voltage.  Another component of the applied gate voltage is necessary to offset the depletion 59 region charge, which is due to the fixed acceptor ions located in the depletion region near the surface. We can calculate the depletion region charge density at surface inversion (4S MOS Transistor =- IF) using (3.12). QBO 42q NA. Esi |.-2F (3.16) Note that if the substrate (body) is biased at a different voltage level than the source, which is at ground potential (reference), then the depletion region charge density can be expressed as a function of the source-to-substrate voltage VSB. QB= 2q NA Esi.- 2F + VSBI (3.17) The component that offsets the depletion region charge is then equal to - QB/COX, where Cox is the gate oxide capacitance per unit area. EOX =tx (3.18) Finally, we must consider the influence of a nonideal physical phenomenon which we have neglected until now. There always exists a fixed positive charge density Qox at the interface between the gate oxide and the silicon substrate, due to impurities and/or lattice imperfections at the interface. The gate voltage component that is necessary to offset this positive charge at the interface is - QOX/Cox. Now, we can combine all of these voltage components to find the threshold voltage. For zero substrate bias, the threshold voltage VM is expressed as follows: VTO=OGC-2 F-- ~OQBO Q0X (3.19) Fi OX For nonzero substrate bias, on the other hand, the depletion charge density term must be mouliiea to reflect tne inrluence ot VSB upon that cnarge, resulting in the ollowing generalized threshold voltage expression. VT = dGC- 2 0F Q. Cox (3.20) The generalized form of the threshold voltage can also be written as ~~~QBO Qx QB Q -QBOB VT CC 2OF COX c0 OX c0 =V'C - , (3.21) OX COX Note that in this case, the threshold voltage differs from VM only by an additive term. This substrate-bias term is a simple function of the material constants and of the source-to- substrate voltage VSB. 60 QB-QBO qNA.8 5 , *( -2F+VI- ( CHAPTER 3 C.C FSB 1 -I 2 0FI) (3.22) Thus, the most general expression of the threshold voltage VT can be found as follows: VT = VTO + F +VsBI I22 ) (3.23) where the parameter y =^ ~ q NA 'E~s, (3.24) is the substrate-bias(or body-effect) coefficient. The threshold voltage expression given in (3.23) can be used both for n-channel and p-channel MOS transistors. One must be careful, however, since some of the terms and coefficients in this equation have different polarities for the n-channel (nMOS) case and for the p-channel (pMOS) case. The reason for this polarity difference is that the substrate semiconductor is p-type in an n-channel MOSFET and n-type in a p-channel MOSFET. Specifically, * The substrate Fermi potential OF is negative in nMOS, positive in pMOS. * The depletion region charge densities QBO and QB are negative in nMOS, positive in pMOS. * The substrate bias coefficient is positive in nMOS, negative in pMOS. * The substrate bias voltage VSB is positive in nMOS, negative in pMOS. Typically, the threshold voltage of an enhancement-type n-channel MOSFET is a positive quantity, whereas the threshold voltage of a p-channel MOSFET is negative. Example 3.2. Calculate the threshold voltage VJO at VB = 0, for a polysilicon gate n-channel MOS transistor, with the following parameters: substrate doping density NA = 1016 cm-3 , polysilicon gate doping density ND = 2 x 1020 cm- 3, gate oxide thickness tx = 500 A, and oxide-interface fixed charge density N = 4 x 1010 cm- 2. First, calculate the Fermi potentials for the p-type substrate and for the n-type polysilicon gate: OF(substrate)= T In( n 0.026 V:(1.4_ 35 q NA) ~ 11 KSnce the doping density of the polysilicon gate is very high, the heavily doped n-type gate 61 aterial is expected to be degenerate. Thus, we may assume that the Fermi potential of the polysilicon gate is approximately equal to the conduction band potential, i.e., OF MOS Transistor ate) = 0.55 V. Now, calculate the work function difference between the gate and the channel: cOGC = OF(substrate)- F(gate) = -0.35 V -0.55 V = -0.90 V The depletion region charge density at VSB = 0 is found as follows: QBO = -. q' NA |-20F(substrate)J.Es =-2.1.6. 1019.1016.11.7.8.85.10-'4 1-2O0.351= -4.82 10-8 C/cm 2 The oxide-interface charge is: Q0X=q N0 X =1.6 10- 9 Cx4 10' 0 Cm-2 =64.10- 9 C/Cm2 The gate oxide capacitance per unit area is calculated using the dielectric constant of silicon dioxide and the oxide thickness t. = 397 8.85.10-14 F/cm = 7.03.-108 F/cm 2 ox tox 500 i0-8 cm Now, we can combine all components and calculate the threshold voltage. VTO GC - 2OF(substrate)- QBO C. Q C. = -0.90-(-0.70)-(-0.69)-0.09 = 0.40V In this simplified analysis, the doping concentrations of the source and the drain diffusion regions and the geometry (physical dimensions) of the channel region have no influence ,upon the threshold voltage Vv. Note that the exact value of the threshold voltage of an actual MOS transistor cannot be determined using (3.23) in most practical cases, due primarily to uncertainties and variations of the doping concentrations, the oxide thickness, and the fixed oxide-interface charge. The nominal value and the statistical range of the threshold voltage'for any MOS process are ultimately determined by direct measurements, which will be described later in Section 3.4. In most MOS fabrication processes, the threshold voltage can be adjusted 62 by selective dopant ion implantation into the channel region of the MOSFET. For n- channel MOSFETs, the threshold voltage is increased (made more positive) by adding CHAPTER 3 extra p-type impurities (acceptor ions). Alternatively, the threshold voltage of the n- channel MOSFET can be decreased (made more negative) by implanting n-type impu- rities (dopant ions) into the channel region. The amount of change in the threshold voltage as a result of extra implants can be approximated as follows. Let the density of implanted impurities be represented by N1 [cm- 2 ]. Assume that all implanted ions are electrically active, i.e., each ion contributes to the depletion region charge. Then, the threshold voltage Vm0 at zero substrate bias (VSB = 0) will be shifted by an amount of qNj1COx. This approximation obviously neglects the variation of the substrate Fermi level IF as the result of extra implan ut it nevertheless provides a fair estimate for the threshold voltage shift. Exercise 3.1 Consider the following p-channel MOSFET process: Substrate doping ND = 1015 cm-3, polysilicon gate doping density ND = 1020 cm-3, gate oxide thickness tx = 650 A, and oxide-interface charge density Nox = 2 x 1010 cm-2. Use Esi = 11.7EO and Eox = 397EO for the dielectric coefficients of silicon and silicon-dioxide, respectively. (a) Calculate the threshold voltage V, for VSB = 0. (b) Determine the type and the amount of channel ion implantation which are necessary to achieve a threshold voltage of V = - 2 V. Note that, using selective ion implantation into the channel, the threshold voltage of an n-channel MOSFET can also be made negative. This means that the resulting nMOS transistor will have a conducting channel at VGS = 0, enabling current flow between its source and drain terminals as long as VGS is larger than the negative threshold voltage. Such adevice is called a depletion-type (or normally-on) n-channel MOSFET. We will see several practical applications for depletion-type nMOS transistors in the design of MOS digital circuits. Except for its negative threshold voltage, the depletion-type n- channel MOSFET exhibits the same electrical behavior as the enhancement-type n- channel MOSFET. Figure 3.13 shows the conventional circuit symbols used for deple- tion-type n-channel MOSFETs.  63 D D rl r]~~~~~~~~~~~ MOS Transistor G -]( G|Ld VTO < S S S 4-Terminal Simplified Simplified Figure 3.13. Circuit symbols for n-channel depletion-type MOSFETs. Example 3.3. Consider the n-channel MOSFET process given in Example 3.2. In several digital circuit applications, the condition VSB = 0 cannot be guaranteed for all transistors. We will examine in this example how a nonzero source-to-substrate voltage VSB affects the threshold voltage of the MOS transistor. First, we must calculate the substrate-bias coefficient using the process parameters given in Example 3.2. Aidq7 sie 2 -L6 10-9.1016 -11.7 8.85 10 1 = 84 V C. ~~~7.03.-10-8.82V Now we compute and plot the threshold voltage VT as a function of the source-to- substrate voltage VSB. The voltage VSB will be assumed to vary between zero and 5 V. VT VT + I-2( F + VSBI 2F) =O.40 +.82 O. 7 +VSB I) It is seen that the threshold voltage variation is about 1.3 V over this range, which could present serious design problems if neglected. We will see in the following chapters that the substrate-bias effect is unavoidable in most digital circuits and that the circuit designer usually must take appropriate measures to account for and/or to compensate for the threshold voltage variations. 64 1.80 CHAPTER 3 1.60 E 1.40 G) 1.20 I 0 1.00 31 0 0.80 (n. 0.60 0.40 n on -1 0 1 2 3 4 5 6 Substrate Bias V (V) Variation of the threshold voltage as a function of the source-to-substrate voltage. MOSFET Operation: A Qualitative View The basic structure of the n-channel MOS (nMOS) transistor built on a p-type substrate was shown in Fig. 3.8. The MOSFET consists of a MOS capacitor with two p-n junctions placed immediately adjacent to the channel region that is controlled by the MOS gate. The carriers, i.e., electrons in an nMOS transistor, enter the structure through the source contact (S), leave through the drain (D), and are subject to the control of the gate (G) voltage. To ensure that both p-n junctions are reverse-biased initially, the substrate potential is kept lower than the other three terminal potentials. We have seen that when 0 < VGS < V, the gated region between the source and the drain is depleted; no carrier flow can be observed in the channel. As the gate voltage is increased beyond the threshold voltage (VGS > Vr), however, the mid-gap energy level at the surface is pulled below the Fermi level, causing the surface potential Os to turn positive and to invert the surface (Fig. 3.12). Once the inversion layer is established on the surface, an n-type conducting channel forms between the source and the drain, which is capable of carrying the drain current. Next, the influence of drain-to-source bias VDS and different modes of drain current flow will be examined for an nMOS transistor with VGS > V70. At VDS = 0, thermal equilibrium exists in the inverted channel region, and the drain current ID is equal to zero (Fig. 3.14(a)). If a small drain voltage VDS > 0 is applied, a drain current proportional to VDS will flow from the source to the drain through the conducting channel. The inversion layer, i.e., the channel, forms a continuous current path from the source to the drain. This operation mode is called the linear mode, or the linear region. Thus, in linear region operation, the channel region acts as a voltage-controlled resistor. The electron velocity, in the channel for this case is usually much lower than the drift velocity limit. Note that 65 as the drain voltage is increased, the inversion layer charge and the channel depth at the drain end start to decrease. Eventually, for VDS = VDSA7, the inversion charge at the drain MOS Transistor is reduced to zero, which is called the pinch-off point (Fig. 3.14i?). (a) VB VS= 0 VG>VT VD = VDSAT S I a,, EEE i yi i,, OXIDE i,,,,,,,,, i,,i rF q4 ,,,, DRAIN (b) I, < f V ~~~~~~~~~~~~~~~(n+) POINTa SUBSTRATE (p-S) DEPLETION REGION VB (c) VS Figure 3.14. Cross-sectional view of an n-channel (nMOS) transistor, (a) operating in the linear region, (b) operating at the edge of saturation, and (c) operating beyond saturation. 66 Beyond the pinch-off point, i.e., for VDS > VDSAT, a depleted surface region forms adjacent to the drain, and this depletion region grows toward the source with increasing CHAPTER 3 drain voltages. This operation mode of the MOSFET is called the saturationmode or the saturation region; For a MOSFET operating in the saturation region, the effective channel length is reduced as the inversion layer near the drain vanishes, while the channel-end voltage remains essentially constant and equal to VDSAT(Fig. 3.14(c)). Note that the pinched-off (depleted) section of the channel absorbs most of the excess voltage drop (VDS - VDSAT) and a high-field region forms between the channel-end and the drain boundary. Electrons arriving from the source to the channel-end are injected into the drain-depletion region and are accelerated toward the drain in this high electric field, usually reaching the drift velocity limit. The pinch-off event, or the disruption of the continuous channel under high drain bias, characterizes the saturation mode operation of the MOSFET. The influence of these operating conditions upon the external (terminal) current- voltage characteristics of the MOS transistor will be examined in the following section. A good understanding of these relationships, and of the factors involved therein, will be essential for the design and analysis of MOS digital circuits. 3.4. MOSFET Current-Voltage Characteristics The analytical derivation of the MOSFET current-voltage relationships for various bias conditions requires that several approximations be made to simplify the problem. Without these simplifying assumptions, analysis of the actual three-dimensional MOS system would become a very complex task and would prevent the derivation of closed- form current-voltage equations. In the' following, we will use the gradual channel approximation (GCA) for establishing the MOSFET current-voltage relationships, which will effectively reduce the analysis to a one-dimensional current-flow problem. This will allow us to devise relatively simple current equations that agree well with experimental results. As in every approximate approach, however, the GCA also has its limitations, especially for small-geometry MOSFETs. We will investigate the most significant limitations and examine some of the possible remedies. VDS Figure 3.15. Cross-sectional view of an n-channel transistor, operating in linear region.  Gradual ChannelApproximation 67 To begin with the current-flow analysis, consider the cross-sectional view of the n- MOS Transistor channel MOSFET operating in the linear mode, as shown in Fig. 3.15. Here, the source and the substrate terminals are connected to ground, i.e., Vs = VB =0. The gate-to-source voltage (VGS) and the drain-to-source voltage (VDS) are the external parameters control- ling the drain (channel) current ID. The gate-to-source voltage is set to be larger than the threshold voltage V. to create a conducting inversion layer between the source and the drain. We define the coordinate system for this structure such that the x-direction is perpendicular to the surface, pointing down into the substrate, and the y-direction is parallel to the surface. The y-coordinate origin (y = 0) is at the source end of the channel. * The channelvoltage with respect to the source will be denoted by Vc(y). Now assume that the threshold voltage V7. is constant along the entire channel region, between y = 0 and y = L. In reality, the threshold voltage changes along the channel since the channel voltage is not constant. Next, assume that the electric field component Ey along the y-coordinate is dominant compared to the electric field component Ex along the x-coordinate. This assumption will allow us to reduce the current-flow problem in the channel to the y- dimension only. Note that the boundary conditions for the channel voltage VC are: VC(y = ) = s = V,(y=L)=VDs (3.25) Also, it is assumed that the entire channel region between the source and the drain is inverted, i.e., VGS VTO (3.26) VGD = VGS - VDS VTO The channel current (drain current) ID is due to the electrons in the channel region traveling from the source to the drain under the influence of the lateral electric field component Ey. Since the current flow in the channel is primarily governed by the lateral drift of the mobile electron charge in the surface inversion layer, we will consider the amount and the bias-voltage dependence of this inversion layer in more detail. Let Q(y) be the total mobile electron charge in the surface inversion layer. This charge can be expressed as a function of the gate-to-source voltage VGS and of the channel voltage V(y) as follows: QY) =-C.X.[VGS v VC(Y)- VTO] (3.27) Figure 3.16 shows the spatial geometry of the surface inversion layer and indicates its significant dimensions. Note that the thickness of the inversion layer tapers off as we move from the source to the drain, since the gate-to-channel voltage causing surface inversion is smaller at the drain end. 68 CHAPTER 3 sou / dy Inversion layer (channel) Figure 3.16. Simplified geometry of the surface inversion layer (channel region). Now consider the incremental resistance dR of the differential channel segment shown in Fig. 3.16. Assuming that all mobile electrons in the inversion layer have a constant surface mobility jun, the incremental resistance can be expressed as follows. Note that the minus sign is due to the negative polarity of the inversion layer charge Q1. dy dR=- = Ql(y) (3.28) The electron surface mobility yun used in (3.28) depends on the doping concentration of the channel region, and its magnitude is typically about one-half of that of the bulk electron mobility. We will assume that the channel current density is uniform across this segment. According to our one-dimensional model, the channel (drain) current ID flows between the source and the drain regions in the y-coordinate direction. Applying Ohm's law for this segment yields the voltage drop along the incremental segment dy, in the y- direction. dV= ID dR dy (3.29) This equation can now be integrated along the channel, i.e., from y = 0 to y = L, using the boundary conditions given in (3.25). |ID dy =-W.iJ (y).dV Y (3.30) The left-hand side of this equation is simply equal to L ID. The integral on the right-hand side is evaluated by replacing Q 1(y) with (3.27). Thus,  69 ID-L=W-l -Cox ( VGS-VC-VTO) dV (3.31) MOS Transistor Assuming that the channel voltage V, is the only variable in (3.31) that depends on the position y, the drain current is found as follows. - 2 L.[2(GS -VTO)VDS-VDS] (3.32) Equation (3.32) represents the drain current ID as a simple second-order function of the two external voltages, VGS and VDS. This current equation can also be rewritten as ID 2 L[2 (VGs V)VDS VDS] (3.33) or ID.[2 2 (VGS-VTO)VDS vSI (3.34) where the parameters k and k' are defined as k'=,Un C0,, (3.35) and k=k'- (3.36) L The drain current equation given in (3.33) is the simplest analytical approximation for the MOSFET current-voltage relationship. Note that, in addition to the process- dependent constants k' and V, the current-voltage relationship is also affected by the device dimensions, Wand L. In fact, we will see that the ratio of WIL is one of the most important design parameters in MOS digital circuit design. Now, we must determine the region of validity for this equation and what this means for the practical use of the equation. Example 3.4. For an n-channel MOS transistor with un= 600 cm 2 /V s, CX=7 1o-8 F/cm 2 , W= 20 glm, L = 2 m and V = 1.0 V, examine the relationship between the drain current and the terminal voltages. 70 First, calculate the parameter k: CHAPTER 3 k =, C0 L-= 600cm 2 /V sx7 8 -10 F/cm 2 x 20 0.42 mA/V 2 L 20 gm Now, the current-voltage equation (3.34) can be written as follows. ID = 0.21 mA/V[2 ( VS-1. ) VDS -VDS] To examine the effect of the gate-to-source voltage and the drain-to-source voltage upon the drain current, we will plot ID as a function of VDS, for different (constant) values of VGS. It can easily be seen that the second-order current-voltage equation given above produces a set of inverted parabolas for each constant VGS value. 4 1 3 3 1 03 a) C- 2 10 0C 1 10-3 O 100 0 1 2 3 4 5 *6 Drain Voltage VDS (V) The drain current-drain voltage curves shown above reach their peak value for VDS = VGS - V. Beyond this maximum, each curve exhibits a negative differential conductance, which is not observed in actual MOSFET current-voltage measurements (section shown by the dashed lines). We must remember now that the drain current equation (3.32) has been derived under the following voltage assumptions, VGS VTO VGD VGS -VDS 2 VTO which guarantee that the entire channel region between the source and the drain is 71 inverted. This condition corresponds to the linearoperating mode for the MOSFET, which was examined qualitatively in Section 3.4. Hence, the current equation (3.32) is MOS Transistor valid only for the linear mode operation. Beyond the linear region boundary, i.e., for VDS values largerthan VGS - V70, the MOS transistor will be assumed to be in saturation.A different current-voltage expression will be necessary for the MOSFET operating in this region. Example 3.4 shows that the current equation (3.32) is not valid beyond the linear region/ saturation region boundary, i.e., for VDS VDSAT = VGS- VTO (3.37) Also, drain current measurements with constant VS show that the current ID does not show much variation as a function of the drain voltage. VDS beyond the saturation boundary, but rather remains approximately constant around the peak value reached for VDS = VDSAP This saturation drain current level can be found simply by substituting (3.37) for VDS in (3.32). ID(sat) = 2~,no L 2 (VGS VTO) (VGS VTO) (VGS VT.) ] =nC W V))(V (3.38) 2 L ) Thus, the drain current ID becomes a function only of the gate-to-source voltage VGS, beyond the saturation boundary. Note that this constant saturation current approximation is not very accurate in reality, and that the saturation-region drain current continues to have a certain dependence on the drain voltage. For simple hand calculations, however, (3.38) provides a sufficiently accurate approximation of the MOSFET drain (channel) current in saturation. Figure 3.17 shows the typical drain current versus drain voltage characteristics of an n-channel MOSFET, as described by the current equations (3.32) and (3.38). The parabolic boundary between the linear and the saturation regions is indicated here by the dashed line. The current-voltage characteristics of the MOS transistor can also be visualized by plotting the drain current as a function of the gate voltage, as shown in Fig. 3.18. This ID_ VGS transfer characteristic in saturation mode (VDS > VDSAT) provides a simple view of the drain current increasing as a second-order function of the gate-to- source voltage (cf. Equation (3.38)). The current is obviously equal to zero for any gate voltage smaller than the threshold voltage V. 72 CHAPTER 3 I 0 C.).Tm 3 Drain Voltage Figure 3.17. Basic current-voltage characteristics of an n-channel MOS transistor. I I I I 0 , D7 I B / /I C 0) V 08 0.. I/ I VTO , 1./ I I I Gate Voltage Figure 3.18. Drain current of the n-channel MOS transistor as a function of the gate-to-source voltage VGS, with VDS > VDSAT (transistor in saturation).  Channel Length Modulation 73 Next, we will examine the mechanisms of channel pinch-off and current flow in MOS Transistor saturation mode in more detail. Consider the inversion layer charge Qjthat represents the total mobile electron charge on the surface, given by (3.27). The inversion layer charge at the source end of the channel is Q(Y = ) = -COX (VGS VTO) (3.39) and the inversion layer charge at the drain end of the channel is Q,(y = L) = -C.X (VGS - VTO - VDS) (3.40). Note that at the edge of saturation, i.e., when the drain-to-source voltage reaches VDSA7, VDS = VDSAT = VGS - VTO (3.41) the inversion layer charge at the drain end becomes zero, according to (3.40). In reality, I the channel charge does not become exactly equal to zero (remember that the GCA is just a simple approximation of the actual conditions in the channel), but it indeed becomes very small. Qi(y = L) = (3.42) Thus, we can state that under the bias condition given in (3.41), the channel is pinched- off at the drain end, i.e., at y = L. The onset of the saturation mode operation in the MOSFET is signified by this pinch-off event. If the drain-to-source voltage VDS is increased even further beyond the saturation edge so that VDS > VDSA7, an even larger portion of the channel becomes pinched-off. Figure3.19. Channel length modulation in an n-channel MOSFET operation in saturation mode. 74 Consequently, the effective channel length (the length of the inversion layer where GCA is still valid) is reduced to CHAPTER 3 L'= L -AL (3.43) where AL is the length of the channel segment with Q = 0 (Fig. 3.19). Hence, the pinch- off point moves from the drain end of the channel toward the source with increasing drain-to-source voltages. The remaining portion of the channel between the pinch-off point and the drain will be in depletion mode. Since Q1(y) = 0 for L'< y < L, the channel voltage at the pinch-off point remains equal to VDSAT, i.e., VC(Y = = VDSAT (3.44) The electrons traveling from the source toward the drain traverse the inverted channel segment of length L', and then they are injected into the depletion region of length AL that separates the pinch-off point from the drain edge. As seen in Fig. 3.19, we can represent the inverted portion of the surface by a shortened channel, with a channel-end voltage of VDSAT. The gradual channel approximation is valid in this region; thus, the channel current can be found using (3.38). ID(sat) = Yn 01.(VGSVT)(45 2 L' Note that this current equation corresponds to a MOSFET with effective channel length L', operating in saturation. Thus, (3.45) accounts for the actual shortening of the channel, also called channel length modulation. Since L'< L, the saturation current calculated by using (3.45) will be larger than that found by using (3.38) under the same bias conditions. As L' decreases with increasing VDS, the saturation mode current ID(sat) will also increase with VDS. By approximating the effective channel length L'= L-AL as a function of the drain bias voltage, we can modify (3.45) to reflect this drain voltage dependence. First, rewrite the saturation current as follows: ID(sat) = i- o2 L GS TO) (3.46) The first term of this saturation current expression accounts for the channel modulation effect, while the rest of this expression is identical to (3.38). It can be shown that the channel length shortening AL is actually proportional to the square root of (VDS - VDSAT). AL oc VDS -VDAT (3.47) To simplify the analysis even further, we will use the following empirical relation 75 between AL and the drain-to-source voltage instead: MOS Transistor 1- L 1- A VDS (3.48) L Here, A is an empirical model parameter, and is called the channel length modulation coefficient. Assuming that AVDS 0. In this case, the influence of the nonzero VSB upon the current characteristics must be accounted for. Recall that the general expression (3.23) for the threshold voltage VT already includes the substrate bias term and, hence, it reflects the influence of the nonzero source-to-substrate voltage upon the device characteristics. VT (VSB) = VTO +Y (1 I2FI + VSB- )12F) (3.50) We can simply replace the threshold voltage terms in linear-mode and saturation-mode current equations with the more general VT(VSB) term. ID (in) = 2 LT [2 (VGS VT (VSB)) VDS VDS I (3.51) 2 ID (sa)= L *(GS-VT(VSB))2 (1 + AVDSV (3.52) In general, we will use only the term VT instead of VT(VSB) to express the general (substrate-bias dependent) threshold voltage. As already demonstrated in Example 3.3, the substrate-bias effect can significantly change the value of the threshold voltage and, hence, the current capability of the MOSFET. With this modification, we finally arrive at a complete first-order characterization of the drain (channel) current as a nonlinear function of the terminal voltages. ID = f(VGs, VDS, VBS) (3.53) In the following, we will repeat the current-voltage equations derived under the first- order gradual channel approximation (GCA), both for n-channel and for p-channel MOS transistors. Figure 3.21 shows the polarities of applied terminal voltages and the drain current directions. Note that the threshold voltage VTand the terminal voltages VGS, VDS, and VSB are all negative for the pMOS transistor. The parameter 1ip denotes the surface hole mobility in the pMOSFET.  77 D , S 3. + MOS Transistor VGS VSB GeoB JI 'D + Vs S D -uO n-channel MOSFET p-channel MOSFET Figure 3.21. Terminal voltages and currents of the nMOS and the pMOS transistor. Current-voltage equations of the n-channel MOSFET: ID = 0 for VGS < VT (3.54) ID~lin)=-Unox - I\1 2 L G[(S-VT)VDS VDS] for VGS 2 VT (3.55) and VDS < VGS -VT ID(sat)= - C- -W( VTGSP (I+ A VDS) for VGS VT 2 L (3.56) and VDS > VGS - VT Current-voltage equations of the p-channel MOSFET: ID =0 , for VGS > VT (3.57) p-. w2 ID (lin) = C L.2 (VGS-VT)VDS VDS] for VGS < VT (3.58) and VDS > VS -VT ID(sat) = P ox.-. (VS-VT) (1+.VDS) for VGS < VT (3.59) and VDS < VGS - VT 78 Measurement of Parameters CHAPTER 3 The MOSFET current-voltage equations (3.54) through (3.59), together with the general threshold voltage expression (3.50), are very useful for simple, first-order calculations of the currents and voltages in the nMOS and pMOS transistors. Because of several simplifications and approximations involved in their derivation, however, the accuracy of these current-voltage equations is fairly limited. To exploit the simplicity of the equations and to achieve the maximum possible accuracy in calculations, the parameters appearing in the current equations must be determined carefully, through experimental measurements. The model parameters that are used in (3.50) and in (3.54) through (3.59) are the zero-bias threshold voltage V.0, the substrate-bias coefficient , the channel