Lecture 2 Digital Electronic Systems (1) PDF

Higher Institute of Engineering, El Shorouk Biomedical and Systems Engineering Department BIS 471 and BIS 461 Digital Electronic Systems (1) Lecture 2 Dr. Mostafa Elhussien Dr. Mostafa Elhussien Digital Electronic Sy...

Higher Institute of Engineering, El Shorouk Biomedical and Systems Engineering Department BIS 471 and BIS 461 Digital Electronic Systems (1) Lecture 2 Dr. Mostafa Elhussien Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 1  Introduction to Digital Logic Gates A Digital Logic Gate is an electronic device that makes logical decisions based on digital signal levels present at its inputs. A digital logic gate may have more than one input but only has one digital output. Standard commercially available digital logic gates are available in two basic families, TTL such as the 7400 series, and CMOS which is the 4000 series of chips. Simple digital logic gates can also be made by connecting together diodes, transistors and resistors to produce DRL, Diode-Resistor logic gates, DTL, Diode-Transistor logic gates or ECL, Emitter-Coupled logic gates but these are less common now compared to the popular CMOS family. Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 2  Introduction to Digital Logic Gates AND OR A simple N-input RTL NOR Gate Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 3  Introduction to Digital Logic Gates The combination of several logic gates into one package is called Integrated Circuits (IC's) which can be grouped together into families according to the number of transistors or "gates" that they contain. For example, a simple AND gate my contain only a few individual transistors, were as a more complex microprocessor may contain many thousands of individual transistor gates. Integrated circuits are categorized according to the number of logic gates or the complexity of the circuits within a single chip with the general classification for the number of individual gates given as: Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 4  Introduction to Digital Logic Gates Type Count Example Small Scale Integration (SSI) Up to 10 transistors or a few gates within AND, OR, NOT a single package Medium Scale Integration (MSI) Between 10 and 100 transistors or tens of Perform digital operations such as adders gates and counters Large Scale Integration (LSI) Between 100 and 1,000 transistors or Perform specific digital operations such hundreds of gates as I/O chips, memory, arithmetic and logic units Very-Large Scale Integration (VLSI) Between 1,000 and 10,000 transistors or Perform computational operations such as thousands of gates processors, large memory arrays and programmable logic devices Super-Large Scale Integration (SLSI) Between 10,000 and 100,000 transistors Perform computational operations such as microprocessor chips, micro-controllers, basic PICs and calculators Ultra-Large Scale Integration (ULSI) More than 1 million transistors Used in computers CPUs, GPUs (video processors), micro-controllers, FPGAs and complex PICs. Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 5  Introduction to Digital Logic Gates Another level of integration which represents the complexity of the Integrated Circuit is known as the System-on-Chip or (SOC). Here the individual components such as the microprocessor, memory, peripherals, I/O logic etc, are all produced on a single piece of silicon, literally putting the word "integrated" into integrated circuit. These complete integrated chips which can contain up to 100 million individual silicon-CMOS transistor gates within one single package are generally used in mobile phones, digital cameras, micro-controllers, PIC's and robotic type applications. Benefits of SOC Reduce overall system cost Increase performance Lower power consumption Reduce size Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 6  Introduction to Digital Logic Gates Characterization of Digital ICs The various characteristics of digital ICs that can be used to compare their performance are: Speed of operation (propagation delay) Power dissipation (power consumption under static condition, O, 1; during the switching intervals or dynamic conditions) Current and voltage parameters (High level input and output voltages and low level input and output voltages) Noise immunity (measure of how much stray noise voltage the device can handle without giving any error) Fan-out (No. of gates that gate in HIGH output state can feed without voltage dropping by more than the allowable noise margin) Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 7  DC Supply Voltage The nominal value of the dc supply voltage for TTL (transistor-transistor logic) devices is +5 V. CMOS (complementary metal-oxide semiconductor) devices are available in different supply voltage categories: +5 V, +3.3 V, 2.5 V, and 1.8 V. Although omitted from logic diagrams for simplicity, the dc supply voltage is connected to the 𝑉𝐶𝐶 pin of an IC package, and ground is connected to the GND pin. Both voltage and ground are distributed internally to all elements within the package, as illustrated in Figure for a 14-pin package. Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 8  CMOS Logic Levels There are four different logic-level specifications: 𝑉𝐼𝐿 , 𝑉𝐼𝐻 , 𝑉𝑂𝐿 𝑎𝑛𝑑 𝑉𝑂𝐻 For CMOS circuits, the ranges of input voltages 𝑉𝐼𝐿 that can represent an acceptable LOW (logic 0) are from 0 V to 1.5 V for the +5 V logic and 0 V to 0.8 V for the 3.3 V logic. The ranges of input voltages 𝑉𝐼𝐻 that can represent an acceptable HIGH (logic 1) are from 3.5 V to 5 V for the 5 V logic and 2 V to 3.3 V for the 3.3 V logic, as indicated in Figure. Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 9  CMOS Logic Levels The ranges of values from 1.5 V to 3.5 V for 5 V logic and 0.8 V to 2 V for 3.3 V logic are regions of unpredictable performance, and values in these ranges are unacceptable. When an input voltage is in one of these ranges, it can be interpreted as either a HIGH or a LOW by the logic circuit. Therefore, CMOS gates cannot be operated reliably when the input voltages are in these unacceptable ranges. Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 10  CMOS Logic Levels The ranges of CMOS output voltages 𝑉𝑂𝐿 𝑎𝑛𝑑 𝑉𝑂𝐻 for both 5 V and 3.3 V logic are also shown in Figure. Notice that the minimum HIGH output voltage, 𝑉𝑂𝐻 𝑚𝑖𝑛 , is greater than the minimum HIGH input voltage, 𝑉𝐼𝐻 𝑚𝑖𝑛. Also, notice that the maximum LOW output voltage, 𝑉𝑂𝐿 𝑚𝑎𝑥 , is less than the maximum LOW input voltage, 𝑉𝐼𝐿 𝑚𝑎𝑥 Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 11  CMOS Logic Levels Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 12  TTL Logic Levels The input and output logic levels for TTL are given in Figure. Just as for CMOS, there are four different logic level specifications: 𝑉𝐼𝐿 , 𝑉𝐼𝐻 , 𝑉𝑂𝐿 𝑎𝑛𝑑 𝑉𝑂𝐻. Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 13  Noise Immunity Noise is unwanted voltage that is induced in electrical circuits and can present a threat to the proper operation of the circuit. Wires and other conductors within a system can pick up stray high-frequency electromagnetic radiation from adjacent conductors in which currents are changing rapidly or from many other sources external to the system. Also, power-line voltage fluctuation is a form of low-frequency noise. In order not to be adversely affected by noise, a logic circuit must have a certain amount of noise immunity. This is the ability to tolerate a certain amount of unwanted voltage fluctuation on its inputs without changing its output state. Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 14  Noise Immunity For example, if noise voltage causes the input of a 5 V CMOS gate to drop below 3.5 V in the HIGH state, the input is in the unacceptable region and operation is unpredictable. Thus, the gate may interpret the fluctuation below 3.5 V as a LOW level, as illustrated in Figure. Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 15  Noise Immunity For example, if noise voltage causes the input of a 5 V CMOS gate to drop below 3.5 V in the HIGH state, the input is in the unacceptable region and operation is unpredictable. Thus, the gate may interpret the fluctuation below 3.5 V as a LOW level, as illustrated in Figure. Similarly, if noise causes a gate input to go above 1.5 V in the LOW state, an uncertain condition is created, as illustrated in part (b). Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 16  Noise Margin A measure of a circuit’s noise immunity is called the noise margin, which is expressed in volts. There are two values of noise margin specified for a given logic circuit: The HIGH-level noise margin (𝑉𝑁𝐻 ) and the LOW-level noise margin (𝑉𝑁𝐿 ). These parameters are defined by the following equations: 𝑉𝑁𝐻 = 𝑉𝑂𝐻 𝑚𝑖𝑛 − 𝑉𝐼𝐻 𝑚𝑖𝑛 𝑉𝑁𝐿 = 𝑉𝐼𝐿 𝑚𝑎𝑥 − 𝑉𝑂𝐿 𝑚𝑎𝑥 Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 17  Noise Margin (Example) Determine the HIGH-level and LOW-level noise margins for CMOS and for TTL by using the information in Figures. Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 18  Noise Margin (Example) Determine the HIGH-level and LOW-level noise margins for CMOS and for TTL by using the information in Figures. For 5 V CMOS, 𝑉𝐼𝐻 𝑚𝑖𝑛 = 3.5 𝑉 𝑉𝐼𝐿 𝑚𝑎𝑥 = 1.5 𝑉 𝑉𝑂𝐻 𝑚𝑖𝑛 = 4.4 𝑉 𝑉𝑂𝐿 𝑚𝑎𝑥 = 0.33 𝑉 𝑉𝑁𝐻 = 𝑉𝑂𝐻 𝑚𝑖𝑛 − 𝑉𝐼𝐻 𝑚𝑖𝑛 = 4.4 − 3.5 = 0.9 𝑉 𝑉𝑁𝐿 = 𝑉𝐼𝐿 𝑚𝑎𝑥 − 𝑉𝑂𝐿 𝑚𝑎𝑥 = 1.5 − 0.33 = 1.17 𝑉 Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 19  Noise Margin (Example) Determine the HIGH-level and LOW-level noise margins for CMOS and for TTL by using the information in Figures. For TTL, 𝑉𝐼𝐻 𝑚𝑖𝑛 =2𝑉 𝑉𝐼𝐿 𝑚𝑎𝑥 = 0.8 𝑉 𝑉𝑂𝐻 𝑚𝑖𝑛 = 2.4 𝑉 𝑉𝑂𝐿 𝑚𝑎𝑥 = 0.4 𝑉 𝑉𝑁𝐻 = 𝑉𝑂𝐻 𝑚𝑖𝑛 − 𝑉𝐼𝐻 𝑚𝑖𝑛 = 2.4 − 2 = 0.4 𝑉 𝑉𝑁𝐿 = 𝑉𝐼𝐿 𝑚𝑎𝑥 − 𝑉𝑂𝐿 𝑚𝑎𝑥 = 0.8 − 0.4 = 0.4 𝑉 Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 20  Power Dissipation A logic gate draws current from the dc supply voltage source, as indicated in Figure. When the gate is in the HIGH output state, an amount of current designated by 𝐼𝐶𝐶𝐻 is drawn; and in the LOW output state, a different amount of current, 𝐼𝐶𝐶𝐿 , is drawn. As an example, if 𝐼𝐶𝐶𝐻 is specified as 1.5 mA when 𝑉𝐶𝐶 is 5 V and if the gate is in a static (nonchanging) HIGH output state, the power dissipation (PD) of the gate is 𝑃𝐷 = 𝑉𝐶𝐶 𝐼𝐶𝐶𝐻 = 5 × 1.5 = 7.5 𝑚𝑊 Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 21  Power Dissipation When a gate is pulsed, its output switches back and forth between HIGH and LOW, and the amount of supply current varies between 𝐼𝐶𝐶𝐻 and 𝐼𝐶𝐶𝐿. The average power dissipation depends on the duty cycle and is usually specified for a duty cycle of 50%. When the duty cycle is 50%, the output is HIGH half the time and LOW the other half. The average supply current is therefore 𝐼𝐶𝐶𝐻 + 𝐼𝐶𝐶𝐿 𝐼𝐶𝐶 = 2 The average power dissipation is 𝑃𝐷 = 𝑉𝐶𝐶 𝐼𝐶𝐶 Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 22  Power Dissipation (Example) A certain gate draws 2 mA when its output is HIGH and 3.6 mA when its output is LOW. What is its average power dissipation if VCC is 5 V and the gate is operated on a 50% duty cycle? Solution The average 𝐼𝐶𝐶 is 𝐼𝐶𝐶𝐻 + 𝐼𝐶𝐶𝐿 2 + 3.6 𝐼𝐶𝐶 = = = 2.8 𝜇𝐴 2 2 The average power dissipation is 𝑃𝐷 = 𝑉𝐶𝐶 𝐼𝐶𝐶 = 5 × 2.8 = 14 𝜇𝑊 Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 23  Power Dissipation Power dissipation in a TTL circuit is essentially constant over its range of operating frequencies. Power dissipation in CMOS, however, is frequency dependent. It is extremely low under static (dc) conditions and increases as the frequency increases. These characteristics are shown in the general curves of Figure. For example, the power dissipation of a low-power Schottky (LS) TTL gate is a constant 2.2 mW. The power dissipation of an HCMOS gate is 2.75 µW under static conditions and 170 µW at 100 kHz. Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 24  CMOS Circuits The abbreviation CMOS stands for complementary metal-oxide semiconductor. The term complementary refers to the use of two types of transistors in the output circuit. An n-channel MOSFET (MOS field-effect transistor) and a p-channel MOSFET are used. Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 25  The MOSFET Metal-oxide semiconductor field-effect transistors (MOSFETs) are the active switching elements in CMOS circuits. These devices differ greatly in construction and internal operation from bipolar junction transistors used in bipolar (TTL) circuits, but the switching action is basically the same: they function ideally as open or closed switches, depending on the input. Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 26  The MOSFET Figure (a) shows the symbols for both n-channel and p- channel MOSFETs. As indicated, the three terminals of a MOSFET are gate, drain, and source. When the gate voltage of an n-channel MOSFET is more positive than the source, the MOSFET is on (saturation), and there is, ideally, a closed switch between the drain and the source. When the gate-to-source voltage is zero, the MOSFET is off (cutoff), and there is, ideally, an open switch between the drain and the source. Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 27  The MOSFET The p-channel MOSFET operates with opposite voltage polarities, as shown in part (c). Sometimes a simplified MOSFET symbol as shown in Figure is used. Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 28  CMOS Inverter Complementary MOS (CMOS) logic uses the MOSFET in complementary pairs as its basic element. A complementary pair uses both p-channel and n- channel enhancement MOSFETs, as shown in the inverter circuit in Figure. Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 29  CMOS Inverter When a HIGH is applied to the input, as shown in When a LOW is applied to the input, as shown in Figure (a), the p-channel MOSFET Q1 is off and the Figure (b), Q1 is on and Q2 is off. n-channel MOSFET Q2 is on. This condition connects the output to +VDD (dc This condition connects the output to ground through supply voltage) through the on resistance of Q1, the on resistance of Q2, resulting in a LOW output. resulting in a HIGH output. Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 30  CMOS NAND Gate Figure shows a CMOS NAND gate with two inputs. Notice the arrangement of the complementary pairs (n- channel and p-channel MOSFETs). The operation of a CMOS NAND gate is as follows: Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 31  CMOS NOR Gate Figure shows a CMOS NOR gate with two inputs. Notice the arrangement of the complementary pairs. The operation of a CMOS NAND gate is as follows: Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 32  Open-Drain Gates The term open-drain means that the drain terminal of the output transistor is unconnected and must be connected externally to VDD through a load. An open-drain gate is the CMOS counterpart of an open-collector TTL gate. An open-drain output circuit is a single n-channel MOSFET as shown in Figure (a). An external pull-up resistor must be used, as shown in part (b), to produce a HIGH output state. Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 33  Tri-state CMOS Gates Tri-state outputs are available in both CMOS and TTL logic. The tri-state output combines the advantages of the totem-pole and open- collector circuits. As you recall, the three output states are HIGH, LOW, and high-impedance (high-Z). Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 34  Tri-state CMOS Gates When selected for normal logic-level operation, as determined by the state of the enable input, a tri- state circuit operates in the same way as a regular gate. When a tri-state circuit is selected for high-Z operation, the output is effectively disconnected from the rest of the circuit by the internal circuitry. Figure illustrates the operation of a tri-state circuit. The inverted triangle (𝛻) designates a tri-state output. Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 35  Tri-state CMOS Gates The circuitry in a tri-state CMOS gate, as shown in Figure, allows each of the output transistors Q1 and Q2 to be turned off at the same time, thus disconnecting the output from the rest of the circuit. When the enable input is LOW, the device is enabled for normal logic operation. When the enable input is HIGH, both Q1 and Q2 are off and the circuit is in the high-Z state. Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 36  Precautions for Handling CMOS All CMOS devices are subject to damage from electrostatic discharge (ESD). Therefore, they must be handled with special care. Review the following precautions: 1. All CMOS devices are shipped in conductive foam to prevent electrostatic charge buildup. When they are removed from the foam, the pins should not be touched. 2. The devices should be placed with pins down on a grounded surface, such as a metal plate, when removed from protective material. Do not place CMOS devices in polystyrene foam or plastic trays. 3. All tools, test equipment, and metal workbenches should be earth-grounded. A person working with CMOS devices should, in certain environments, have his or her wrist grounded with a length of cable and a large-value series resistor. The resistor prevents severe shock should the person come in contact with a voltage source. Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 37  Precautions for Handling CMOS All CMOS devices are subject to damage from electrostatic discharge (ESD). Therefore, they must be handled with special care. Review the following precautions: 4. Do not insert CMOS devices (or any other ICs) into sockets or PCBs with the power on. 5. All unused inputs should be connected to the supply voltage or ground as indicated in Figure. If left open, an input can acquire electrostatic charge and “float” to unpredicted levels. 6. After assembly on PCBs, protection should be provided by storing or shipping boards with their connectors in conductive foam. The CMOS input and output pins may also be protected with large- value resistors connected to ground. Dr. Mostafa Elhussien Digital Electronic Systems (1) Lec. 2 38