ARCHI 2 - Chapter 3 (1) PDF

Architecture of Computers L2ING Chapter 3 Notions about computer instructions 2024-2025 PLAN 1. Machine language, assembler, high-level language 2. Usual machine instructions 3. Compilation and assembly principle Assembly language ✓ This is...

Architecture of Computers L2ING Chapter 3 Notions about computer instructions 2024-2025 PLAN 1. Machine language, assembler, high-level language 2. Usual machine instructions 3. Compilation and assembly principle Assembly language ✓ This is the language closest to machine language ✓ Symbolic ✓ Logical & arithmetic instructions ✓ Loading, transfer instructions, etc. ✓ Each instruction represents a machine code ASSEMBLY INSTRUCTION Symbol operation Operand2, Oprerand1 Destination Source Example: Symbo operation operands ADD Op2, Op1 MOV Op2, Op1 NOT Op Common machine instructions Register Addressing This mode uses the CPU internal registers (Source: register, Destination: register) MOV AX, BX AX SI BX DI CX SP DX BP CPU SS IP CS PSW DS ES  Common machine instructions Immediate addressing In this addressing mode the operand (as value) appears in the instruction itself MOV AX, 5 AX 5 SI BX DI CX SP DX BP CPU SS IP CS PSW DS ES  Common machine instructions Direct addressing In this addressing mode, unlike immediate addressing mode, the operand contains the address of the data in memory MOV AX, [1234H] Memory 100 AX SI BX DI CX SP DX BP DS 1234H 100 CPU SS IP CS PSW DS ES  Common machine instructions Register Indirect Addressing (Based) Indirect addressing mode allows data to be accessed through a base register. MOV AX, [BX] Mémoire 500 AX SI 2000H BX DI CX SP DX BP DS 2000H 500 CPU SS IP CS PSW DS ES  Common machine instructions Register Indirect Addressing (Based) Indirect addressing mode allows data to be accessed through a base register. MOV AX, ES:[BX] Mémoire 200 AX SI 2000H BX DI CX SP DX BP DS 2000H 500 CPU SS IP CS PSW 2000H 200 DS ES ES  Common machine instructions Register Indirect Addressing (Based+Dep) Indirect addressing mode allows data to be accessed via a base register with displacement MOV AX, [BX+0002H] Mémoire 100 AX SI 2000H BX DI CX SP DX BP 2002H DS 2000H 100 500 CPU SS IP CS PSW DS ES  Common machine instructions Register Indirect Addressing (Based) Indirect addressing mode allows data to be accessed through a pointer register. MOV AX, [BP] Mémoire 250 AX SI 1000H BX DI SS 3000H 250 CX SP DX BP 3000H DS 2000H 500 CPU SS IP CS PSW 1000H 200 DS ES ES  Common machine instructions Indexed addressing Similar to based addressing, but, it uses the SI and DI index registers MOV AX, [SI] 400 AX SI 1500H Mémoire 2000H BX DI CX SP DX BP 2002H DS 2000H 100 500 CPU 1500H 400 SS IP CS PSW DS ES  Common machine instructions Indexed Addressing + Dep Similar to based addressing, but, it uses the SI and DI index registers with displacement MOV AX, [DI+0200H] Mémoire 300 AX SI 2000H BX DI 1500H CX SP DX BP DS 100 500 CPU 1700H 300 1500H SS IP CS PSW DS ES  Common machine instructions Index Based Addressing It is an addressing mode that combines both modes (based and indexed) MOV AX, [BX+SI] 500 AX SI 500H Mémoire 1000H BX DI 1500H CX SP DX BP DS 1500H 100 500 CPU 300 SS IP CS PSW DS ES  Common machine instructions Index Based Addressing (+Dep) It is an addressing mode that combines both modes (based and indexed) with displacement MOV AX, [BX+SI+0200H] 100 AX SI 500H Mémoire 1000H BX DI 1500H CX SP DX DI BP 1700H DS 1500H 100 500 CPU 300 SS IP CS PSW DS ES  Common machine instructions Index Based Addressing It is an addressing mode that combines both modes (pointer and indexed) MOV AX, [BP+SI] Mémoire 350 AX SI 500H 1000H BX DI 1500H SS 1500H 350 CX SP DX BP 1000H 1700H DS 1500H 100 500 CPU 300 SS IP CS PSW DS ES  Common machine instructions Indexed Based Addressing (+Dep) It is an addressing mode that combines both modes (pointer-based and indexed) with displacement MOV AX, [BP+SI+0200H] Mémoire 450 AX SI 500H 1700H 450 1000H BX DI 1500H SS 350 CX SP DX BP 1000H 1700H DS 1500H 100 500 CPU 300 SS IP CS PSW DS ES Common machine instructions INTERDICTIONS !! ✓ MOV Val_1, Val_2 ✓ MOV AL, BX ✓ MOV DS, ES ✓ MOV DS, 1000H ✓ MOV Mot_1, Mot_2 ✓ Immediate values ​can never be assigned to segment registers. Common machine instructions Mode adressage Opérande Segment Registre AX, BX, … // Immédiat Data (Val) // Direct [Offset] DS [BX] / [BX+Val] DS ou ES Basé / Basé avec déplacement [BP] / [BP+Val] SS Indexé [SI] ou [DI] DS Indexé avec déplacement [SI+Val] ou [DI+Val] DS [BX+SI] ou [BX+DI] DS Basé indexé [BP+SI] ou [BP+DI] SS [BX+SI+Val] ou [BX+DI+Val] DS Basé indexé avec déplacement [BP+SI+Val] ou [BP+DI+Val] SS Implicite Ex: (STD), (Loop ‘’CX’’) // Common machine instructions ✓ Transfer instructions (load, store) ✓ Logical instructions ✓ Arithmetic instructions ✓ Control instructions (jumps and branches)  Common machine instructions Transfer instructions (loading, storage) Allows data to be moved from one location (source) to another location (destination) ✓ Register to register ✓ Register to memory ✓ Memory to register “MOV” instruction Syntax: MOV Destination, Source  Common machine instructions Transfer instructions (loading, storage) Allows data to be moved from one location (source) to another location (destination) ✓ Register to register ✓ Register to memory ✓ Memory to register ‘’PUSH and POP’’ instruction Syntax: PUSH AX ; Transfers the contents of AX to the top of the stack POP BX ; Transfers the top of the stack to the BX register PUSHF ; Loads the PSW status register into the top of the stack POPF ; Transfers the top of the stack to the PSW register  Common machine instructions Transfer instructions (loading, storage) Allows data to be moved from one location (source) to another location (destination) ✓ Register to register ✓ Register to memory ✓ Memory to register Instruction ‘’XCHG’’ Syntax: XCHG Op1, Op2 (Commuter Op1 avec Op2) AX=1000 ; BX=2000 XCHG AX, BX AX=2000 ; BX=1000  Common machine instructions Transfer instructions (loading, storage) Allows data to be moved from one location (source) to another location (destination) ✓ Register to register ✓ Register to memory ✓ Memory to register ’IN and OUT’’ instruction Syntax: ✓ IN Acc, DX : send PORT of DX address to Acc ✓ OUT DX, Acc : return Acc to the PORT of DX address IN AL, DX / IN AX, DX OUT DX, AL / OUT DX, AX  Common machine instructions Transfer instructions (loading, storage) Allows data to be moved from one location (source) to another location (destination) ✓ Register to register ✓ Register to memory ✓ Memory to register ‘’LEA’’ instruction (Transfers the address of a memory word to a register) Syntax: LEA Reg, Mot_mem Mémoire LEA SI, Alpha → SI=1234H 1234H 100 Alpha MOV AX, Alpha → AX=100  Common machine instructions Logical (bit) instructions Allows data manipulation at the bit level. Basic logical operations are: ✓ AND, OR, NOT, XOR, TEST ✓ SHL, SHR ‘’’AND’’ instruction Syntax: AND Destination, Source ; Destination  Destination (AND) Source Destination: Register, memory word Source: Register, memory word, immediate  Common machine instructions Logical (bit) instructions Allows data manipulation at the bit level. Basic logical operations are: ✓ AND, OR, NOT, XOR, TEST ✓ SHL, SHR ‘’OR’’ instruction Syntax: OR Destination, Source ; Destination  Destination (OR) Source Destination: Register, memory word Source: Register, memory word, immediate  Common machine instructions Logical (bit) instructions Allows data manipulation at the bit level. Basic logical operations are: ✓ AND, OR, NOT, XOR, TEST ✓ SHL, SHR ‘’XOR’’ instruction Syntax: XOR Destination, Source ; Destination  Destination (XOR) Source Destination: Register, memory word Source: Register, memory word, immediate  Common machine instructions Logical (bit) instructions Allows data manipulation at the bit level. Basic logical operations are: ✓ AND, OR, NOT, XOR, TEST ✓ SHL, SHR ‘’NOT’’ instruction Syntax: NOT Op ; Op  (NOT) Op  Common machine instructions Logical (bit) instructions Allows data manipulation at the bit level. Basic logical operations are: ✓ AND, OR, NOT, XOR, TEST ✓ SHL, SHR ‘’TEST’’ instruction (Logical ‘’AND’’ operation that sets only FLAGs) Syntax: TEST Op1, Op2 Op1: Register, memory word Op2: Register, memory word, immediate  Common machine instructions Logical (bit) instructions Allows data manipulation at the bit level. Basic logical operations are: ✓ AND, OR, NOT, XOR, TEST ✓ SHL, SHR ‘’SHL’’ instruction : Shift left Syntax: SHL Destination, N Destination  Destination × 𝟐𝑵 Destination: Register, memory word N: Constant, CL register MOV AL, 04 (0100b) SHL AL, 1 AL=1000b =8 MOV BL, 8 SHL BL, 2 BL=32  Common machine instructions Logical (bit) instructions Allows data manipulation at the bit level. Basic logical operations are: ✓ AND, OR, NOT, XOR, TEST ✓ SHL, SHR ‘’SHR’’ instruction : Shift right Syntax: SHR Destination, N Destination  Destination / 𝟐𝑵 Destination: Register, memory word N: Constant, CL register MOV AL, 4 (0100b) SHR AL, 1 AL=0010b =2 MOV AL, 16 (010000b) MOV CL, 2 SHR AL, CL AL=000100b=4  Common machine instructions Arithmetic instructions ‘’ADD’’ instruction : Sum of two operands Syntax: ADD Destination, Source Destination  Destination + Source Destination: Register, memory word Source: Register, memory word, immediate value MOV AL, 03H ADD AX, [1234H] ; MOV BL, 02H ADD AX, [BX] ; ADD AL, BL ADD [1200H], 05H ; AL=AL+BL=05H  Common machine instructions Arithmetic instructions ‘’SUB’’ instruction : Subtraction between two operands Syntax: SUB Destination, Source Destination  Destination - Source Destination: Register, memory word Source: Register, memory word, immediate value SUB AX, BX ; SUB AX, [1234H] ; SUB AX, [BX] ; SUB [1200H], 05H ;  Common machine instructions Arithmetic instructions ‘’MUL’’ instruction : Multiplication between accumulator and operand Syntax: MUL Op Op : Register, memory word MUL BL ; BL × AL → AX MUL CX ; CX × AX → DX:AX MUL byte ptr [1234H] ; AX=AL × [1234H] MUL Op MUL word ptr [1234H] ; (DX:AX)=AX × [1234H] Op (1 octet) Op (2 octets) Result (AX) Result (DX:AX) AL × Op AX × Op  Common machine instructions Arithmetic instructions Instruction ‘’CMP’’ : Comparison between two operands Syntax: CMP Op1, Op2 Result  Op1 – Op2 Op1: Register, memory word Op2: Register, memory word, immediate value MOV AL, 40 MOV AH, 30 CMP AL, AH ; les FLAGs (ZF=0, SF=0) ---------------------------------------------- MOV AL, 30 MOV AH, 40 CMP AL, AH ; les FLAGs (ZF=0, SF=1)  Common machine instructions Jump or Plug Instructions ‘’JMP’’ instruction : Unconditional jump Syntax: JMP Label Result : unconditional jump to the line labeled ‘’Label’’, where ‘’Label’’ is an address identifier in the program Instruction 1; Instruction 2; JMP Etiq Instruction 4; Instruction 5; Etiq: Instruction 6; Instruction 7;  Common machine instructions Jump or Plug Instructions ‘’Jcond’’ instruction : Conditional jump Syntax: Jcond Label Result : jump to ‘’Label’’ if the condition ‘’cond’’ is verified (Jump if valid), otherwise, the execution continues sequentially to the next instruction Instruction 1; Jcond Etiq (Si cond valide, jamp vers Etiq) Instruction 2; Instruction 3; Etiq: Instruction 4;  Common machine instructions Instruction Condition JZ Label Saut si Zero JNZ Label Saut si not Zero JE Label Saut si égal JNE Label Saut si not égal JA Label Saut si supérieur Nombres JAE Label Saut si supérieur ou égal Non JB Label Saut si inférieur Signés JBE Label Saut si inférieur ou égal JG Label Saut si plus grand Nombres JGE Label Saut si plus grand ou égal Signés JL Label Plus petit JLE Label Plus petit ou égal Loop Répéter tant que CX ≠ 0  STACK SEGMENT/SS ✓ The stack is a part of central memory defined by the SS register ✓ Uses the LIFO (Last In First Out) principle 1 1 1 1 ✓ Stack addresses evolve unlike 1 1 1 0 traditional memory addresses 1 1 0 1 1 1 0 0 1 0 1 1 ✓ ALL stack accesses are 16-bits 1 0 1 0 1 0 0 1 ✓ SP is a register that points to the top 1 0 0 0 0 1 1 1 of the stack 0 1 1 0 SS=01 SP 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0  STACK SEGMENT/SS METHODS OF USE 15 0 STACK MEMORY Sequential Direct 00F8 EXPLICIT IMPLICIT BP register 00FA 00FC Empiler Procedure calls 00FE (PUSH) et and returns dépiler (POP) (save return SP 0100 des données addresses)  STACK SEGMENT/SS MOV AX, 0400H MOV SS, AX MOV SP, 0100H MOV BX, 1234H PUSH BX PUSH AX …. Treatment POP AX POP BX After PUSH SRC After POP DST SP=SP-2 DST=[SP] AX=0400 BX=1234 [SP]=SRC SP=SP+2 15 0 15 0 00FA 00FA Dépilement Empilement SP 00FC 0400 00FC 0400 00FE 1234 00FE 1234 0100 SP 0100  STACK SEGMENT/SS METHODS OF USE 15 0 0000 STACK MEMORY Sequential Direct 00F8 EXPLICIT IMPLICIT BP register 00FA 00FC Empiler Procedure calls 00FE (PUSH) et and returns dépiler (POP) (save return SP 0100 des données addresses)  STACK SEGMENT/SS MOV AX, 0400H MOV SS, AX MOV SP, 0100H PUSHF …. Treatment POPF After PUSHF After POPF SP=SP-2 PSW=[SP] PSW=PSW [SP]=PSW SP=SP+2 15 0 15 0 00FA 00FA Dépilement Empilement 00FC 00FC SP 00FE PSW 00FE PSW 0100 SP 0100  Exercise 1 Using the stack, write a sequence of instructions that forces the TF control status bit to 1 X X X X OF DF IF TF SF ZF X AF X PF X CF Solution Solution (for TF=0) PUSHF (empiler PSW register) PUSHF (empiler PSW register) POP AX (AX=PSW) POP AX (AX=PSW) OR AX, 0000000100000000b AND AX, 1111111011111111b PUSH AX PUSH AX POPF (Dépiler top of stack toward PSW) POPF (Dépiler top of stack toward PSW)  STACK SEGMENT/SS METHODS OF USE 15 0 0000 STACK MEMORY Sequential Direct 00F8 EXPLICIT IMPLICIT BP register 00FA 00FC Empiler Procedure calls 00FE (PUSH) et and returns dépiler (POP) (save return SP 0100 des données addresses)  STACK SEGMENT/SS EXPLICIT Procedure calls and returns (save return addresses) Procedure NEAR Procedure FAR (Intra-segment) (Inter-segment) NEAR return FAR return 10: ip1: Ins 1 Procedure NEAR 10: ip2: Ins 2 (Intra-segment) 10: ip3: CALL PROC 10: ip4: Ins 4 PROC 10:ip1_P: Inst 1 10:ip2_P: Inst 2 RET CS=10 SS=01 SP Syntax: CALL NEAR PTR Name_PROC (3 octets) SP=SP-2 [SP]=𝑰𝑷𝒓𝒆𝒕𝒐𝒖𝒓 (Empiler l’adresse de retour)  STACK SEGMENT/SS Procédure de type NEAR (Intra-segment) Main Program MOV AX, 0400H After CALL NEAR MOV SS, AX MOV SP, 0100H 00FA 𝑪𝑺𝑵 = 𝟑𝟓𝟎𝟎 𝑰𝑷𝑵 = 𝟎𝟑𝟎𝟎 00FC 3500:0200 CALL NEAR PTR USTHB SP 00FE 0203 (IP_Retour) 3500:0203 ADD AX, BX 0100 After RET Procedure USTHB 00FA USTHB PROC NEAR (Syntax) 𝑪𝑺𝑵 = 𝟑𝟓𝟎𝟎 3500:0300 MOV CX, 4 00FC 𝑰𝑷𝑵 = 𝟎𝟐𝟎𝟑 00FE 0203 RET (Return) SP 0100 USTHB ENDP 10: offset1: Ins 1 Procédure de type 10: offset2: Ins 2 FAR 10: offset3: CALL PROC (Inter-segment) 10: offset4: Ins 4 PROC 00: offset1: Ins 1 00: offset2: Ins 2 RET CS=10 SS=01 SP xxxxx Syntaxe: CALL FAR PTR Name_PROC (5 octets) CS=00 SP=SP-2 [SP]=𝑪𝑺𝒓𝒆𝒕𝒐𝒖𝒓 (Empiler le CS de retour) SP=SP-2 [SP]=𝑰𝑷𝒓𝒆𝒕𝒐𝒖𝒓 (Empiler le IP de retour)  STACK SEGMENT/SS Procédure de type FAR (Inter-segment) Main Program MOV AX, 0400H After CALL FAR MOV SS, AX MOV SP, 0100H 00FA 𝑪𝑺𝑵 = 𝟓𝟎𝟎𝟎 𝑰𝑷𝑵 = 𝟎𝟒𝟎𝟎 SP 00FC 0205 (IP_Retour) 3500:0200 CALL FAR PTR USTHB 00FE 3500 (CS_Retour) 3500:0205 ADD AX, BX 0100 Procedure USTHB USTHB PROC FAR (Syntax) After RET 5000:0400 MOV CX, 4 00FA 𝑪𝑺𝑵 = 𝟑𝟓𝟎𝟎 RET (Return) 00FC 0205 𝑰𝑷𝑵 = 𝟎𝟐𝟎𝟓 USTHB ENDP 00FE 3500 SP 0100  STACK SEGMENT/SS METHODS OF USE 15 0 0000 STACK MEMORY Séquentiel Direct 00F8 EXPLICIT IMPLICIT BP register 00FA 00FC Empiler Procedure calls 00FE (PUSH) et and returns dépiler (POP) (save return SP 0100 des données addresses) Stack - Summary METHODS OF USE STACK MEMORY Sequential Direct EXPLICIT IMPLICIT BP register [BP], [BP+2], …. PUSH AX POP BX NEAR/RET FAR/RET Actions Actions CALL CALL Sp Sp-2 BX [Sp] Sp Sp-2 Sp Sp-2 [Sp] AX Sp Sp+2 [Sp] IP_r [Sp] CS_r Sp Sp-2 RET [Sp] IP_r IP_N [Sp] Sp Sp+2  Principle of compilation and assembly High-level language Low level closest Lowest Level to the machine (Machine 0/1) Program written in Program written in H-L Assembly language Machine code MOV AX, BX 0011101010100 int Number=5; MOV CX, N 1011001010001 C String=‘’abc’’; Scanner scan; ADD DX, 0020h 0101001010100 P MUL BL 1010101000000 System.out.print; DIV BL 00111110101011 U Compiler assembleur MOV AL, a 0011101010100 SHL AL, 1 1011001010001 C MOV BL, b P:=(a*2)+(b*2); SHL BL, 1 0101001010100 P 1010101000000 ADD AL, BL MOV P, AL 00111110101011 U  Machine language MACHINE INSTRUCTION It is the only language that can be executed directly by the microprocessor. This language is difficult to master since each instruction is coded by a specific sequence of bits (Binary Digit). Field Depends on Depends on Depends on required The instruction The instruction The instruction 7 0 7 0 7 0 7 0 7 0 7 0 Op.Code + Addressing mode Dept bas Dept haut Data bas Data haut Dept. Bas: low byte of the displacement cited in the addressing mode of the memory operand Dept. Haut: high byte of the displacement cited in the addressing mode of the memory operand Data. Bas: low byte of the immediate data cited in the instruction Data. Haut: high byte of the immediate data cited in the instruction  Machine language MACHINE INSTRUCTION Field Depends on Depends on Depends on required The instruction The instruction The instruction 7 0 7 0 7 0 7 0 7 0 7 0 Op.Code D W MOD REG R/M Dept bas Dept haut Data bas Data haut D (Destination): Indicates whether the register is a source (D=0) or destination (D=1) W (Width): Indicates whether the operand is 8 (W=0) bits or 16 bits (W=1) [D, REG] is a pair that works together [MOD, R/M] is a pair that works together  MOD REG-R/M 00 01 10 w=0 11 w=1 000 [BX+SI]/DS Depl.8[BX+SI]/DS Depl.16[BX+SI]/DS AL AX 001 [BX+DI]/DS Depl.8[BX+DI]/DS Depl.16[BX+DI]/DS CL CX 010 [BP+SI]/SS Depl.8[BP+SI]/SS Depl.16[BP+SI]/SS DL DX 011 [BP+DI]/SS Depl.8[BP+DI]/SS Depl.16[BP+DI]/SS BL BX 100 [SI]/DS Depl.8[SI]/DS Depl.16[SI]/DS AH SP 101 [DI]/DS Depl.8[DI]/DS Depl.16[DI]/DS CH BP 110 Depl.16/DS Depl.8[BP]/SS Depl.16[BP]/SS DH SI 111 [BX]/DS Depl.8[BX]/DS Depl.16[BX]/DS BH DI  Machine language Op.Code D W MOD REG R/M Dept bas Dept haut Data bas Data haut ✓ Machine codes for instructions are generated using machine code generation rules ✓ Each instruction has several rules  Machine language Op.Code D W MOD REG R/M Dept bas Dept haut Data bas Data haut MOV instruction MOV R(M), R(M) 100010DW MOD REG R/M Depl B Depl H MOV R(M), Data 1100011W MOD 000 R/M Depl. B Depl. H Data. B Data. H MOV R, Data 1011 W REG Data. B Data. H MOV Acc, M 1010 000W Depl. B Depl. H MOV M, Acc 1010 001W Depl. B Depl. H MOV R:S, R(M) 1000 1110 MOD 0SR R/M Depl. B Depl. H MOV R(M), R:S 1000 1100 MOD 0SR R/M Depl. B Depl. H SR: Segment Registre  Machine language Example: MOV BL, [SI] MOV R(M), R(M) 100010DW MOD REG R/M Depl B Depl H D (Destination): ✓ D=1; destination registre 1000 1010 MOD REG R/M ✓ D=0; source registre MOV Reg.8, Reg8.(Mem.8) W (Width): ✓ W=1; argument 16 bits 1000 1010 MOD 011 R/M ✓ W=0; argument 8 bits MOV BL, Reg8.(Mem.8) [D,REG] 1000 1010 00 011 100 ✓ REG=011 MOV BL, [SI] [MOD,R/M] ✓ MOD=00 (no displacement) ✓ R/M=100 ([SI]) 8A 1C  Machine language Example: MOV [BX], CX (i.e, MOV Mem, Reg) MOV R(M), R(M) 100010DW MOD REG R/M Depl B Depl H D (Destination): ✓ D=1; destination registre 1000 1001 MOD REG R/M ✓ D=0; source registre MOV Mem.16, Reg16 W (Width): ✓ W=1; argument 16 bits 1000 1001 MOD 001 R/M ✓ W=0; argument 8 bits MOV Mem.16, CX [D,REG] 1000 1001 00 001 111 ✓ REG=001 MOV [BX], CX [MOD,R/M] ✓ MOD=00 ✓ R/M=111 89 0F  Machine language Example: MOV DX, [BX+1234H] MOV R(M), R(M) 100010DW MOD REG R/M Depl B Depl H D (Destination): ✓ D=1; destination registre 1000 1011 MOD REG R/M ✓ D=0; source registre MOV Reg.16, Reg16.(Mem.16) W (Width): ✓ W=1; argument 16 bits 1000 1011 MOD 010 R/M ✓ W=0; argument 8 bits MOV DX, Reg.16(Mem.16) [D,REG] 1000 1011 10 010 111 ✓ REG=010 MOV DX, [BX+Dep.16] [MOD,R/M] 1000 1011 10 010 111 00110100 00010010 ✓ MOD=10 MOV DX, [BX+1234H] ✓ R/M=111 8B 97 34 12  Machine language Example: MOV [DI+1234H], CX MOV R(M), R(M) 100010DW MOD REG R/M Depl B Depl H D (Destination): ✓ D=1; destination registre 1000 1001 MOD REG R/M ✓ D=0; source registre MOV Mem.16, Reg16.(Mem.16) W (Width): ✓ W=1; argument 16 bits 1000 1001 MOD 001 R/M ✓ W=0; argument 8 bits MOV Mem.16, CX [D,REG] 1000 1001 10 001 101 ✓ REG=001 MOV [DI+Dep.16], CX [MOD,R/M] 1000 1001 10 001 101 00110100 00010010 ✓ MOD=10 MOV [DI+1234H], CX ✓ R/M=101 89 8D 34 12  Machine language Example: MOV CX, AX (i.e, MOV Reg, Reg) MOV R(M), R(M) 100010DW MOD REG R/M Depl B Depl H D (Destination): ✓ D=1; destination registre 1000 100W MOD REG R/M ✓ D=0; source registre 1000 101W MOD REG R/M W (Width): 1000 1001 MOD 000 R/M ✓ W=1; argument 16 bits 1000 1011 MOD 001 R/M ✓ W=0; argument 8 bits 1000 1001 11 000 001 1000 1011 11 001 000 89 C1 8B C8  Machine language Example: MOV DX, FE00H (i.e, MOV Reg, Data) MOV R(M), Data 1100011W MOD 000 R/M Depl. B Depl. H Data. B Data. H MOV R, Data 1011 W REG Data. B Data. H 1011 1 010 0000 0000 1111 1110 = BA 00 FE (Rule 3) 1100011 1 11 000 010 0000 0000 1111 1110 = C7 C2 00 FE (Rule 2) R3 is an optimized rule  Machine language Example: MOV [SI+FFFEH], 6789H MOV R(M), Data 1100011W MOD 000 R/M Depl. B Depl. H Data. B Data. H 11000111 10000100 11111110 11111111 10001001 0110 0111= C7 84 FE FF 89 67  Machine language Example: MOV usthb, 67H ; With EA(usthb)=6648H MOV R(M), Data 1100011W MOD 000 R/M Depl. B Depl. H Data. B Data. H 11000110 00 000 110 0100 1000 0110 0110 0110 0111 = C6 06 48 66 67  Machine language Exemple: MOV AL, usthb AE(usthb)=6648H MOV R(M), R(M) 100010DW MOD REG R/M Depl B Depl H R1 : Size of instruction = 4 octets MOV Acc, M 1010 000W Depl. B Depl. H R4 : Size of instruction = 3 octets R4: 1010 0000 0100 1000 0110 0110 = A0 48 66 Machine language MOV M, Acc (R5) 1010 001W Depl. B Depl. H  Machine language Example: MOV DS, AX MOV RS, R(M) 1000 1110 MOD 0SR R/M Depl. B Depl. H Registre Segment Machine code (SR) ES 00 CS 01 SS 10 DS 11 1000 1110 11 011 000 = 8E D8  Machine language Op.Code D W MOD REG R/M Dept bas Dept haut Data bas Data haut ADD instruction ADD R(M), R(M) 000000DW MOD REG R/M Depl B Depl H ADD R(M), Data 1000 00SW MOD 000 R/M Depl. B Depl. H Data. B Data. H S: Sign Extended ADD Acc, Data 0000 010W Data. B Data. H  Machine language Example: ADD BX, [SI] ADD R(M), R(M) 1000 10DW MOD REG R/M Depl B Depl H 1000 0011 00 011 100 = 83 1C Example: ADD AX, 1234H ADD Acc, Data 0000 010W Data. B Data. H 0000 0101 0011 0100 0001 0010 = 05 34 12  Machine language Example: ADD BX, 0036H ADD R(M), Data 1000 00SW MOD 000 R/M Depl. B Depl. H Data. B Data. H S: Sign Extended 1000 0001 11 000 011 0011 0110 0000 0000 = 81 C3 36 00 0036H = 0000 0000 0011 0110 1000 0011 11 000 011 0011 0110 = 83 C3 36 Example: ADD CX, FF80H ADD R(M), Data 1000 00SW MOD 000 R/M Depl. B Depl. H Data. B Data. H S: Sign Extended FF80H = 1111 1111 1000 0000 1000 0011 11 000 001 1000 1000 = 83 C1 80