Assembling and Disassembling PDF

Assembling by Hand Content  Content Assembling by hand  What is assembling? An assembler is a program, which translates an assembly program into the corresponding executable machine code (and a disassembler does the opposite). So when you Submit code in ARMlite you assemble it into...

Assembling by Hand Content  Content Assembling by hand  What is assembling? An assembler is a program, which translates an assembly program into the corresponding executable machine code (and a disassembler does the opposite). So when you Submit code in ARMlite you assemble it into machine code which will appear in memory as binary/hex or decimal Each line of code has been translated into machine language (in binary)  Machine Code Computer executable programs are in binary forms, known as machine code, object code or executable code, often indicated by an unequivocal file extension such as.obj or.exe.  Assembly language Assembly programs are the same as machine code, but in a symbolic form which improves the readability and reveals the operations to be conducted in terms of the CPU instructions.  Assembly language High Level Language Assembly Language Machine Language Hardware A compiler is a program (or set of programs), which transforms higher-level language programs into assembly or machine code for execution.  Suitable for computers to Suitable for people to read and write store and execute Compiler Assembler/Disassembler High-level program Assembly program Machine code.c,.cpp,.java.arm.obj,.exe v=x+y-z; Program faults caused by incorrect compiler behaviour can be very difficult to track down and work around; therefore, compiler implementers invest significant effort to ensure the correctness of their software.  Suitable for computers to Suitable for people to read and write store and execute Compiler Assembler/Disassembler High-level program Assembly program Machine code.c,.cpp,.java.arm.obj,.exe v=x+y-z; MOV R1, #value1 ADD R1,R1, #value2 SUB R1, R1, #value3 Program faults caused by incorrect compiler behaviour can be very difficult to track down and work around; therefore, compiler implementers invest significant effort to ensure the correctness of their software.  Opcode{conditions}{flags} Rd, Rn, operand2 where: {cond} is a optional two-letter condition e.g.EQ {flags} is an optional additional flag e.g. S Rd is the destination register Rn is the first source register (0000 if there is only 1 operand) Operand2 is the flexible second register (or Rn if there is only 1 operand) e.g. ADD R2, R3, #4 10 Instruction Data Sheet  Assembling Machine code ARM (and ARMlite) instruction come in the following format: Opcode{conditions}{flags} Rd, Rn, operand2 where: {cond} is a optional two-letter condition e.g.EQ {flags} is an optional additional flag e.g. S Rd is the destination register Rn is the first source register Operand2 is the flexible second register Example MOV R2, R1 To assemble this line of code by hand we need to refer to the ARM data sheet MOV R2, R1 MOV R2, R1  MOV R2, R1 31 28 27 26 25 24 21 20 19 16 15 12 11 0 1110 Cond 00 I Opcode S Rn Rd Operand2  MOV R2, R1 31 28 27 26 25 24 21 20 19 16 15 12 11 0 31 1110 28 27 26 25 24 21 20 19 16 15 12 11 0 1110 Cond 00 00 I Opcode S Rn Rd Operand2 Cond 00 I Opcode S Rn Rd Operand2  MOV R2, R1 31 31 28 28 27 27 2626 25 25 24 24 21 21 20 20 19 19 16 16 15 15 12 12 11 11 0 0 1110 00 1110 Cond 00 00 I0 Opcode S Rn Rd Operand2 Cond 00 I Opcode S Rn Rd Operand2  MOV R2, R1 31 31 28 28 27 27 2626 25 25 24 24 21 21 20 20 19 19 16 16 15 15 12 12 11 11 0 0 1110 00 0 1Cond 110 00 00 I0 1101 Opcode S Rn Rd Operand2 Cond 00 I Opcode S Rn Rd Operand2  MOV R2, R1 Format: MOV Rd, No Rn so use 0000 31 31 28 1110 28 27 26 27 00 26 25 25 0 24 21 24 1101 21 20 20 19 19 16 16 15 15 12 12 11 11 0 0 1110 Cond 00 00 I0 1101 Opcode S0 0000 Rn Rd Operand2 Cond 00 I Opcode S Rn Rd Operand2  MOV R2, R1 31 28 27 26 25 24 21 20 19 16 15 12 11 0 31 1110 28 27 00 26 25 0 24 1101 21 20 0 19 0001 16 15 12 11 0 1Cond 110 00 00 I0 1101 Opcode S0 0000 Rn 0010 Rd Operand2 Cond 00 I Opcode S Rn Rd Operand2  MOV R2, R1 3131 28 28 27 26 27 26 25 25 24 21 24 21 20 20 19 16 19 16 15 12 15 12 11 11 00 31 11 11 11 00 28 27 00 00 26 25 00 24 1101 1101 21 20 00 19 0001 0001 16 15 0010 12 11 0 1Cond Cond 110 00 00 00 II0 1101 Opcode Opcode SS0 0000 Rn Rn 0010 Rd Rd 000000000001 Operand2 Operand2 Cond 00 I Opcode S Rn Rd Operand2  MOV R2, R1 3131 28 28 27 26 27 26 25 25 24 21 24 21 20 20 19 16 19 16 15 12 15 12 11 11 00 31 11 11 11 00 28 27 00 00 26 25 00 24 1101 1101 21 20 00 19 0001 0001 16 15 0010 12 11 0 1Cond Cond 110 00 00 00 II0 1101 Opcode Opcode SS0 0000 Rn Rn 0010 Rd Rd 000000000001 Operand2 Operand2 Cond 00 I Opcode S Rn Rd Operand2 1110 0001 1010 0000 0010 0000 0000 0001 0xE1A02001  MOV R2, R1 1110 0001 1010 0000 0010 0000 0000 0001 0xE1A02001 ADD R3, R2, R1 ADD R3, R2, R1  ADD R3, R2, R1 31 28 27 26 25 24 21 20 19 16 15 12 11 0 1110 Cond 00 I Opcode S Rn Rd Operand2  ADD R3, R2, R1 31 28 27 26 25 24 21 20 19 16 15 12 11 0 31 1110 28 27 26 25 24 21 20 19 16 15 12 11 0 1110 Cond 00 00 I Opcode S Rn Rd Operand2 Cond 00 I Opcode S Rn Rd Operand2  ADD R3, R2, R1 31 31 28 28 27 27 2626 25 25 24 24 21 21 20 20 19 19 16 16 15 15 12 12 11 11 0 0 1110 00 1110 Cond 00 00 I0 Opcode S Rn Rd Operand2 Cond 00 I Opcode S Rn Rd Operand2  ADD R3, R2, R1 31 31 28 28 27 27 2626 25 25 24 24 21 21 20 20 19 19 16 16 15 15 12 12 11 11 0 0 1110 00 0 1Cond 110 00 00 I0 0100 Opcode S Rn Rd Operand2 Cond 00 I Opcode S Rn Rd Operand2  ADD R3, R2, R1 31 31 28 1110 28 27 26 27 00 26 25 25 0 24 21 24 1101 21 20 20 19 19 16 16 15 15 12 12 11 11 0 0 1110 Cond 00 00 I0 0100 Opcode S0 Rn Rd Operand2 Cond 00 I Opcode S Rn Rd Operand2  ADD R3, R2, R1 31 31 28 1110 28 27 26 27 00 26 25 25 0 24 21 24 1101 21 20 20 19 19 16 16 15 15 12 12 11 11 0 0 1110 Cond 00 00 I0 0100 Opcode S0 0010 Rn Rd Operand2 Cond 00 I Opcode S Rn Rd Operand2  ADD R3, R2, R1 31 28 27 26 25 24 21 20 19 16 15 12 11 0 31 1110 28 27 00 26 25 0 24 1101 21 20 0 19 0001 16 15 12 11 0 1Cond 110 00 00 I0 0100 Opcode S0 0000 Rn 0011 Rd Operand2 Cond 00 I Opcode S Rn Rd Operand2  ADD R3, R2, R1 3131 28 28 27 26 27 26 25 25 24 21 24 21 20 20 19 16 19 16 15 12 15 12 11 11 00 31 11 11 11 00 28 27 00 00 26 25 00 24 1101 1101 21 20 00 19 0001 0001 16 15 0010 12 11 0 1Cond Cond 110 00 00 00 II0 0100 Opcode Opcode SS0 0000 Rn Rn 0010 Rd Rd 000000000001 Operand2 Operand2 Cond 00 I Opcode S Rn Rd Operand2  ADD R3, R2, R1 3131 28 28 27 26 27 26 25 25 24 21 24 21 20 20 19 16 19 16 15 12 15 12 11 11 00 31 11 11 11 00 28 27 00 00 26 25 00 24 1101 1101 21 20 00 19 0001 0001 16 15 0010 12 11 0 1Cond Cond 110 00 00 00 II0 0100 Opcode Opcode SS0 0010 Rn Rn 0011 Rd Rd 000000000001 Operand2 Operand2 Cond 00 I Opcode S Rn Rd Operand2 1110 0000 1000 0010 0011 0000 0000 0001 0xE0823001  Disassembling Machine code To disassemble machine code by hand we need to refer to the ARM data sheet Example 0xE3A02003  31 31 28 28 27 26 27 26 25 25 24 21 24 21 20 20 19 16 19 16 15 12 15 12 11 11 00 31 11 11 11 00 28 27 00 00 26 25 00 24 1101 1101 21 20 00 19 0001 0001 16 15 0010 12 11 0 Cond Cond 00 00 II Opcode Opcode SS Rn Rn Rd Rd Operand2 Operand2 Cond 00 I Opcode S Rn Rd Operand2 0xE3A02003  31 28 27 26 31 31 11 11 11 00 28 28 2626 2727 00 00 25 2525 00 24 21 2424 21 1101 21 1101 20 2020 00 19 16 1919 0001 0001 16 16 15 12 15 15 0010 12 12 11 11 11 00 0 Cond Cond 00 00 II Opcode Opcode SS Rn Rn Rd Rd Operand2 Operand2 Cond 00 I Opcode S Rn Rd Operand2 0xE3A02003 = 1110 00 1 1101 0 0000 0010 000000000011 3131 28 28 27 26 27 26 25 25 24 21 24 21 20 20 19 16 19 16 15 12 15 12 11 11 00 31 11 11 11 00 28 27 00 00 26 25 00 24 1101 1101 21 20 00 19 0001 0001 16 15 0010 12 11 0 1Cond Cond 110 00 00 00 I1 I 1101 Opcode Opcode SS0 0000 Rn Rn 0010 Rd Rd 00000000011 Operand2 Operand2 Cond 00 I Opcode S Rn Rd Operand2 0xE3A02003 = 1110 00 1 1101 0 0000 0010 000000000011  31 31 28 28 27 26 27 26 25 25 24 21 24 21 20 20 19 16 19 16 15 12 15 12 11 11 00 31 11 11 11 00 28 27 00 00 26 25 00 24 1101 1101 21 20 00 19 0001 0001 16 15 0010 12 11 0 1 Cond Cond 110 00 00 00 I1 I 1101 Opcode Opcode SS0 0000 Rn Rn 0010 Rd Rd 00000000011 Operand2 Operand2 Cond 00 I Opcode S Rn Rd Operand2 0xE3A02003 = 1110 00 1 1101 0 0000 0010 000000000011  Condition: Always 00 I: immediate 31 31 28 28 27 26 27 26 25 25 24 21 24 21 20 20 19 16 19 16 15 12 15 12 11 11 00 31 11 11 11 00 28 27 00 00 26 25 00 24 1101 1101 21 20 00 19 0001 0001 16 15 0010 12 11 0 1 Cond Cond 110 00 00 00 I1 I 1101 Opcode Opcode SS0 0000 Rn Rn 0010 Rd Rd 00000000011 Operand2 Operand2 Cond 00 I Opcode S Rn Rd Operand2 0xE3A02003 = 1110 00 1 1101 0 0000 0010 000000000011  Condition: Always 00 I: immediate Opcode: MOV 31 31 28 28 27 26 27 26 25 25 24 21 24 21 20 20 19 16 19 16 15 12 15 12 11 11 00 31 11 11 11 00 28 27 00 00 26 25 00 24 1101 1101 21 20 00 19 0001 0001 16 15 0010 12 11 0 1 Cond Cond 110 00 00 00 I1 I 1101 Opcode Opcode SS0 0000 Rn Rn 0010 Rd Rd 00000000011 Operand2 Operand2 Cond 00 I Opcode S Rn Rd Operand2 0xE3A02003 = 1110 00 1 1101 0 0000 0010 000000000011  Condition: Always 00 I: immediate Opcode: MOV S: Set condition Code = do not use condition codes 31 31 28 28 27 26 27 26 25 25 24 21 24 21 20 20 19 16 19 16 15 12 15 12 11 11 00 31 11 11 11 00 28 27 00 00 26 25 00 24 1101 1101 21 20 00 19 0001 0001 16 15 0010 12 11 0 1 Cond Cond 110 00 00 00 I1 I 1101 Opcode Opcode SS0 0000 Rn Rn 0010 Rd Rd 00000000011 Operand2 Operand2 Cond 00 I Opcode S Rn Rd Operand2 0xE3A02003 = 1110 00 1 1101 0 0000 0010 000000000011  Condition: Always 00 I: immediate Opcode: MOV S: Set condition Code = do not use condition codes Rn: 1st operand register (if applicable) N/A 31 31 28 28 27 26 27 26 25 25 24 21 24 21 20 20 19 16 19 16 15 12 15 12 11 11 00 31 11 11 11 00 28 27 00 00 26 25 00 24 1101 1101 21 20 00 19 0001 0001 16 15 0010 12 11 0 1 Cond Cond 110 00 00 00 I1 I 1101 Opcode Opcode SS0 0000 Rn Rn 0010 Rd Rd 00000000011 Operand2 Operand2 Cond 00 I Opcode S Rn Rd Operand2 0xE3A02003 = 1110 00 1 1101 0 0000 0010 000000000011  Condition: Always 00 I: immediate Opcode: MOV S: Set condition Code = do not use condition codes Rn: 1st operand register (if applicable) N/A Rd: Destination Register R2 31 31 28 28 27 26 27 26 25 25 24 21 24 21 20 20 19 16 19 16 15 12 15 12 11 11 00 31 11 11 11 00 28 27 00 00 26 25 00 24 1101 1101 21 20 00 19 0001 0001 16 15 0010 12 11 0 1 Cond Cond 110 00 00 00 I1 I 1101 Opcode Opcode SS0 0000 Rn Rn 0010 Rd Rd 00000000011 Operand2 Operand2 Cond 00 I Opcode S Rn Rd Operand2 0xE3A02003 = 1110 00 1 1101 0 0000 0010 000000000011  Condition: Always 00 I: immediate Opcode: MOV S: Set condition Code = do not use condition codes Rn: 1st operand register (if applicable) N/A Rd: Destination Register R2 Operand2: 3 31 31 28 28 27 26 27 26 25 25 24 21 24 21 20 20 19 16 19 16 15 12 15 12 11 11 00 31 11 11 11 00 28 27 00 00 26 25 00 24 1101 1101 21 20 00 19 0001 0001 16 15 0010 12 11 0 1 Cond Cond 110 00 00 00 I1 I 1101 Opcode Opcode SS0 0000 Rn Rn 0010 Rd Rd 00000000011 Operand2 Operand2 Cond 00 I Opcode S Rn Rd Operand2 0xE3A02003 = 1110 00 1 1101 0 0000 0010 000000000011  Condition: Always 00 I: immediate Opcode: MOV S: Set condition Code = do not use condition codes Rn: 1st operand register (if applicable) N/A Rd: Destination Register R2 Operand2: 3 MOV R2, #3 31 31 28 28 27 26 27 26 25 25 24 21 24 21 20 20 19 16 19 16 15 12 15 12 11 11 00 31 11 11 11 00 28 27 00 00 26 25 00 24 1101 1101 21 20 00 19 0001 0001 16 15 0010 12 11 0 1 Cond Cond 110 00 00 00 I1 I 1101 Opcode Opcode SS0 0000 Rn Rn 0010 Rd Rd 00000000011 Operand2 Operand2 Cond 00 I Opcode S Rn Rd Operand2 0xE3A02003 = 1110 00 1 1101 0 0000 0010 000000000011 Content  Content Assembling by hand