Experiment No. 7: JK and T Flip-Flops PDF

# Experiment No.- 7 ## AIM: Understand JK Flip-Flop and implement T-Flip Flop using NAND circuit of JK Flip Flop. ## Learning Objectives: 1. To implement JK flip flop using NAND gates and verify its functionality. 2. To implement T flip flop using NAND gates and verify its functionality. ## Compo...

# Experiment No.- 7 ## AIM: Understand JK Flip-Flop and implement T-Flip Flop using NAND circuit of JK Flip Flop. ## Learning Objectives: 1. To implement JK flip flop using NAND gates and verify its functionality. 2. To implement T flip flop using NAND gates and verify its functionality. ## Components & Instruments required: IC 7410, 7400, Power supply and LEDs. ## Theory: The logic circuits whose outputs at any instant of time depend not only on the present input but also on the past outputs are called sequential circuits. The simplest kind of sequential circuit which is capable of storing one bit of information is called latch. The operation of basic latch can be modified, by providing an additional control input that determines, when the state of the circuit is to be changed. The latch with additional control input is called the Flip-Flop. The additional control input is either the clock or enable input. Flip flop is formed using logic gates. Flip flop are fundamental building blocks in the memory of electronic devices. Each flip flop can store one bit of data. Based on their operations, flip flops are basically 4 types. They are 1. S-R flip flop 2. D flip flop 3. J-K flip flop 4. T flip flop ## J-K flip-flop: JK flip flop operates on sequential logic principle, where the output is dependent not only on the current inputs but also on the previous state. There are two inputs in JK Flip Flop Set and Reset denoted by J and K. It also has two outputs: Output and complement of Output denoted by Q and Q. The internal circuitry of a JK Flip Flop consists of a combination of logic gates, usually NAND gates as shown in **Figure 1**. JK flip flop comprises four possible combinations of inputs: * **J=0, K=0:** In this state, flip flop retains its preceding state. It neither sets nor resets itself, making it stable. * **J=0, K=1:** This input combination forces flip flop to reset, resulting in Q=0 and Q=1. It is often referred to as the "reset" state. * **J=1, K=0:** Here, flip flop resides in the set mode, causing Q=1 and Q=0. It is known as the "set" state. * **J=1, K=1:** This combination toggles flip flop. If the previous state is Q-0, it switches to Q=1 and vice versa. This makes it valuable for frequency division and data storage applications. **Figure 1:** J-K Flip flop using NAND gate, Truth Table (here Q₁=Q) ## T flip-flop: T flip flop or to be precise is known as Toggle Flip Flop because it can able to toggle its output depending upon on the input. T, here stands for Toggle. Toggle basically indicates that the bit will be flipped i.e., either from 1 to 0 or from 0 to 1. The toggle or T-type flip-flop gets its name from the fact that its two outputs Q and Q invert from their previous state as it toggles back and forth every time it is triggered (T=1). That is, the Q and Q outputs change to a "l" if it was "0", and "0" if it was previously a "1" but only when the "T" input changes HIGH, otherwise they do not change. Same is shown in **Figure 2**. **Figure 2:** NAND implementation of T-FF and Truth Table *** ## Procedure: 1. Make the connections using IC 7400 and 7410 as per **Figure 1** 2. Power on the IC-7410 and 7400 by connecting Vcc at pin 14 and GND at PIN 7. 3. Connect the "Clock 1Hz" button or pulse button as a CLK. 4. Apply the inputs as per characteristic table of JK FF and note the outputs in **Figure 1**. Update the observation table of JK FF. 5. Verify the practical and theoretical values of JK-FF as per entries in observation table of JK FF. 6. Similarly repeat step 4 and 5 for T FF of **Figure 2**. 7. Identify different sources of error in the practical. ## IC Diagram of JK-FF using NAND Gates: ## IC Diagram of T-FF using NAND Gates ## Precautions: 1. Do not press the IC on breadboard until pins are aligned with pours. 2. Make connection properly. 3. There should not any short circuit in the circuit. Avoid the heating of IC. Provide proper clock pulse. ## Learning Outcomes: 1. Explain the working of flip flops. 2. Test the IC of logic gates 7400, 7410. 3. Verify the effect of previous output and current input on the next state output. ## Viva Questions: 1. What is the function of clock pulse? 2. What do you mean by race around condition? 3. How the race around condition can be removed? 4. How to convert JK to T-FF. ## Learning Outcomes (expected): 1. Implement JK and T-FF on the breadboard 2. Verify JK and T FF. 3. Identify different sources of error in the practical. ## Learning Outcomes (what I have learnt?): 1. How to test functioning of 7400 and 7410? * **Ans:** 2. What steps are required to convert JK-FF to T-FF? * **Ans:** ## Worksheet of the student ## Observation Table for J-K Flip Flop | J | K | Qn| Q(n+1) (Calculated using Characteristic equation) | Q(n+1) (Observed using LED display of Digital trainer kit) | |---|---|---|---|---| | 0 | 0 | 0 | 0.0+0.0-0.1-1.0-0+0=0 | | | 0 | 0 | 1 | 0.1+0.1-0.0-1.1-0+1=1 | | | 0 | 1 | 0 | 0.0+0.0-0.1+1.0-0-0-0 | | | 0 | 1 | 1 | 0.1+1.1-0.0-0.1-0-0-0 | | | 1 | 0 | 0 | 1.0+0.0-1.1+1.0=1+0=1 | | | 1 | 0 | 1 | 1.1+0.1-1.0+1.1=0+1=1 | | | 1 | 1 | 0 | 1.0+1.0-1.1+0.0=1+0=1 | | | 1 | 1 | 1 | 1.1+1.1-1.0-0.1-0+0=0 | | ## Observation Table for T Flip Flop | T | Qn | Q(n+1) (Calculated using Characteristic equation) | Q(n+1) (Observed using LED display of Digital trainer kit) | |---|---|---|---|---| | 0 | 0 | 0.0+0.0-0.1+1.0-0+0=0 | | | 0 | 1 | 0.1+0.1-0.0+1.1=0+1=1 | | | 1 | 0 | 1.0+1.0-1.1+0.0=1+0=1 | | | 1 | 1 | 1.1+1.1-1.0-0.1-0-0-0 | |