DE Lab File PDF

## Experiments ### Experiment No. 1 **Aim:** Study of Logic Bread Board with Verification of truth table for AND, OR, NOT, NAND, EX-OR, NOR gate. **Requirement:** Logic Trainer Board. **Main Parts of Logic Bread Board Trainer:** 1. Power supply 2. Input Logic Level and Indicator 3. Output log...

## Experiments ### Experiment No. 1 **Aim:** Study of Logic Bread Board with Verification of truth table for AND, OR, NOT, NAND, EX-OR, NOR gate. **Requirement:** Logic Trainer Board. **Main Parts of Logic Bread Board Trainer:** 1. Power supply 2. Input Logic Level and Indicator 3. Output logic Indicator 4. Clock Generator 5. Pulser 6. Decoder Display 7. Logic Probe 8. Bread board **Block Diagram Representation of Logic Board Trainer:** - A **Clock Generator** at the top left is connected to a **Bread Board** in the middle. - A **Pulser** at the bottom left is connected to the **Bread Board** in the middle. - The **Bread Board** in the middle is connected to a **Decoder Prove** on the left and an **Output Logic Indicator** on the right. - The **Output Logic Indicator** on the right is connected to a **Logic Probe** at the top top right. - The **Bread Board** is also connected to a **Power Supply Unit** at the bottom right. - The **Power Supply Unit** is connected to a **CMOS** at the top right and a **TTLO** on the right. **Fig. 1. Block diagram representation of Logic Board trainer.** ### Experiment No. 2 **Aim:** Verification of NAND and NOR gates as a Logic Universal Gate **Component and Materials Required:** - IC 7400 - IC 7402 - Logic Trainer - Bread Board - Connecting wires **Theory:** Nand and Nor gates are called universal gates because all logic functions are performed by these gates. This is why these two NAND and NOR gates are called universal gates. **1. NAND Gate as a Universal Gate** **(a) NAND Gate as an Inverter Gate:** - A goes through the input of a NAND gate and comes out as **Y**. - **A**, is considered the input value - **Y**, is considered the output value **(b) NAND Gate as an AND Gate:** - If **A** and **B** are the two inputs of **AND gate**, then the output (**Y**) of the AND gate is **Y = AB**. - The logic function is realized by NAND gate as: - **A** goes through one NAND gate and the output is **AB**. - **B** goes through another NAND gate and the output is **AB**. - **AB** and **AB** go through a third NAND gate and the output is **Y**. - **Y = AB**. **(c) NAND Gate as an OR Gate:** - If **A** and **B** are the two input values of **OR gate**, then the output (**Y**) of the **OR gate** is **Y = A + B**. - The logic function is realized as: - **A** goes through one NAND gate and the output is **A**. - **B** goes through another NAND gate and the output is **B**. - **A** and **B** go through a third NAND gate and the output is **AB**. - **AB** goes through a fourth NAND gate and the output is **Y**. - **Y = AB = A + B = A + B**. **Wiring Diagram:** **(a) For Inverter Gate:** - **A** is the input, **Y** is the output. - **A** comes from the Logic input side of the trainer board. - **Y** comes from the output logic indicator of the trainer board. **(b) For AND Gate:** - **A** is the input on the left, **Y** is the output on the right. - **A** comes from the Logic input side of the trainer board. - **Y** comes from the output logic indicator of the trainer board. - The Logic input side of the trainer board is connected to **B** and **B** comes from the Logic input side of the trainer board **Observation Table, Truth Table for Inverter Gate:** **(a) Observation Table, Truth Table for Inverter Gate:** - Same input and output for A and Y. **Conclusion:** Observation table and truth table of NOT gate are the same. **(b) Wiring Diagram for AND Gate:** - **B** is the input on the left, **Y** is the output on the right. - **B** comes from the Logic input side of the trainer board. - **Y** comes from the output logic indicator of the trainer board. - The Logic input side of the trainer board is connected to **A** and **A** comes from the Logic input side of the trainer board **Observation Table, Truth Table for AND Gate:** - **A** and **B** are the input values. - **Y** is the output value. **Conclusion:** Observation table and truth table for AND gate are the same. **(c) Wiring Diagram of OR gate using NAND gate:** - **A** is the input on the left, **Y** is the output on the right. - **A** comes from the Logic input side of the trainer board. - **Y** comes from the output logic indicator of the trainer board. - The Logic input side of the trainer board is connected to **B** and **B** comes from the Logic input side of the trainer board. **Observation Table, Truth Table for OR Gate:** - **A** and **B** are the input values. - **Y** is the output value. **Conclusion:** Observation table and truth table for OR gate are the same. **NOTE:** As in digital electronics there are three fundamental gates (NOT, OR, and AND), so they are only realized. **2. NOR Gate as NOT Gate** **(a) NOR Gate as NOT gate:** - **A**, is connected to a NOR gate and the output is **A + A = A**. **(b) NOR Gate as an AND Gate:** - **A** is connected to a NOR gate and the output is **A**. - **B** is connected to a NOR gate and the output is **B**. - The output of each gate is connected to another NOR gate and the final output is **Y = A.B = A.B = AB**. **(c) NOR Gate as OR gate:** - **A** is connected to a NOR gate and the output is **A + B**. - **B** is connected to a NOR gate and the output is **A + B**. - The output of each gate goes through a final NOR gate and the output is **Y = (A + B) + (A + B) = A + B = A + B**. **Wiring Diagram of NOT gate using NOR gate:** - **A** comes fromthe Logic input side of the trainer board. - **Y** comes from the output indicator side of the trainer board. **Observation Table of Not gate using NOR gate:** - **A** is the input value. - **Y** is the output value. **Conclusion** Observation table of this gate is similar to the truth table of NOT gate. Hence realization of NOT gate with NOR gate is verified. **Wiring Diagram of AND gate using NOR gate** - **A** comes from the Logic input side of the trainer board. - **Y** comes from the output indicator side of the trainer board. - The Logic input side of the trainer board is connected to **B** and **B** comes from the Logic input side of the trainer board. - **Conclusion:** Observation table of this gate is similar to the truth table of NOT gate. Hence realization of NOT gate with NOR gate is verified. **Realization of OR gate using NOR gate:** - **A** comes from the Logic input side of the trainer board. - **Y** comes from the output indicator side of the trainer board. - The Logic input side of the trainer board is connected to **B** and **B** comes from the Logic input side of the trainer board. **Observation Table** - ** A and B ** are the input. - **Y** is the output. **Conclusion** The observation table of the logic circuit is similar to the truth table of OR gate. Hence realization of OR gate with NOR gate is verified. ### Experiment No. 3 **Aim:** Construction of Half Adder and Full Adder Circuit Using Ex-OR and NAND gate and verification of their operation **Component and Material Required:** - Logic trainer board - IC-7486 - IC 7400 - Connecting wire **Theory:** The binary addation performed by a logic circuit is called a Half adder. The symbol of binary adder is as: - Two input values are **A** and **B**. - Two output values are **Sum (Σ)** and **Carry out (Co)**. **Truth Table:** - **A** and **B** are the input. - **Σ** and **Co** are the output. **The Logical expression for sum and carry output is:** - **Sum = Σ = A ⊕ B = AB + AB**, - **Carry output Co = AB**. **Logical Diagram of Half Adder:** - Two input values **A** and **B** are connected to both sides of an **Ex-OR Gate**. - The output from the **Ex-OR Gate** is **Sum = A ⊕ B**. - **A** and **B** are connected to both sides of an **AND Gate**. - The output from the **AND Gate** is **CO = AB**. - ### Experiment No. 4 (1) **Aim:** Verify the operation of Multiplexer, Demultiplexer using an IC. **Materials Required:** - Digital Logic Trainer Board - IC 74151 - Connecting wires. **Theory:** Multiplexer is a logic circuit that accepts several date imputs and allows only one of them at the output. Which data is transferred at the output depends upon the select line. For four bit data input there is two select line, eight bit data there is three select line and for sixteen bit data there is four select line. The block diagrame representation of multiplexer is shown as: - **n data inputs** are at the top. - **n- select lines** at the bottom. - **Output** is on the right. **The Relation between m and n is:** - **2 ^ m = n**. **Logic Circuit Diagram of 8 bit input data selector (74151):** - An **ENABLE** input on the left (input 7). **Truth Table:** | S2 | S1 | So | Input Selected | | --- | --- | --- | --- | | 0 | 0 | 0 | D₀ | | 0 | 0 | 1 | D₁ | | 0 | 1 | 0 | D₂ | | 0 | 1 | 1 | D₃ | | 1 | 0 | 0 | D₄ | | 1 | 0 | 1 | D₅ | | 1 | 1 | 0 | D₆ | | 1 | 1 | 1 | D₇ | **Wiring Diagram of 74151 I.C** - The board is **enabled** from the Logic input side of the trainer board. - **D₀ - D₇** come from the Logic input side of the trainer board. - **S₂**, **S₁**, and **S₀** come from the Logic input side of the trainer board. - **Y** comes from the output indicator of the trainer board. **Observation Table** - **S₂**, **S₁**, and **S₀** are the input values. - **Y** is the output value. **Conclusion:** Observation table for 8 bit input multiplexer is the same as the truth table of 8 bit MUX. Hence the operation of multiplexer is verified. ### Experiment No. 5 (1) **Aim:** Verify the operation of BCD to Decimal decoder using an IC **Material Required:** - Logic trainer board - IC 7442 (BCD to Decimal decoder) - Connecting wires. **Theory:** - The function of the **Decoder** is to detect the presence of a specific combination of bits on its input and indicate the presence by a specified output level. A decoder has **n** input lines to handle **n** bits from one to 2ⁿ output lines, and it converts BCD numbers to decimal equivalents. - **BCD code**, represents only ten decimal digit 9 through a, and has a decoding function. | Decimal No. | BCD Code | Logic Function| | --- | --- | --- | | 0 | 0 0 0 0 | DCBA | | 1 | 0 0 0 1 | DCBA | | 2 | 0 0 1 0 | DCBA | | 3 | 0 0 1 1 | DCBA | | 4 | 0 1 0 0 | DCBA | | 5 | 0 1 0 1 | DCBA | | 6 | 0 1 1 0 | DCBA | | 7 | 0 1 1 1 | DCBA | | 8 | 1 0 0 0 | DCBA | | 9 | 1 0 0 1 | DCBA | **Pin Discription of IC 7442 is shown in fig.** - **Vcc** is connected to pin 16 - **A - D** correspond to pins 15-12. - **Y₀ - Y₉** correspond to pins 1-8. - **GND** is ground and is connected to pin 9. **Wiring Diagram of BCD to decimal decoder** - **A (LSB) - D (MSB)** come from the Logic input side of the trainer board, connected to pins 15-12. - **Y₀ - Y₉** are outputs, connected to pins 1-8, and go to the output indicator of the trainer board. **Observation Table:** - **D**, **C**, **B**, and **A** are the BDC Code values. - **Y­­₀** - **Y­­_­9**are output values. **Conclusion:** From observation table, the function of IC 7442 as BCD to Decimal decoder is verified. ### Experiment No. 6 (1) **Aim:** Verify the operation of SR, D, JK, and inverter slave JK Flip flop. **Requirement:** NAND Gate IC 7400, Flip-flop Logic Trainer Board, connecting wire. **Theory:** Set /Reset Flip-flop has two Inputs **S** and **R**, with a clock signal and gives two outputs that are complements of each other. **Logic Symbol:** - **A** is the input. - **B** is the input. - **Q** is the output. - **Q** is the output, and is the opposite of **Q**. **RS Flip-flop Constructed with the Help of NAND Gate:** - The inputs are **S** and **R**. - The outputs are **Q** and **Q**. - The clock is the pulse being introduced to flip the state. **Truth Table:** | **R** | **S** | **Clock** | **Q** | **Q** | **Remark** | |---|---|---|---|---|---| | 0 | 0 | ↑ | Q | Q | No change | | 0 | 1 | ↑ | 1 | 0 | Set | | 1 | 0 | ↑ | 0 | 1 | Reset | | 1 | 1 | ↑ | ? | ? | Invalid | **Wiring Diagram of RS Flip-Flop:** - **Ro** comes from the Logic input side of the trainer board, connected to pin 1. - **Clock input** comes from the Logic input side of the trainer board. - **B** comes from the Logic input side of the trainer board, connected to pin 6.. - **Q** and **Q** are outputs, and go to the output logic indicator on the trainer board. **Observation Table:** - **R** and **S** are the input. - **Q** and **Q** are the output. **Conclusion:** Operation of RS flip-flop is verified. ### Experiment No. 7 **Title:** To study the various type of shift registers **Requirements:** - IC 7495 - Bread board - Connecting wires **Theory:** A shift register moves the stored bits left or right. This bit shifting is essential for arithmetic and logic operations used in microcomputers. A shift register can work in four different configurations: - Serial in Serial Out (SISO) - Serial in Parallel Out (SIPO) - Parallel in Serial Out (PISO) - Parallel in Parallel Out (PIPO) **Shift Left Register:** - A shift register is **Q₃ Q_­2 Q₁ Q_­0**, with a 4 bit digital word. - **D_in** is the input. - The **Clock** is the pulse triggering the shift. **Truth Table:** | CLK Pulse | Q₃ | Q_­2 | Q₁ | Q_­0 | |---|---|---|---|---| | None | 0 | 0 | 0 | 0 | | CLK 1 | 0 | 0 | 0 | 1 | | CLK 2 | 0 | 0 | 1 | 1 | | CLK 3 | 0 | 1 | 1 | 1 | | CLK 4 | 1 | 1 | 1 | 1 | **Shift Right Register:** - A shift register is **Q_­3 Q₂ Q₁ Q₀**, with a 4 bit digital word. - **D_in** is the input. - The **Clock** is the pulse triggering the shift. **Truth Table:** | CLK | Q₃ | Q_­2 | Q₁ | Q_­0 | |---|---|---|---|---| | None | 0 | 0 | 0 | 0 | | CLK 1 | 0 | 0 | 0 | 1 | | CLK 2 | 0 | 0 | 1 | 1 | | CLK 3 | 0 | 1 | 1 | 1| | CLK 4 | 1 | 1 | 1 | 1 | **Parallel Loading:** - All bits in the shift register are loaded in a single clock pulse. - Certain control signals are used. **Serial Loading:** - One bit is stored at a time. - The number of clock pulses required is the same as the number of bits in the register. **Procedure** **(a) Serial Input Right Shift Register** - **M = 0** - Apply serial data at **serial Input terminal** starting from LSB. - Apply clock pulses at pin 9, after each data, and record the outputs. - Verify the operation as a right shift register. **(b) Parallel Input Shift Register** - Connect **M to logic '1'** and verify the operation as a right shift register by applying clock pulses at the CK-1 terminal, as a left shift register by applying clock pulses at the CK-2 terminal. - Connect **M to Logic 1** and apply the serial data at the **D input** starting from MSB. - Apply clock pulses at CK-2 terminal and observe the outputs **Q_A**, **Q_B**, **Q_C**, **Q­_D**. Record output states and verify the operation as a left shift register. **IC 7495 as Shift Register** - **A** is the serial input. - **B, C, and D** are the parallel inputs. - **M** is mode control. - **Clock 1** and **Clock 2** are the clock inputs. ### Experiment No 8 (1) **Title**: Up-Down Counter Using IC 74193 **Objective:** To study the following functions of IC 74193: - Up-counter - Down-counter **Materials Required:** - Logic Trainer - IC 74193 - Volt-ohm-milliammeter - Resistances of 1 kΩ, 470 Ω **Diagram:** - The circuit is composed of a **Logic trainer**, **74193 counter IC**, **pulser switches**, **resistors**, and a **voltmeter.** **Procedure** **(A) Up-counting Function** - Assemble the circuit as shown above. - Connect the logic switches, output, and resistors as indicated. - Connect a voltmeter to pin 12. - Switch on the power supply. The counter may come up in one of the possible states. - Reset the counter to 0000 with pulser switch B. - Record the voltage at pin 12, which should be about 4 V. - Apply input pulses to the counter with pulser switch A. - Notice that when the counter shows a count of 1 1 1 1, that is the maximum count, the voltage at pin 12 will drop to 0.2 V. - At the next input pulse, counter output will drop to 0000, and the voltage at pin 12 will go high, indicating a transition of the carry-out signal from 0 → 1, which can step up the next counter if there is one in position. **Table** | Count Sequence | Counter Output | Voltage at pin 12 | |---|---|---| | Initial state | 0 0 0 0 | 4 V | | After 1st pulse | 0 0 0 1 | 4 V | | After 14th pulse | 1 1 1 0 | 4 V | | After 15th pulse | 1 1 1 1 | 0.2 V | | After 16th pulse | 0 0 0 0 | 4 V | **(B) Down-counting Function** - Assemble the circuit shown in Fig. 12.5, noticing that connections to pins 4 and 5 are not the same as for the up-counter (Fig. 12.5). - Connect a voltmeter between pin 13 and ground. - Switch on the power supply and reset the counter to 0000 with pulser switch B. - Apply a pulse input with pulser switch A at the DOWN input, pin 4, and notice that the counter output is now 1 1 1 1. Also note the voltage at pin 13, which should be high. - After 15 pulses, the counter will register 0 0 0 0, and at the same time the voltage at pin 13 will drop to about 0.2 V. At the next pulse input, the counter output will jump to 1 1 1 1 and, if another similar counter is connected in cascade, it will be decremented by one count at the same time during transition from 0 → 1 at pin 13. **Diagram** - The circuit is composed of a **Logic trainer**, **74193 counter IC**, **pulser switches**, **resistors**, and a **voltmeter.** **Table** | Count Sequence | Counter Output | Voltage at pin 12 | |---|---|---| | Initial state | 1 1 1 1 | 4 V | | After 1st pulse | 1 1 1 0 | 4 V | | After 2nd pulse | 1 1 0 1 | 4 V | | After 15th pulse | 0 0 0 0 | 0.2 V | | After 16th pulse | 1 1 1 1 | 4 V |