Chapter 3

Decoding on a Bus System

• The 8080 bus has 16 bits for addressing, with the first 6 bits used for I/O devices.

• The memory address bus tells a memory device which location is being accessed, with the number of memory address lines required depending on the size of the memory device.

• The quantity of data stored at each memory location depends on the particular memory device, with units of memory connected in parallel to meet the processor data width.

• To access data from a memory device, the address is placed on the address bus, followed by a chip select signal and a read or write signal.

• Partial and full address decoding are implemented depending on the number of address pins required by the devices connected to the processor address bus.

• Memory foldover occurs when a memory address responds to several different processor addresses, which can cause inefficiencies and programming errors.

• Address decoders using K-Maps or standard Boolean logic can be used to connect several memory ICs to an address bus, but demultiplexers or decoders are easier to use in many cases.

• The 74138 1-of-8 demultiplexer is commonly used, with the output pin going low corresponding to the binary input at pins A, B, and C.

• The 74LS85 4 bit comparator is also used for decoding, with the output going low when the digital value at the A inputs equals the digital value at the B inputs.

• To design a full decoding system using a 74138, the number of address pins used by the memory chip itself must be identified, and the memory map of the design must be drawn.

• The truth table is then created, and a pattern is identified to fit to the truth table of the 74138.

• A final design can then be produced, with the 74LS85 enabling A15 to A14 when it has the value 2H, and the 74138 enabling up to 8 devices one at a time depending on the values of A13 to A11.Decoding Memory and I/O Devices on the 8080 and SMI Buses

• The 8080 microprocessor can access buffers and latches through the SMI bus.

• Memory devices use only some of the available address lines and a decoder selects one of several memory devices based on higher address lines.

• Buffers and latches have only a single address location and require decoding for each device to avoid activating other I/O by accident.

• The SMI implementation only uses 6 bits of the 16 bit I/O address space available on Intel microprocessors.

• An external gate is needed to control access for buffers and latches, so that processor reads are directed to buffers and writes are directed to latches.

• The 74138 and 74LS85 TTL chips allow for easy and flexible decoding of individual I/O addresses.

• The 74LS85 activates a block of 8 devices through the 74138, with the starting address of the block having A0-A2 pins at logic 0.

• Memory devices contain many storage locations within itself and have control pins that determine whether data is written or read to.

• Buffers and latches, being individual devices, need full decoding to be done externally as it does not have the circuitry internally.

• External gates may be needed to correctly decode the signal for buffers and latches.

• Some examples of current devices that use the 8080 bus include STM32F10xxx, FlexIO, and Raspberry Pi Compute Module 3+.

• Understanding how to decode memory and I/O devices is essential for designing input and output ports on the 8080 and SMI buses.

Decoding on a Bus System

• The 8080 bus has 16 bits for addressing, with the first 6 bits used for I/O devices.

• The memory address bus tells a memory device which location is being accessed, with the number of memory address lines required depending on the size of the memory device.

• The quantity of data stored at each memory location depends on the particular memory device, with units of memory connected in parallel to meet the processor data width.

• To access data from a memory device, the address is placed on the address bus, followed by a chip select signal and a read or write signal.

• Partial and full address decoding are implemented depending on the number of address pins required by the devices connected to the processor address bus.

• Memory foldover occurs when a memory address responds to several different processor addresses, which can cause inefficiencies and programming errors.

• Address decoders using K-Maps or standard Boolean logic can be used to connect several memory ICs to an address bus, but demultiplexers or decoders are easier to use in many cases.

• The 74138 1-of-8 demultiplexer is commonly used, with the output pin going low corresponding to the binary input at pins A, B, and C.

• The 74LS85 4 bit comparator is also used for decoding, with the output going low when the digital value at the A inputs equals the digital value at the B inputs.

• To design a full decoding system using a 74138, the number of address pins used by the memory chip itself must be identified, and the memory map of the design must be drawn.

• The truth table is then created, and a pattern is identified to fit to the truth table of the 74138.

• A final design can then be produced, with the 74LS85 enabling A15 to A14 when it has the value 2H, and the 74138 enabling up to 8 devices one at a time depending on the values of A13 to A11.Decoding Memory and I/O Devices on the 8080 and SMI Buses

• The 8080 microprocessor can access buffers and latches through the SMI bus.

• Memory devices use only some of the available address lines and a decoder selects one of several memory devices based on higher address lines.

• Buffers and latches have only a single address location and require decoding for each device to avoid activating other I/O by accident.

• The SMI implementation only uses 6 bits of the 16 bit I/O address space available on Intel microprocessors.

• An external gate is needed to control access for buffers and latches, so that processor reads are directed to buffers and writes are directed to latches.

• The 74138 and 74LS85 TTL chips allow for easy and flexible decoding of individual I/O addresses.

• The 74LS85 activates a block of 8 devices through the 74138, with the starting address of the block having A0-A2 pins at logic 0.

• Memory devices contain many storage locations within itself and have control pins that determine whether data is written or read to.

• Buffers and latches, being individual devices, need full decoding to be done externally as it does not have the circuitry internally.

• External gates may be needed to correctly decode the signal for buffers and latches.

• Some examples of current devices that use the 8080 bus include STM32F10xxx, FlexIO, and Raspberry Pi Compute Module 3+.

• Understanding how to decode memory and I/O devices is essential for designing input and output ports on the 8080 and SMI buses.

Decoding on a Bus System

• The 8080 bus has 16 bits for addressing, with the first 6 bits used for I/O devices.

• The memory address bus tells a memory device which location is being accessed, with the number of memory address lines required depending on the size of the memory device.

• The quantity of data stored at each memory location depends on the particular memory device, with units of memory connected in parallel to meet the processor data width.

• To access data from a memory device, the address is placed on the address bus, followed by a chip select signal and a read or write signal.

• Partial and full address decoding are implemented depending on the number of address pins required by the devices connected to the processor address bus.

• Memory foldover occurs when a memory address responds to several different processor addresses, which can cause inefficiencies and programming errors.

• Address decoders using K-Maps or standard Boolean logic can be used to connect several memory ICs to an address bus, but demultiplexers or decoders are easier to use in many cases.

• The 74138 1-of-8 demultiplexer is commonly used, with the output pin going low corresponding to the binary input at pins A, B, and C.

• The 74LS85 4 bit comparator is also used for decoding, with the output going low when the digital value at the A inputs equals the digital value at the B inputs.

• To design a full decoding system using a 74138, the number of address pins used by the memory chip itself must be identified, and the memory map of the design must be drawn.

• The truth table is then created, and a pattern is identified to fit to the truth table of the 74138.

• A final design can then be produced, with the 74LS85 enabling A15 to A14 when it has the value 2H, and the 74138 enabling up to 8 devices one at a time depending on the values of A13 to A11.Decoding Memory and I/O Devices on the 8080 and SMI Buses

• The 8080 microprocessor can access buffers and latches through the SMI bus.

• Memory devices use only some of the available address lines and a decoder selects one of several memory devices based on higher address lines.

• Buffers and latches have only a single address location and require decoding for each device to avoid activating other I/O by accident.

• The SMI implementation only uses 6 bits of the 16 bit I/O address space available on Intel microprocessors.

• An external gate is needed to control access for buffers and latches, so that processor reads are directed to buffers and writes are directed to latches.

• The 74138 and 74LS85 TTL chips allow for easy and flexible decoding of individual I/O addresses.

• The 74LS85 activates a block of 8 devices through the 74138, with the starting address of the block having A0-A2 pins at logic 0.

• Memory devices contain many storage locations within itself and have control pins that determine whether data is written or read to.

• Buffers and latches, being individual devices, need full decoding to be done externally as it does not have the circuitry internally.

• External gates may be needed to correctly decode the signal for buffers and latches.

• Some examples of current devices that use the 8080 bus include STM32F10xxx, FlexIO, and Raspberry Pi Compute Module 3+.

• Understanding how to decode memory and I/O devices is essential for designing input and output ports on the 8080 and SMI buses.