Chapter 3.pdf

3 Decoding on a bus system Although the 8080 bus has 16 bits for addressing, we first consider the use of these 16 bits for memory chips, then the first 6 bits for I/O devices. To see what is needed, we will examine the interfacing of some memory devices. 3.1 Accessing a memory device As we have co...

3 Decoding on a bus system Although the 8080 bus has 16 bits for addressing, we first consider the use of these 16 bits for memory chips, then the first 6 bits for I/O devices. To see what is needed, we will examine the interfacing of some memory devices. 3.1 Accessing a memory device As we have considered the address, data and control busses from the processor point of view, now we consider them from the memory point of view. 3.1.1 Memory address, data, control bus In contrast to the processor address bus, the memory address bus will tell a memory device which particular location is being accessed. The number of memory address lines required depends on the size of the memory device. (e.g. a device with 2K (i.e. 2048) locations, requires 11 address lines, because 211 = 2048). In the same way, the quantity of data stored at each memory location depends on the particular memory device. It may be a single bit, or 4, 8 or 16 bits per location. Units of memory may be connected in parallel to meet the processor data width. For example, four 8 bit memory devices may be connected in parallel to a 32 bit processor. 3.1.2 Steps to access memory A0 A11 D0 D7 __ CS __ RD __ WR Memory Device Fig 3.1 Steps to access memory The block diagram of a memory device is as shown. To access data, the following steps are executed. page 3-1 Chapter 3 Decoding on a bus system 1) Embedded Computer Systems The address is placed on the address bus. The lower bits will be used by the memory device for internal decoding, the higher bits go to a decoder chip which will generate a ���). This will then select one of the several memory devices. chip select signal (CS 2) READ ����) which is connected to If doing a read operation, the processor will generate a read signal (RD ���� the output enable (OE) of the memory chip. The memory device will place the data from the memory location after a short delay. The processor then reads in the data. 3) WRITE If doing a write operation, the processor will places the data to be written on the data bus, then �����) signal, which is connected to the write enable (WE �����) of the memory chip. generates a write (WR The memory device will then latch the data in. 3.1.3 Partial and Full Address Decoding In most practical situations, the devices connected to a processor address bus require fewer address bits than there are bits provided on the address bus. The 8080 has 16 pins while a 6116 RAM has only 11 pins for addressing. Since there are 5 pins unused by the RAM chip, then this is a case of partial address decoding. If we have a memory system where all the address pins are used in memory access, we then have full address decoding. As an illustration of how partial and full address decoding are implemented, we shall look at how a memory chip can be connected to a 16-bit address bus. 3.1.3.1 A memory device 8 7 6 5 4 3 2 1 23 22 21 U1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 D0 D1 D2 D3 D4 D5 D6 D7 18 CS 20 OE 21 WE 9 10 11 13 14 15 16 17 Pin Name Function A0 to A10 Address input D0 to D7 Data input/output CS Chip select WE Write enable OE Output enable Vcc Power supply Vss Ground 6116 Fig 3.2 6116 schematic page 3-2 Chapter 3 Decoding on a bus system Embedded Computer Systems Pins A0 to A10 are the 11-bit address inputs to the 2048 locations in the RAM while D0 to D8 are the 8 data bits in each location. CS1 is the chip select inputs (active high or low depending on whether there is a bar on top) that enable the chip. 8080 A d d r e s s b u s A15 Unassigned A10 6116 A0 Fig 3.3 Foldover When the 6116 is connected to the 8080 address bus as shown only the states of the address lines A0 to A10 will determine which location inside the RAM is accessed. The other address lines A11 to A15 are ignored by the chip. Hence the location 000 0000 0000B can be accessed by the addresses XXXX X000 0000 0000B. Therefore addresses from the processor bus 0000H, 0800H, 1000H and so on will all access the same memory location 0000H. This is an inefficient way of using the address bus since even though 216 = 65536 locations can be selected individually, only 2K are used, each responding to 65536/2048 = 32 different processor addresses. Memory Foldover When a memory address (or group of physical addresses) responds to several different processor addresses, the effect is known as memory foldover. In the example above, there is a 32 times foldover. In small systems, this is tolerable. But we see two problems here. First is that if more than one device needs to be attached to the bus, how do we fit it in? Secondly is that a programmer may access data from the wrong memory location. When connecting several memory ICs to an address bus, we can use logic gates as address decoders using K-Maps or standard Boolean logic. However, it is much easier to use demultiplexers or decoders, because of the way memory is laid out, which in many cases is in sequential blocks of addresses, as we will see shortly. page 3-3 Chapter 3 Decoding on a bus system Embedded Computer Systems One of the most commonly used demultiplexers is the 74138 1-of-8 demultiplexer. Looking at the output pins, note that the pin that goes low will correspond to the binary input at pins A, B and C. For example, an input of 111 will cause pin Y7 to go low. PIN No 1,2,3 4,5 6 7, 9 to 15 SYMBOL NAME AND FUNCTION A,B,C Address Inputs _G2A,_G2B Enable Inputs G1 Enable Inputs Y0 to Y7 Outputs 8 GND Ground (0V) 16 Vcc Positive Supply Voltage Fig 3.4 74LS138 schematic Truth table INPUTS ENABLE OUTPUTS SELECT G2B G2A G1 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X L X X X H H H H H H H H X H X X X X H H H H H H H H H X X X X X H H H H H H H H L L H L L L L H H H H H H H L L H L L H H L H H H H H H L L H L H L H H L H H H H H L L H L H H H H H L H H H H L L H H L L H H H H L H H H L L H H L H H H H H H L H H L L H H H L H H H H H H L H L L H H H H H H H H H H H L We see that the 74138 can select one of eight possible devices based on its ABC inputs. If we add this to the thirteen inputs of the 6116, we see that we now have fourteen (11+3) inputs, which still causes foldover. To take care of this, we can still choose to use logic gates, but we introduce another device, the 74LS85 4 bit comparator which makes decoding more versatile. page 3-4 Chapter 3 Decoding on a bus system Embedded Computer Systems SYMBOL NAME AND FUNCTION iA=B Input A=B must be 1 A B A word input B word inputs 6 oA=B equal to output 8 GND Ground (0V) 16 Vcc Positive Supply Voltage PIN No 3 10, 12,13,15 9,11,14,1 Fig 3.5 74LS85 schematic We will use only the A=B output. From the truth table, when the digital value at the A inputs equal the digital value at the B inputs, and IA=B is high, then the output OA=B pin will go low. What makes this device versatile is that we do not need inverted versions of address signals, which is true if we use the 74138. We can set the desired bit pattern at either the A or B inputs. Another important point is that there are other devices connected to the system that use up certain parts of the memory map. Thus we need flexibility in locating the starting address of our memory block. page 3-5 Chapter 3 Decoding on a bus system Embedded Computer Systems EXAMPLE: Design a 16K memory space starting from 8000H, using 6116 memory chips. In designing a full decoding system using a 74138, we should note the number of address lines are used by the memory chip itself. This is because these lines cannot be used for decoding. Thus only the remaining lines on the host processor address bus is available. To summarize, we may use the following steps: 1) 2) 3) 4) 5) 6) 7) Identify how many address pins the memory chip uses. Calculate the number of chips that are required in the design. Draw the memory map of the design. Do this by laying out the chips contiguously, that is, the starting address of a chip follows immediately after the last address of the previous chip. Write down the range of addresses of each chip in hexadecimal. Draw a truth table. This is the binary representation of the range of addresses. Looking at the bits, observe any pattern of numbers, for example, running binary numbers in the bits. Fit this pattern to the truth table of the 74138. First, see which address pins are to be assigned to inputs A, B and C. Then see how to assign the remaining address pins to the Enable inputs of the 74138. If there are unassigned processor address pins, assign them to the 74688. 8) Finally, produce the schematic. Applying to the above example: 1) 2) 3) The memory device to be used is a 6116, which is a 2048 by 8 bit device. This device uses address pins A0 to A10. (211 = 2048). Each chip will take up 204810 or 7FFH addresses. Since we require 16K bytes in the design, we need 8 chips. (16K/2K). This 16K will occupy the range from 8000H to BFFFH. So the first memory chip will start from 8000H and occupy the address range 80000 - 87FFH. We continue until we get the following memory map: RAM 1 RAM 2 RAM 3 RAM 4 RAM 5 RAM 6 RAM 7 RAM 8 - 8000H to 87FFH 8800H to 8FFFH 9000H to 97FFH 9800H to 9FFFH A000H to A7FFH A800H to AFFFH B000H to B7FFH B800H to BFFFH To draw the truth table, let us look at the first chip. It occupies the address range 8000-87FFH. Using binary, and noting that the MSB is address line A15: page 3-6 Chapter 3 Decoding on a bus system Embedded Computer Systems MSB The range in binary is: 1000 0000 0000 0000 (8000H) 1000 0111 1111 1111 (87FFH) We are not interested in the address lines used by the chip at this point. Note that the 0's and 1's change only at lines A0 to A10. In order to simplify the design process, we will introduce a notation. Instead of writing two lines with all the 0's and 1's, we will represent the above range by: A15 A10 A0 1 0 0 0 0 X--------X 8000 - 87FFH "X" means that the value for the address line can be 0 or 1. The dashed line "X---X" means that address lines from A0 to A10 can be 0 or 1. So they are not available for general use. This highlights the fact that only address lines A15 to A11 are available for decoding. Proceeding in similar fashion for the other chips, we have the following truth table. A15 A14 A13 A12 A11 A10 -- - - - - - - - - - A0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x------------------------x x------------------------x x------------------------x x------------------------x x------------------------x x------------------------x x------------------------x x------------------------x 8000-87FFH 8800-8FFFH 9000-97FFH 9800-9FFFH A000-A7FFH A800-AFFFH B000-B7FFH B800-BFFFH 1. Looking at the truth table, we can see the address lines A13 to A11 taking on values that increment, starting from 000 to 111. If we assign these lines to a 74138, we can enable up to 8 devices one at a time, depending on the values of A13 to A11. 2. Comparing this with the truth table of the 74138, we see that A13 should be assigned to input C, A12 to B and A11 to A. Note that this incrementing bit pattern is only true for this situation. Other situations will have different patterns at different address lines. The important thing is to look out for a pattern to fit to the truth table of the 74138. 3. It is convenient to let A15 to A14 be enabled by the 74LS85, so it activates when it has the value 2H. page 3-7 Chapter 3 Decoding on a bus system Embedded Computer Systems The final design is shown below: 74LS85 A14 A15 0 1 +5 A0 A1 A2 A3 B0 B1 B2 B3 A>Bi A=Bi A<Bi A0 A10 74LS138 A>Bo A=Bo A<Bo A11 A12 A13 A B C 0 1 2 3 4 G2A G2B 5 6 G1 7 6116 6116 8000H to 87FFH 8800H to 8FFFH 6116 9000H to 97FFH 9800H to 9FFFH CE CE CE CE CE CE CE CE B800H to BFFFH B000H to B7FFH A800H to AFFFH A000H to A7FFH 6116 6116 6116 6116 CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 6116 Fig 3.6 Circuit which memory maps 16KB of SRAM starting from 8000H 3.2 Input / Output Decoding The 8080 is able to access buffers and latches, but now we consider the use of SMI bus to do so. As we have seen, memory devices use only some of the available address lines. The lower address lines will select a single memory location in the memory device. The higher address lines from the system are used by a decoder to select one of several memory devices. Also, the memory device will have an Output Enable pin for a read and a RAM device will also have a Write Enable pin. 3.2.1 Single address decoding However, buffers and latches have only a single address location. The PC architecture has used up quite a few I/O addresses so that there are few left for the user. Also, other devices connected to the system may have used up other address. Thus we need to decode each device exactly, so we do not activate other I/O by accident. What this means is that for a 16 bit I/O address space such as that available on Intel microprocessors we need to use all address lines, giving us theoretically 64K addressable I/O devices. But we note that the SMI implementation only uses 6 bits, making the hardware requirements somewhat simpler. Also, since buffers have only one control pin (normally the Enable pin) and latches use the clock pin, we need an external gate to control the access, so that processor reads are directed to buffers and writes are directed to latches. Of course, if there is no confusion as to the assignment of addresses, the gates may not be required. page 3-8 Chapter 3 Decoding on a bus system Embedded Computer Systems Example: Design an input port of address 30H and an output port of address 31H. Truth Table A5 A4 A3 A2 A1 A0 1 1 1 1 0 0 0 0 0 0 1 0 31H 30H We let A0-A2 be decoded by the 74138. The bit pattern on the ‘B’ inputs correspond to bits A3 to A5. 74LS244 74LS85 A3 A4 A5 0 1 1 +5 D7 A0 A1 A2 A3 B0 B1 B2 B3 iA>B iA=B iA<B D0 74LS138 oA>B oA=B oA<B A0 A1 A2 A 0 B 1 C 2 30H CE 74LS374 31H CK CS0 CS1 3 4 E1 5 E2 6 E3 7 SOE SWE Fig 3.7 I/O decoding with 74LS85 As we see, the 74LS85 in conjunction with a 74138 allows us to decode individual I/O addresses. The 74LS85 activates a block of 8 devices through the 74138. The starting address of this block will have the A0-A2 pins at logic 0. This address is known as the base address as all the other I/O addresses are simply added to the base to get its address. 3.3 Summary In summary, we saw how memory and I/O devices may be decoded on the 8080 and SMI busses respectively. The TTL chips 74LS85 and 74138 helped us to easily and flexibly do this. The main differences between memory and I/O is that: i) Memory devices contain many storage locations within itself. Selecting a memory chip through a decoder only enables the chip. Internal decoding circuitry within the memory chip will select individual memory locations. Buffers and latches, being individual devices, need full decoding to be done externally as it does not have the circuitry internally. page 3-9 Chapter 3 Decoding on a bus system ii) Embedded Computer Systems In addition to enable pins, memory devices have control pins which determine whether data is written or read to. Buffers and latches are normally activated through a single control pin. Again, external gates may be needed to correctly decode the signal. Some examples of current devices that use the 8080 bus are given in the following online links. https://www.st.com/resource/en/application_note/cd00200423-using-the-highdensitystm32f10xxx-fsmc-peripheral-to-drive-external-memories-stmicroelectronics.pdf https://www.nxp.com/docs/en/supporting-information/FTF-ACCF1179_Introduction_to_FlexIO.pdf https://www.raspberrypi.org/documentation/hardware/computemodule/datasheets/rpi_ DATA_CM3plus_1p0.pdf page 3-10