Makefiles: Targets, Prerequisites, and Compilation

• The make utility executes a sequence of commands found in a description file.
• It can be used to create executables and perform other tasks such as removing Files, reporting project status, package files, install, build libraries and more.

Alternatives to Make

• The ant utility is similar for Java
• Cmake is supposed to be an improved make
• make is still the most common

Makefiles and Compiler Toolchains

• The make is separate from the compiler toolchain
• It automates code building by passing flags to compilers, specifying paths, and setting library names.
• It's essential to comprehend how the compiler toolchain functions to employ makefiles effectively.

Using Make

• There are many approaches to makefile creation.
• Programmers usually have their own preferred coding approaches.
• Exposure helps learning and avoids treating makefiles as "magical incantations."
• It is best use to very straightforward conventions for readability.

Examining Files

• Makefiles examine dependencies between files, including their dates and existence.
• If files do not exist, make attempts to build them
• If dependencies have newer dates than compiled files, recompilation occurs.

Makefile Structure

• Consists of three parts
  • Target
  • Prerequisites or Dependencies
  • Command Line

Makefile Target

• It is what a makefile entry builds
• Targets are typically filenames, such as executables or libraries
• Example being myprog or librecord.so

Prerequisites

• These are files that must exist for a target to be buildable; for example, building myprog may require myprog.c and myprog.h
• The command line executes if any prerequisites are newer than the target
• Only the files needing recompilation are recompiled.

Makefiles and Efficiency

• Recompiling files that require recompilation is beneficial for large applications.

Command Line

• It's typically a Unix/Linux command-line utility with arguments to build the target using dependencies.
• The command line needs a single tab character before it, not spaces.

Invoking Make

• Typing make alone will search for a Makefile or makefile and build the first target.
• Typing make <target> will build the specified target directly.

Typing Make Examples

• make myprog builds myprog
• make fred builds fred
• Just typing make builds myprog since it's the first target in the makefile.

Common Targets

• Targets don't always have to be files
• For example, clean is to clean up files
• In examples, clean typically deletes: all targets, executables, library files, temporary .o files, and the core file.

Checking Commands

• The -n flag displays commands make would execute without executing them
• make -n displays commands for the first target
• make someTarget -n displays commands for someTarget

Multiline Commands

• Multiple lines can be in the command line, using a semi-colon to separate them.
• libawesome.a: awesome.c followed by commands on separate lines
• Backslashes mean to continue to the next line but it must be the last character on the line

Makefile Macros

• Macros are to avoid repeatedly typing text in makefiles.
• Paths, compiler flags, and lists of libraries often appear in a makefile, and may be annoying to retype.
• Macros replace long strings
• Defined with e.g. LIBS = -L/usr/local/lib -lm -llibname
• Referenced $(LIBS) or ${LIBS}

Sample Macro Example

• Macro names are in uppercase normally
  • CC = gcc
  • LIBS = -lm -L/usr/local/lib -L. -lmyLib
  • prog: prog.c
  • $ (CC) prog.c -o prog $ (LIBS)

Sample Macro Example Specifics

• Compiles using gcc, but CC macro can change to specify an alternative compiler like clang
• Links libraries in m, i.e C math library, and myLib
• The linker will look for the search path for libraries in /usr/local/lib and the current directory, in addition to its standard search path

Undefined Macros

• Undefined macros replaced with a null string
• gcc a1.o -o a1 will execute since the command uses an undefined macro

Predefined Macros

• Macro CC is predefined as command cc; it's usually a symbolic link to the distribution's default C compiler (*nix).
• It's commonly either GNU C or the LLVM C compiler.
• Macro LD is predefined as command ld.
• These can be used without definition, or replace them with something else.

Macro String Substitution

• Allows using a macro and substituting a string.
• In the SRCS = a.c b.c c.c example, SRCS can be referenced with
• $ (SRCS: .c = .०) translates the list to: a.o b.o c.o
• Executable names are created using source filenames a.c, b.c, and c.c.
• These allow you to specify prerequisites
• Reduce clutter in a makefile for large projects with many prerequisites.

More on Macro String Substitution

• $ (SRCS: .c = ) translates to: a b c
• Using names of source files can create names of executables

Suffix Rules

• They tell the system how to compile different types of files automatically
• C files typically end with .c, Fortran files with .f, and C++ files with .cc.
• Make has built-in rules to turn a source code file into an executable.
• Type make -p to see the predefined macros

Comments

• Comments start with # and continue until the end of the line.

Flags Control Options

• The C toolchain components are controlled using makefiles
• Some IDEs let you change the flag by selecting options in property pages
• Others--multi-platform ones--use make and provide lists of flags to modify.

Selecting Compiler

• Using CC=gcc will select the gcc compiler.
• On a Mac, the command line "gcc" is an alias for the Clang compiler, unless you specifically install GNU gcc.
• Pass options to elements of the compiler toolchain.

Preprocessor Flags

• Preprocessor: CPPFLAGS=
• -Iinclude_file_dir will add the file of the directory to the include paths of both includes <> and "", this helps avoid hardcoding relative with the #include statements with -I~/myproj/include it will add to the path of the source files

Useful Preprocessor Flags

• -Dsymbol[=value] is equivalent to #define symbol value
• -DNDEBUG disables assertions within the code

Compiler Flags

• Compiler: CFLAGS=
  • -g saves symbol for debugger
  • -On optimization level (0,1,2,3)
  • -Wall -std=c11 all warnings, C11 standard.
  • -fpic position-independent code for shared object libraries
  • -c compiles .o file.
  • The -c flag goes in the command, compiling to .o file.

Linker Flags

• Linker: LDFLAGS=
  • -Llibrary_dir will pass a library path to the linker
    • -L~/myproj/lib adds as containing linked files in library.
  • -llibrary, links library
    • -Ifoo links libfoo.so (or .a).
  • -shared creates shared object library These flags are used in the actual command
  • -o filename creates output file with name, instead of default names
    • -o caltest creates an output file with the name caltest

Code Organization

• Large C codebases are often broken up into folders
• Headers go into the include directory
• Source code goes into the src directory
• Binary Files go into folders like bin, lib etc

Real World Project ex Curl

• The curl library uses the code structure
• The libraries used will follow the specific type of code structure which depends on the project.

Standard Code organization for the Course

• They are to follow a similar convention in their code
• The code goes in src
• Header files go in include
• Main makefile is in main
• Assignment description will explain exact details

Using Makefile Macros Code Examples

• Use macros to define locations of code and headers.
  • INC = include/
  • SRC = src/
• Use macros in makefile
• The dependencies can be the command line -$ (CC) $ (CFLAGS) –I$ (INC) -c $ (SRC) StructListDemo.c

Explore Makefiles: how make uses prerequisites to determine if a target needs recompilation. Understand the effects of spaces vs tabs and the function of compiler flags. Learn how to build specific targets and the importance of selective recompilation in large projects.