CAP 3 - Datapaths and Stalls: Control Hazards and Hardware Forwarding

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Questions and Answers

What can cause greater performance losses compared to data hazards?

Conditional branches

Hardware forwarding

Control hazards (correct)

Address calculation

In the context of conditional branches, what does a taken branch refer to?

A branch that maintains the current PC value

A branch that changes the PC to the branch's target address (correct)

A branch that causes a one-cycle stall

A branch that skips the next instruction

What method is commonly used to cope with branches in the context of pipeline stalls?

Increasing the pipeline stages

Skipping the branch instruction

Redoing the fetch of the instruction following a branch (correct)

Freezing the pipeline

Which scheme is illustrated by the predicted-not-taken scheme?

Predicted-taken scheme Signup and view all the answers

What is a one-cycle stall in a five-stage pipeline typically associated with?

Branch instructions Signup and view all the answers

What is the performance loss range typically associated with a one-stall cycle per branch?

10-30% Signup and view all the answers

What happens when a branch is untaken in the predicted-not-taken scheme?

The fetch and fall-through occur ordinarily Signup and view all the answers

In the delayed branch scheme, what happens if the branch is taken?

Execution continues with the instruction after the branch delay instruction Signup and view all the answers

What is a characteristic of processors implementing the delayed branch scheme?

They use a single instruction delay Signup and view all the answers

What is the purpose of having a branch delay slot in the delayed branch scheme?

To always execute instructions in that slot Signup and view all the answers

How was the delayed branch scheme utilized in early RISC processors?

Heavily used Signup and view all the answers

In the predicted-not-taken scheme, when is the target address known?

Not known any earlier than the branch outcome Signup and view all the answers

What is the primary purpose of branch prediction in pipelined processors?

To improve performance by guessing the outcome of branch conditions Signup and view all the answers

Which of the following statements about branch prediction is true?

Prediction is effective when the hit rates are high, such as in end-of-loop testing or searches Signup and view all the answers

What is the primary advantage of a pipelined processor over a multiple clock cycle processor?

Each functional unit can be used only once per instruction Signup and view all the answers

Which of the following techniques is commonly used in superscalar processors to address branch prediction?

Speculative execution Signup and view all the answers

What is the purpose of branch delay slots in pipelined processors?

To improve performance by allowing instructions to be executed while a branch is being resolved Signup and view all the answers

Which of the following statements about pipelined processors is true?

Instructions must use functional units at the same stage as other instructions Signup and view all the answers

What is the purpose of the instruction fetch (IF) cycle?

To fetch the next instruction from the instruction memory and update the program counter (PC) register Signup and view all the answers

What is the purpose of the new program counter (NPC) register?

To store the address of the next sequential instruction in memory Signup and view all the answers

What is the purpose of the instruction register (IR)?

To store the instruction that will be worked on in subsequent clock cycles Signup and view all the answers

In which cycle is the PC register updated?

Memory access/branch completion (MEM) cycle Signup and view all the answers

Which statement is true about the multiple-cycle implementation of MIPS instructions?

Every MIPS instruction can be implemented in at most five clock cycles Signup and view all the answers

Which of the following is not one of the five clock cycles in the multiple-cycle implementation of MIPS instructions?

Data transfer (DT) Signup and view all the answers

Explain the purpose of the new program counter (NPC) register in the multiple-cycle implementation of MIPS instructions.

The NPC register holds the address of the next sequential instruction in memory. It is incremented by 4 from the current program counter (PC) value during the instruction fetch (IF) cycle, so that it can be used to update the PC in the subsequent memory access (MEM) cycle. Signup and view all the answers

Describe the purpose of the branch delay slot in the delayed branch scheme used in early RISC processors.

The branch delay slot in the delayed branch scheme was used to improve performance by executing an instruction immediately following the branch instruction, even if the branch was taken. This helped to hide the latency of the branch instruction and keep the pipeline full. Signup and view all the answers

Explain how branch prediction is commonly used in superscalar processors to address branch hazards.

Superscalar processors often use branch prediction techniques, such as the predicted-not-taken scheme, to speculate on the outcome of conditional branches. This allows the processor to continue executing instructions down the predicted path, avoiding pipeline stalls due to branch hazards. Signup and view all the answers

Discuss the primary advantage of a pipelined processor over a multiple clock cycle processor in terms of instruction-level parallelism.

The primary advantage of a pipelined processor over a multiple clock cycle processor is the ability to achieve higher throughput by overlapping the execution of multiple instructions. In a pipelined processor, instructions can be executed concurrently, allowing for greater instruction-level parallelism and improved overall performance. Signup and view all the answers

Explain the purpose of the instruction fetch (IF) cycle in the multiple-cycle implementation of MIPS instructions.

The purpose of the instruction fetch (IF) cycle is to fetch the current instruction from the instruction memory (IMem) and load it into the instruction register (IR). During this cycle, the program counter (PC) is also incremented by 4 to point to the next sequential instruction in memory. Signup and view all the answers

Describe the performance impact of a one-cycle stall per branch in a five-stage pipeline, and explain the typical range of performance losses associated with this type of stall.

A one-cycle stall per branch in a five-stage pipeline can have a significant impact on performance, typically resulting in a performance loss in the range of 10-20%. This is because the branch stall causes a pipeline bubble, which reduces the overall throughput of the processor. Signup and view all the answers

What are the potential consequences if the instruction in the branch delay slot of the delayed branch scheme is also a branch?

If the instruction in the branch delay slot is also a branch, it can lead to a cascade of branch delays, potentially causing significant performance degradation. This is because the execution of the second branch would also be delayed, creating a chain reaction that could stall the pipeline for multiple cycles. Signup and view all the answers

Explain the key difference between the predicted-not-taken scheme and the delayed branch scheme in terms of branch target address determination.

How does the delayed branch scheme address the performance impact of branches in a pipelined processor, and what are the potential drawbacks of this approach?

The delayed branch scheme addresses the performance impact of branches by executing the instruction in the branch delay slot regardless of whether the branch is taken or not, thereby reducing the number of pipeline stalls. However, this approach can lead to issues if the instruction in the delay slot is also a branch, potentially causing a cascade of branch delays and further performance degradation. Signup and view all the answers

Contrast the branch target address determination process in the predicted-not-taken scheme and the delayed branch scheme, and discuss the implications of each approach on pipeline performance.

In the predicted-not-taken scheme, the branch target address is not known until the branch outcome is verified during the ID cycle, whereas in the delayed branch scheme, the target address is known earlier, during the branch delay slot execution. The predicted-not-taken scheme can lead to more pipeline stalls due to the delayed target address determination, while the delayed branch scheme can mitigate this issue but introduces the potential for a cascade of branch delays if the delay slot instruction is also a branch. Signup and view all the answers

Explain how the delayed branch scheme addresses the performance impact of branches in a pipelined processor, and discuss the potential drawbacks of this approach compared to the predicted-not-taken scheme.

Analyze the trade-offs between the predicted-not-taken scheme and the delayed branch scheme in terms of their impact on pipeline performance, and discuss the potential consequences of a branch instruction appearing in the branch delay slot of the delayed branch scheme.

The predicted-not-taken scheme can lead to more pipeline stalls due to the delayed branch target address determination, while the delayed branch scheme can mitigate this issue by executing the instruction in the branch delay slot regardless of whether the branch is taken or not. However, the delayed branch scheme introduces the potential for a cascade of branch delays if the instruction in the delay slot is also a branch. This can cause significant performance degradation, as the execution of the second branch would also be delayed, creating a chain reaction that could stall the pipeline for multiple cycles. Signup and view all the answers

Explain how the predicted-not-taken scheme handles branch instructions in a pipelined processor, and what potential performance penalty is incurred if the branch is actually taken.

In the predicted-not-taken scheme, the processor assumes that branch instructions will not be taken (i.e., the next sequential instruction will be executed). If the branch is not taken, no penalty is incurred. However, if the branch is taken, the pipeline must be flushed and refilled with instructions from the branch target address, resulting in a multi-cycle penalty. Signup and view all the answers

Describe the purpose and operation of branch delay slots in the delayed branch scheme, and how they were utilized in early RISC processors.

In the delayed branch scheme, one or more instructions immediately following the branch instruction are executed, regardless of whether the branch is taken or not. These instructions are called branch delay slots. Early RISC processors utilized this scheme to improve performance by allowing useful work to be done while the branch was being resolved. Signup and view all the answers

Explain the significance of control hazards in pipelined processors, and how they can cause greater performance losses compared to data hazards.

Control hazards arise from branching instructions, which can cause the processor to fetch and execute instructions from an incorrect path. If a branch is mispredicted, the entire pipeline may need to be flushed and refilled, resulting in a significant performance penalty. Data hazards, on the other hand, can often be resolved through techniques like forwarding or stalling, which have a relatively smaller impact on performance. Signup and view all the answers

Discuss the trade-offs between the predicted-not-taken, predicted-taken, and delayed branch schemes in terms of their impact on performance, complexity, and branch prediction accuracy.

The predicted-not-taken scheme is simple but can incur significant penalties for taken branches. The predicted-taken scheme can improve performance for taken branches but may suffer penalties for untaken branches. The delayed branch scheme can improve performance by allowing useful work during branch resolution but requires compiler support and may not always have suitable instructions to fill the delay slots. Overall, there is a trade-off between performance, complexity, and branch prediction accuracy. Signup and view all the answers

In the context of pipelined processors, explain the purpose and operation of the instruction fetch (IF) cycle, and how it relates to the other pipeline stages.

The instruction fetch (IF) cycle is the first stage of the pipeline, where the processor fetches the next instruction from memory using the program counter (PC). The fetched instruction is then passed to the subsequent pipeline stages for decoding, execution, memory access, and writeback. The IF stage must be coordinated with the other stages to ensure smooth and efficient pipeline operation. Signup and view all the answers

Describe the techniques used in superscalar processors to address branch prediction, and how they differ from the approaches used in scalar processors.

Superscalar processors employ more advanced branch prediction techniques, such as branch target buffers (BTBs) and branch history tables (BHTs), to predict the outcome and target address of branches more accurately. These techniques leverage past branch behavior and can handle multiple branches in flight simultaneously, unlike the simpler schemes used in scalar processors. Signup and view all the answers

Explain the key tradeoff involved in the delayed branch technique and how compilers can optimize this approach.

The delayed branch technique introduces a delay slot after branch instructions where useful instructions can be placed to improve performance. However, compilers must carefully choose the instructions for this slot to ensure they are effectively executed regardless of whether the branch is taken or not. The tradeoff is between introducing this delay for all branches versus the potential performance gains from filling the delay slot with useful work. Signup and view all the answers

Describe the premise behind branch prediction and why it can improve performance when prediction hit rates are high.

Branch prediction involves guessing the outcome of a branch condition and proceeding execution as if that guess were correct. The key premise is that processor state cannot be affected by any misprediction. When predictions are often correct (high hit rates), execution can proceed without stalls, improving performance. Common cases with good prediction like loop branches and failed searches enable these performance gains. Signup and view all the answers

Compare and contrast the multiple clock cycle and pipelined implementations of processors, highlighting the key advantage of pipelining.

In a multiple clock cycle processor, each functional unit can only be used once per instruction, with all instructions using the units in the same stage. A pipelined processor overlaps execution of instructions, with each stage handling a different instruction concurrently. This enables much higher throughput as multiple instructions are effectively executed in parallel, which is the key advantage of pipelining. Signup and view all the answers

Explain how the predicted-not-taken scheme for branch prediction operates, including when the target address is known and what happens on a taken versus untaken branch.

In the predicted-not-taken scheme, the processor continues executing sequentially after a branch. If the branch is untaken (falls through), no penalty is incurred as the next instructions are already being fetched. If the branch is taken, execution must stall while the target address is fetched and fed into the pipeline. The target address is only known after the branch condition is evaluated, incurring some delay on taken branches. Signup and view all the answers

Describe a scenario where branch prediction hit rates may be low, potentially negating its performance benefits. Justify your answer.

Branch prediction hit rates may be low in code with many unpredictable data-dependent branches, such as those dependent on complex calculations or input data. In these cases, past branch behavior provides little information to reliably predict future branches. Low hit rates mean frequent mispredictions, causing pipeline flushes and stalls that can severely degrade performance, potentially negating the benefits of branch prediction. Signup and view all the answers

Elaborate on the statement: "These techniques are generally used in superscalar processors, which will be addressed in the later chapters." What additional capabilities might superscalar processors require to effectively utilize branch prediction and related techniques? Provide a specific example.

Superscalar processors can issue and execute multiple instructions per cycle, so they likely require more advanced branch prediction capabilities to keep multiple pipelines fed efficiently. For example, they may utilize more sophisticated predictors that can predict multiple branches per cycle, or predictors that integrate more complex heuristics and history tracking for better accuracy on harder-to-predict branches. Signup and view all the answers

Study Notes

Branch Prediction Schemes

When a branch is untaken, verified during the ID cycle, the scheme goes to the fetch and fall-through ordinarily.
When a branch is taken, verified during ID, the fetch is redone at the branch target.

Predicted-Not-Taken Scheme

Treats every branch as not taken.
In a five-stage MIPS pipeline, the target address is not known earlier than the branch outcome (taken or untaken).
This approach has no advantage in this pipeline.

Delayed Branch Scheme

Heavily used in early RISC processors.
Instructions in the delay slot are always executed.
If the branch is untaken, execution continues with the instruction after the branch delay instruction.
If the branch is taken, execution continues at the branch target.

Control Hazards

Can cause greater performance losses compared to data hazards.
Conditional branch execution may or may not change the program counter (PC) to a value other than its current value plus four (PC=PC+4).
If a conditional branch changes the PC to the branch's target address, it is a taken branch; otherwise, it is an untaken branch.

Performance Loss

One-cycle stall in a five-stage pipeline can result in a performance loss of around 10-30%.

Schemes to Cope with Branches

Predicted-not-taken scheme
Predicted-taken scheme
Delayed branch scheme
Branch prediction scheme to guess the outcome of the branch condition and proceeding as if the guessing were correct.

MIPS Simple Multiple-Cycle Implementation

Every MIPS instruction can be implemented in at most five clock cycles: instruction fetch (IF), instruction decode/register fetch (ID), execution/effective address (EX), memory access/branch completion (MEM), and write-back (WB).
Each functional unit can be used only once per instruction.
Instructions must use functional units at the same stage like all other instructions, bringing considerable performance improvements.

Pipeline Processor

Considered an enhancement of the multiple clock cycle processor.
Each functional unit can be used only once per instruction.
Instructions must use functional units at the same stage like all other instructions, bringing considerable performance improvements.

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Description

Learn about control hazards, hardware forwarding, and the impact of conditional branches on program counter (PC) in datapaths. Understand the difference between taken and untaken branches in control flow.