CSIT 230: ARM Assembly Language

Which ARM register is typically used for system calls, indicating the desired action to the OS?

What does the acronym CPSR stand for in ARM architecture?

Which register stores the memory address to return to after the function call is finished?

When does the Negative flag (N) in CPSR get set?

When is the Zero flag (Z) in the CPSR set?

In ARM assembly, what is the primary function of registers R0-R3?

What is the primary function of the SPSR register in ARM architecture?

In ARM assembly, what is the result of the logical operation AND R2, R0, R1 if R0 = 0b1010 and R1 = 0b1100?

If register R0 contains the value 0xFF (0b11111111) and register R1 contains the value 0x0F (0b00001111), what will be the value of register R2 after the operation EOR R2, R0, R1?

What is the result of the MVN R1, R0 instruction if R0 holds the value 0x00000001?

In ARM assembly, the instruction MVN R1, R0 is used to perform a bitwise NOT operation. If R0 = 0, what would be the decimal value of R1 after this operation?

Which logical operation is not natively supported and requires two instructions to implement?

What is the combined effect of the following ARM assembly instructions, assuming R0 = 1 and R1 = 1: AND R2, R0, R1 followed by MVN R2, R2?

If R0 = 0b1100 and R1 = 0b1010, what is the value of R2 after the following instructions: AND R2, R0, R1 and MVN R2, R2?

In the context of ARM assembly, what does "native" support for a logical operation imply?

Given R0 = 0b1100 and R1 = 0b1010, what is the result of executing the following instructions: ORR R2, R0, R1 followed by MVN R2, R2?

Which of the following best describes the additional overhead introduced by using a non-native logical operation like NAND in ARM assembly?

What is the result of EOR R2, R0, R1 followed by MVN R2, R2 if R0 = 0b1100 and R1 = 0b1010?

In ARM assembly, if R0 contains the value 5 and R1 contains the value 3, what will R2 contain after executing ANDS R2, R0, R1?

What would be the output, in decimal, of the following ARM code snippet?

MOV R0, #10
MOV R1, #3
EORS R2, R0, R1

Which URL provides access to an ARM emulator?

Which of the following registers in ARM assembly is used to hold the memory address of the next instruction to be executed?

The Carry flag (C) in CPSR is set when?

The Overflow flag (V) in the CPSR is set when?

Assume R0 = 5. What will R1 contain after the following is run?

MVN R1, R0

Registers R4-R6 are typically for?

What will R2 contain after the following code block is executed, if R0 = 1 and R1 = 0?

ORR R2, R0, R1

Given R0 = 0b1010 and R1 = 0b1100, what is R2 after executing the instruction AND R2, R0, R1?

If register R0 = 0b11110000 and register R1 = 0b11111111, what is the value of register R2 after executing the following assembly instruction? ANDS R2, R0, R1

In ARM assembly, which instruction performs a bitwise exclusive OR operation?

Assume that R0 = 0b11001100 and R1 = 0b10101010. What value will R2 have after executing the following instruction?

EOR R2, R0, R1

In ARM assembly, what does the instruction MVN generally do?

Given R0 = 0x5 and R1 = 0xA, what will be the value of R2 after the following instructions are executed?

ORR R2, R0, R1
MVN R2, R2

Which of the following logical operations is not directly supported as a native instruction in ARM assembly?

If a logical operation is not natively supported in ARM assembly, what is needed to implement it?

What type of overhead is usually associated with implementing a non-native logical operation in ARM assembly?

Which of these snippets of code is an implementation of NOR in ARM? Assume R0 and R1 are input and R2 is the output.

What actions does the CPSR, or Current Program Status Register, perform?

What actions does the LR, or Link Register, perform?