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What is the likelihood that Bob will need the hammer again after attaching the first board an example of?
Instructions can exhibit spatial locality, but never temporal locality.
False
What is the primary difference between SRAM and DRAM technologies?
SRAM is faster and more expensive than DRAM.
Flash memory is a type of electrically erasable programmable read-only memory (_____).
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The high likelihood of accessing element $A[i]$ repeatedly in a loop demonstrates which type of locality?
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Match the following types of memory with their characteristics:
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Data can exhibit spatial locality but never temporal locality.
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What determines the cache index in a direct-mapped cache?
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Study Notes
Locality of Reference
- The likelihood that Bob will need the hammer again is an example of temporal locality.
- Temporal locality is the tendency for a program to access the same memory locations repeatedly over a short period.
- The likelihood that Bob will need other tools stored in the garage is an example of spatial locality.
- Spatial locality is the tendency for a program to access memory locations that are near to each other.
- The high likelihood of accessing multiple elements within array A in the loop is an example of spatial locality.
- The high likelihood of accessing i = i + 1 repeatedly in the loop is an example of temporal locality.
- Instructions may exhibit temporal locality, but never spatial locality.
- Data may exhibit spatial locality, but never temporal locality.
Memory Technologies
- SRAM (Static Random Access Memory) is a type of memory that uses latches to store data.
- DRAM (Dynamic Random Access Memory) is a type of memory that uses capacitors to store data.
- Flash memory is a type of electrically erasable programmable read-only memory (EEPROM).
Cache Basics
- Cache index is calculated based on the block address and the cache size.
- The tag and valid bits are used to access the cache.
- If a request misses the cache, the data is fetched from the main memory and stored in the cache.
- The index and tag fields are shown in binary in the cache contents after each miss.
Cache Size Calculation
- Cache size is determined by the address size, cache data size, and cache block size.
- For a direct-mapped cache with:
- Address size: 32 bits
- Cache data size: 2 KiB
- Cache block: 2 words
- Calculate the cache index:
- Cache index = log2(Cache data size / Cache block size) = log2(2 KiB / 2 words) = log2(1024 bytes / 8 bytes) = log2(128) = 7 bits
- Calculate the number of tag bits:
- Tag bits = Address size - Cache index - log2(Cache block size) = 32 bits - 7 bits - log2(8 bytes) = 32 bits - 7 bits - 3 bits = 22 bits
- Calculate the number of valid bits:
- Valid bits = 1 bit
- Calculate the total number of bits per cache line:
- Total bits = Tag bits + Valid bits + Cache block size = 22 bits + 1 bit + 8 bytes = 31 bits + 64 bits = 95 bits
- Calculate the total number of cache lines:
- Cache lines = Cache data size / Cache block size = 2 KiB / 2 words = 1024 bytes / 8 bytes = 128
- Calculate the total cache size in bits:
- Total cache size = Total bits per cache line * Cache lines = 95 bits * 128 = 12,160 bits = 1.5 KiB
Dependable Memory Hierarchy
- A dependable memory hierarchy is a system that uses multiple levels of memory to improve performance and reliability.
- Lower levels of memory are faster but smaller, while higher levels of memory are slower but larger.
- The hierarchy is designed to ensure that the most frequently used data is stored in the fastest memory levels.
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Description
This quiz explores key concepts in computer memory, focusing on locality of reference, which includes temporal and spatial locality. It also covers different memory technologies like SRAM and DRAM. Test your understanding of these vital concepts in computer architecture.
