Memory Day 1 PDF

Memory In Computer Systems 1) Bob is building a fence behind his 3) Given the following loop, the house. He uses a hammer to high likelihood of accessing attach a board to the rail. Bob multiple elements within array then measures and cuts the ne...

Memory In Computer Systems 1) Bob is building a fence behind his 3) Given the following loop, the house. He uses a hammer to high likelihood of accessing attach a board to the rail. Bob multiple elements within array then measures and cuts the next A is an example of _____ board. locality. while (i < 10){ A[i] = A[i] + 2; i The likelihood that Bob will need the hammer again is an example = i + 1; } of _____ locality. 4) 2) Given the following loop, the Bob is building a fence behind his high likelihood of accessing i = house. He grabs a hammer from i + 1 repeatedly is an example the garage. Bob will likely need of _____ locality. additional tools stored in the garage, so Bob also grabs nails, a while (i < 10) shovel, and a level. { A[i] = A[i] + 2; i = i + 1; } The likelihood that Bob will need 5) Instructions may exhibit temporal locality, but never spatial locality. 6) Data may exhibit spatial locality, but never temporal locality. Memory technologies  Primary technologies used in memories. SRAM technology DRAM technology Price source is https://jcmit.net/memoryprice  Flash memory is a type of electrically erasable programmable read-only memory (EEPROM). Magnetic disk access times. The basics of caches Determine the cache index given the direct-mapped cache size and block address. Determine the cache index as a binary value. Ex: 110 Accessing a cache using the tag and valid bits. The cache contents are shown after each reference request that misses, with the index and tag fields shown in binary for the sequence of addresses in the previous table Example: Bits in a cache. How many total bits are required for a direct-mapped cache with 16 KiB of data and 4-word blocks, assuming a 32-bit address? Calculating cache size. Assume a direct- mapped cache with the following parameters: Address size: 32 bits Cache data size: 2 KiB Cache block: 2 words Dependable memory hierarchy