Computer Architecture Quiz
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Questions and Answers

Which register holds the address of the next instruction to be fetched?

  • MAR
  • IR
  • MBR
  • PC (correct)

    • What is the purpose of the Instruction Register (IR)?

  • To hold the data being processed by the CPU
  • To control the flow of data between the CPU and memory
  • To store the address of the next instruction
  • To store the current instruction being executed (correct)

    • What is the main action performed during the execute cycle?

  • Performing the operation specified by the instruction (correct)
  • Storing the result of the operation in memory
  • Decoding the current instruction
  • Fetching the next instruction from memory

    • Which of these actions is NOT performed during the execute cycle?

    <p>Fetching the next instruction from memory (A)</p> Signup and view all the answers

    What does the abbreviation 'HLT' stand for in assembly language?

    <p>Halt (D)</p> Signup and view all the answers

    In the example program execution steps, what is the first instruction fetched from memory?

    <p>1940 (C)</p> Signup and view all the answers

    What is the address of the memory location from which data is to be loaded in the second instruction?

    <p>940 (C)</p> Signup and view all the answers

    Which of these instructions is responsible for adding the contents of memory location 941 to the accumulator (AC)?

    <p>2941 (C)</p> Signup and view all the answers

    What determines the maximum possible memory capacity of a system?

    <p>The width of the address bus (B)</p> Signup and view all the answers

    Which option indicates that a module has been granted control of the bus?

    <p>Bus grant (B)</p> Signup and view all the answers

    What is the purpose of the memory write operation?

    <p>To cause data on the bus to be written into the addressed location (D)</p> Signup and view all the answers

    In a shared bus architecture, which module is traditionally addressed by the higher-order bits?

    <p>The I/O module (B)</p> Signup and view all the answers

    Which component is used to synchronize operations within the bus?

    <p>Clock signal (D)</p> Signup and view all the answers

    What is a key reason for the transition from shared bus architecture to point-to-point interconnection?

    <p>Limitations of electrical constraints with frequency increases (D)</p> Signup and view all the answers

    What signal indicates that data has been accepted from or placed on the bus?

    <p>Transfer ACK (B)</p> Signup and view all the answers

    When a module wishes to request data from another module, what is the first action it must take?

    <p>Obtain the use of the bus (B)</p> Signup and view all the answers

    What is the primary function of the transaction layer (TL) in PCIe?

    <p>To create and transmit request packets (D)</p> Signup and view all the answers

    What is the unique feature of the split transaction technique in PCIe?

    <p>It separates the request and completion in time (B)</p> Signup and view all the answers

    Which of the following address spaces is NOT supported by the PCIe transaction layer?

    <p>Cache (B)</p> Signup and view all the answers

    What is the role of the data link layer (DLL) in PCIe?

    <p>To ensure reliable delivery of packets (C)</p> Signup and view all the answers

    What technique does the PCIe data link layer use to detect errors in data?

    <p>Cyclic redundancy check (CRC) (A)</p> Signup and view all the answers

    Which address space in PCIe is primarily used for control signals related to interrupts?

    <p>Message (B)</p> Signup and view all the answers

    What happens to other PCIe traffic while waiting for a completion packet?

    <p>It may use the link while waiting (A)</p> Signup and view all the answers

    Who initiates the completion packet in the PCIe transaction process?

    <p>The completer device (B)</p> Signup and view all the answers

    What is a key characteristic of a bus?

    <p>It is a shared transmission medium. (C)</p> Signup and view all the answers

    What occurs when two devices transmit on a bus at the same time?

    <p>The signals will overlap and become garbled. (B)</p> Signup and view all the answers

    What is the primary purpose of data lines in a bus system?

    <p>To provide a path for moving data among system modules. (B)</p> Signup and view all the answers

    When referring to the 'width' of the data bus, what does it represent?

    <p>The number of separate lines in the data bus. (C)</p> Signup and view all the answers

    What distinguishes the system bus in a computer system?

    <p>It connects major computer components like the processor, memory, and I/O. (A)</p> Signup and view all the answers

    How are the lines of a bus classified?

    <p>By functional groups: data, address, and control lines. (D)</p> Signup and view all the answers

    What is the significance of the data bus width in system performance?

    <p>It defines how many bits can be transferred at a time. (D)</p> Signup and view all the answers

    What is the role of address lines in a bus system?

    <p>To designate the source or destination of data on the data bus. (A)</p> Signup and view all the answers

    What is the main function of the root complex in PCIe architecture?

    <p>To buffer differences in data rates between I/O controllers and memory. (C)</p> Signup and view all the answers

    Which device is responsible for managing multiple PCIe streams?

    <p>Switch (B)</p> Signup and view all the answers

    What type of endpoint allows older PCI devices to connect to PCIe systems?

    <p>PCIe/PCI bridge (D)</p> Signup and view all the answers

    What layer is responsible for reliable transmission and flow control in PCIe?

    <p>Data link layer (A)</p> Signup and view all the answers

    What are Data Link Layer Packets referred to in PCIe?

    <p>DLLPs (C)</p> Signup and view all the answers

    Which PCIe layer generates and consumes data packets for load/store data transfer?

    <p>Transaction layer (A)</p> Signup and view all the answers

    What is a characteristic of PCIe ports in terms of lanes?

    <p>They can provide 1, 4, 6, 16, or 32 lanes. (B)</p> Signup and view all the answers

    What does the Physical layer of PCIe consist of?

    <p>The actual wires and supporting circuitry. (D)</p> Signup and view all the answers

    What type of data transfer is used for a processor sending data to an I/O device?

    <p>Processor to I/O (D)</p> Signup and view all the answers

    What is NOT a characteristic of an I/O module?

    <p>Directly accesses main memory without processor involvement (A)</p> Signup and view all the answers

    What is the primary function of a processor in a computer system?

    <p>Execute instructions and process data (C)</p> Signup and view all the answers

    Which of the following is NOT a reason why bus structures are still commonly used in embedded systems?

    <p>High bandwidth for demanding applications (B)</p> Signup and view all the answers

    What is a key advantage of point-to-point interconnection structures over bus structures in modern computer systems?

    <p>Greater scalability and higher bandwidth (C)</p> Signup and view all the answers

    What type of data transfer allows an I/O module to exchange data directly with memory without going through the processor?

    <p>Direct Memory Access (DMA) (A)</p> Signup and view all the answers

    What is a common type of interconnection structure besides the bus?

    <p>Point-to-point (A)</p> Signup and view all the answers

    What is the purpose of a port on an I/O module?

    <p>To connect to external devices through specific interfaces (C)</p> Signup and view all the answers

    Flashcards

    I/O Module

    An I/O module manages data transfer between the computer and external devices and performs read/write operations.

    Ports

    Unique interfaces for I/O modules to connect to external devices, each having a unique address.

    Direct Memory Access (DMA)

    A method that allows I/O modules to exchange data directly with memory without involving the processor.

    Processor

    The central unit that reads instructions from memory, processes data, and controls system operations.

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    Memory to Processor Transfer

    The process where the processor reads instructions or data from the memory.

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    I/O to Processor Transfer

    Data transfer where the processor reads data from an I/O device via an I/O module.

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    Bus Interconnection

    A common method of interconnecting components in a computer system that allows for multiple devices to share paths for data transfer.

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    Point-to-Point Interconnection

    A structure allowing direct data transfer between two devices without intermediate devices, often packetized.

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    Program Counter (PC)

    Register that holds the address of the next instruction to be fetched.

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    Instruction Register (IR)

    Register that holds the fetched instruction from memory.

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    Fetch Cycle

    Process of retrieving the next instruction from memory.

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    Execute Cycle

    Process where the fetched instruction is carried out by the processor.

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    Data Processing

    Operations such as arithmetic or logic conducted by the processor.

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    Control Instruction

    Instruction that alters the sequence of execution, like jumps.

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    Memory Address Register (MAR)

    Register that holds the memory address of the data to be accessed.

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    Memory Buffer Register (MBR)

    Register that holds data being transferred to or from memory.

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    Address Lines

    Conducts addresses from the processor to memory or I/O ports.

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    Address Bus Width

    Determines the maximum possible memory capacity of a system.

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    Control Lines

    Signals which control memory and I/O operations.

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    Memory Read

    Causes data from a memory location to flow onto the bus.

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    Memory Write

    Transfers data from the bus to a specified memory location.

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    Point-to-Point Interconnect

    Connects components directly instead of through a shared bus.

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    Bus Request

    Indicates a module wishes to gain control of the bus.

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    Bus Grant

    Confirms that a module has been given control of the bus.

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    Root Complex

    A buffering device handling I/O controller and memory differences.

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    PCIe Transaction Formats

    Formats translated by root complex for processor and memory signals.

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    PCIe Switch

    Manages multiple PCIe streams between devices.

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    PCIe Endpoint

    An I/O device implementing PCIe, like a graphics controller.

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    Legacy Endpoint

    Supports older designs migrated to PCIe with legacy behaviors.

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    PCIe/PCI Bridge

    Allows older PCI devices to connect to PCIe systems.

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    PCIe Protocol Layers

    Layers including Physical, Data Link, and Transaction that define PCIe interactions.

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    Data Link Layer Packets (DLLPs)

    Packets used for reliable transmission and flow control in PCIe.

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    PCIe Transaction Layer

    The layer that handles read and write requests, creating packets for transfer while using split transactions.

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    Split Transaction Technique

    A method where requests and completions are separated in time, allowing other traffic on the link.

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    Completion Packet

    The response packet sent back to the originator after a request, containing data/status.

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    Unique Identifier

    A tag used in packets to ensure completion packets are delivered to the correct source device.

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    PCIe Address Spaces

    Four address spaces (Memory, I/O, Configuration, Message) used by the Transaction Layer.

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    Memory Address Space

    Part of the PCIe Transaction Layer that includes system memory and maps I/O devices.

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    Data Link Layer

    Ensures reliable packet delivery across the PCIe link and checks for errors.

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    Cyclic Redundancy Check (CRC)

    An error-detecting code used to detect accidental changes to digital data during transmission.

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    Bus

    A pathway for communication connecting devices.

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    Shared transmission medium

    A characteristic where multiple devices connect and share the same bus.

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    Signal overlap

    Occurs when multiple devices transmit at the same time, causing garbled signals.

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    System bus

    Connects major computer components like processor, memory, I/O.

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    Data lines

    Lines that provide paths for moving data among system modules; known as the data bus.

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    Width of data bus

    The number of lines in a data bus, determining bits transferred at a time.

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    Functional groups of bus lines

    Classified into data, address, and control lines for organization.

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    Study Notes

    Computer Organization and Architecture

    • This course studies computer organization and architecture.
    • Key textbooks include Computer Organization and Architecture: Designing for Performance by William Stallings (11th edition, 2019) and Computer Organization and Architecture by John P. Hayes (3rd edition, 2002).
    • Course outcomes include explaining the central processing unit (CPU) function, developing algorithms for memory error correction, designing input/output modules, selecting and using memory addressing modes, listing and defining instruction pipeline stages, and exploring micro instruction sequencing and execution.

    Module 1: Introduction to Computer Architecture

    • Module 1 introduces computer organization and architecture, focusing on a top-level view of computer function and interconnection.
    • A computer is a programmable electronic device that accepts raw data, processes it using instructions (a program), and produces output.
    • It can perform mathematical and logical operations, and save output for later use.
    • The term "computer" comes from the Latin word "computare," meaning to calculate.

    Basic Computer Components

    • Processor: Executes instructions from software and hardware.
    • Memory: Primary memory for data transfer between the CPU and storage.
    • Motherboard: Connects all other computer parts.
    • Storage Device: Permanently stores data (e.g., hard drive).
    • Input Device: Allows communication and data input (e.g., keyboard).
    • Output Device: Displays output (e.g., monitor).
    • Computer types include Micro Computer, Mini Computer, Mainframe Computer, Super Computer, and Workstations.

    Computer Architecture

    • Refers to programmer-visible attributes of a computer system.
    • Instruction Set Architecture (ISA) is another term for computer architecture and defines instruction formats, opcodes, registers, instruction/data memory, the effect of instructions on registers/memory, and the instruction execution algorithm.
    • Key elements of computer architecture include the instruction set, bits used to represent data types, I/O mechanisms, and memory addressing techniques.

    Computer Organization

    • It details the operational units and their interconnections that realize architectural specifications.
    • It covers hardware details transparent to the programmer, such as control signals, computer-peripheral interfaces, and memory technology.
    • Key aspects include control signals, computer-peripheral interfaces, and memory technology.
    • The central processing unit (CPU) has components like the Arithmetic Logic Unit (ALU), Control Unit, Registers, I/O Devices, Main memory and Bus.

    Structure and Function

    • Structure: The way components are interconnected.
    • Function: The operation of each individual component within the structure.
    • Core computer functions include Data Processing, Data Storage, Data Movement, and Control.

    Von Neumann Architecture

    • Data and instructions are stored in a single read-write memory.
    • Memory contents are addressable regardless of data type.
    • Execution occurs sequentially (unless modified).

    Hardware and Software Approaches

    • Programming in hardware involves a sequence of arithmetic and logic functions.
    • Programming in software uses instruction codes interpreted by a general-purpose arithmetic and logic unit.
    • Instruction interpreter and general-purpose arithmetic/logic functions form the CPU.
    • Input and Output (I/O) components handle input data conversion and output result generation.

    Instruction Cycle

    • The instruction cycle involves two main phases: Fetch Cycle and Execute Cycle.
    • Fetch Cycle: The processor fetches instructions from memory sequentially.
    • Execute Cycle: The processor interprets and performs the instructions.
    • Program execution ends when a halt instruction or an unrecoverable error is encountered.

    Instruction Fetch and Execute

    • The program counter (PC) holds the address of the next instruction to be fetched.
    • Fetched instructions are placed in the instruction register (IR).
    • The processor interprets and executes instructions contained within the instruction register.

    Execute Cycle

    • Processor-memory operations may transfer data between processor and memory.
    • Processor-I/O operations may transfer data to/from peripheral devices.
    • Operations within the processor might involve arithmetic or logic computations.
    • Instructions can control the sequence of program execution (e.g., jumps).

    Characteristics of a Hypothetical Machine

    • Opcode: Specifies the instruction operation.
    • Address: Holds location of data or instruction.
    • Internal CPU registers include the program counter (PC), instruction register (IR), and accumulator (AC).
    • Specific examples of instruction formats and internal CPU registers are included.

    Example of Program Execution

    • This part demonstrates a program executing, showing how instructions are fetched and executed, with effects on registers and memory.

    Interrupts

    • External modules use interrupts to notify the processor of events.
    • Interrupt types include program, timer, I/O, and hardware failures.
    • Interrupts allow the processor to handle events in a non-blocking fashion—meaning, the processor can switch between handling interrupts and other tasks.

    Sequential and Nested Interrupt Processing

    • Sequential interrupt processing handles interrupts one at a time.
    • Nested interrupt processing allows higher priority interrupts to cause lower ones to wait for later processing.

    Interconnection Structures

    • Computer components such as processors, memories, and peripherals connect using paths to communicate.
    • Various interconnection structures, like buses and point-to-point connections, exist for communication and data exchange between modules.
    • The design of these structures depends on required data exchanges.

    Bus Interconnection

    • A bus is a shared communication pathway connecting multiple devices.
    • A bus's key characteristic is its shared transmission medium.
    • Different signals (control, data, and address) are transmitted on different lines.
    • One device can successfully transmit at any given time, but there must be arbitration to control simultaneous access, otherwise data can get garbled.

    Point-to-Point Interconnect

    • This architecture replaces the shared bus approach in modern systems to improve system performance while addressing limitations of wider synchronous buses at higher data transfer rates using point-to-point connections.
    • Interconnects such as QuickPath Interconnect (QPI) and PCI Express (PCIe) are based on point-to-point architecture and have a better performance than bus-based architectures.

    PCI Express (PCIe)

    • A popular high-bandwidth and processor-independent interconnect alternative to bus specifications like PCI.
    • It excels for high-performance I/O subsystems.
    • PCIe implements a point-to-point architecture with layered protocols and packet transfers.

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    Test your knowledge on computer architecture fundamentals with this quiz. Explore topics like registers, instruction execution cycles, and memory operations. Perfect for students of computer science or those interested in understanding how computers function.

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