8086 Microprocessor: Instruction Execution & Clock Cycles

Processors and Assembly Language

• The System Clock signal is continuous and drives the operation of the CPU.
• Instruction execution is synchronized to the system clock.
• An instruction requires a number of clock cycles to complete, which differs depending on the complexity of the instruction and addressing mode.

Time States (T-States)

• The number of clock cycles needed to execute an instruction is called Time States (T-States).
• The processor does different things during the different T-States of the instruction.
• The first clock cycle of the execution of any instruction is known as T1, which is the fetch phase.
• Then, T2 is the decode phase, T3, and so on until the instruction completes.
• The first cycle of the next instruction goes back to being T1.

Bus Cycle and Time States

• A Bus Cycle is the basic operation that the processor performs to communicate with external devices.
• There are four types of bus cycles:
  • Memory Read
  • Memory Write
  • Input from external device (I/O Read)
  • Output to external device (I/O Write)

I/O Instructions

• There are two types of I/O instructions:
  • Direct I/O: The port number is provided in the instruction (8-bit port number, 00H – FFH, 256 ports).
  • Variable I/O: Uses a 16-bit port number that resides in DX (64KByte I/O address space, up to 65536 byte-sized ports).

Bus Cycle Timing

• Each bus cycle is 4 clock cycles (4 T-States).
• If the CPU is operating at 8 MHz, then each clock cycle is 125 ns long.
• Length of a normal bus cycle is 4 × 125 ns = 500 ns.
• External devices connected to the microprocessor have 1 clock cycle to decode and locate the location, and then produce the data and maintain it on the data bus for 2 clock cycles.

I/O Data Types

• I/O data transfer in the 8088/8086 MPU can be byte-wide or word-wide.
• I/O port numbers are 16-bits in length.
• Data is transferred using AD0 … AD7 if a byte is transferred, then one clock cycle is needed.
• If a word is transferred, then two clock cycles are needed.

Idle and Wait States

• Idle state: No bus cycles required, the bus remains idle.
• Wait state: States inserted between T3 & T4 of the current bus cycle, used to wait for very slow devices.