Computer Architecture Fundamentals

Advanced Computer Architecture

• Topics covered include instruction set architecture, computer arithmetic, pipelining, memory hierarchies, input/output, and multiprocessors.

Michael Gerndt

• Michael Gerndt has a Diploma and a Ph.D. in Computer Science from Bonn.
• He conducted postdoctoral research in Vienna from 1990 to 1991.
• He worked as Researcher at Forschungszentrum Jülich from 1992 to 2000.
• He has been a Professor for Parallel Computer Architecture at TUM since 2000.
• Previous research topics include Automatic Parallelization for Distributed Memory Systems, High Performance Fortran, Shared Virtual Memory, and Automatic Performance Analysis and Tuning for HPC Systems.
• Current Research interests include Cloud Computing, the Internet of Things, Embedded processors, and Serverless IoT Frameworks.

Chair for Computer Architecture and Parallel Systems (CAPS)

• The chair is 110 in I10.
• Personnel include include Prof. Dr. Martin Schulz, Prof. Dr. Michael Gerndt, Prof. Carsten Trinitis.
• Course Offerings include Einführung in die Rechnerarchitektur, Parallel Programming for Computational Science and Engineering, and courses on programming, computer architecture, and cloud computing.
• Additional teaching includes Advanced Computer Architecture, Cloud Computing, Efficient Programming of Multicore Processors and Supercomputers, IoT Sensor Node, Seminar on Cloud Computing, Seminar Existenzgründung.

Lecture Organization

• Lecture Time: Tuesdays 12:30 - 14:00 in HS2 and Fridays 12:15 - 13:45 in HS2
• The course has 6 ECTS and 4 SWS.
• Resources:
  • Script provided as PDF and updated during lecture
  • Lectures will be recorded
  • All materials available in Moodle
• Student Presentations:
  • Topics are offered in Moodle and students can suggest their own.
  • Presentations are 10-15 minutes
  • At most one presentation is allowed per lecture
  • Gives bonus (0.3)
  • First presentation is next Friday, October 25th of that recording year

Lecture Organization: Course Quizzes and Examination

• Quizzes are given during the lecture covering content from the last session.
• They consist of multiple choice questions.
• The goal is to encourage lecture attendance and content review.
• 60% of points are needed to pass the quiz.
• Each quiz will have a similar number of possible points.
• Quiz points can be combined with exam bonus points, and quizzes start Tuesday, Oktober 29th of recorded year
• Exam format:
• ninety minutes in duration
• multiple choice and free text answers
• Moodle based, with on-site screen recording Repetition exams are planned at the end of the summer semester Bonus points (Boni) do not apply to repetition exams.

Goals of the Lecture

• Know the architecture of processors including IT systems.
• Students should be able to assess different designs.
• Understand the interaction of architecture, compiler, technology and its applications.
• Know classes of parallel architectures and their implementation concepts.
• Start research work in related areas.
• Judge, categorize, and rank new information.

Application of the Knowledge

• A cornerstone for other teachings is the lecture.
• Operating Systems, distributed systems, computer graphics, microprocessors, parallel programming, cloud computing, IoT are some of the follow on lectures that can be applied.
• Direct application in industries for hardware, OS, and compiler developers
• Applies to developers and programmers of embedded systems
• Knowledge applicable in selection of computer systems and areas where program efficiency is important, such as real-time systems, servers, games/graphics, and IoT.

Computer Architecture

• Computer architecture combines hardware components to create computers tailored to functionality, performance, and cost goals. Modeling systems completes the process.
• Three main subcategories of computer architecture include:
  • Instruction Set Architecture (ISA): It is machine language composed of instruction sets, word size, memory addresses, and data formats.
  • Microarchitecture: A processor implements ISA that may have different binary compatibility implementations.
  • System architecture: Assembling hardware components implement an entire computer system.

Course Content

• Introduction
• Cross-cutting aspects
• Instruction set architecture
• Instruction pipelining
• Caches
• Memory technologies
• VLIW processors
• Data parallel architectures
• Shared memory systems
• Distributed memory systems

Learning Recommendations

• Review lecture material and identify key terms.
• Research unexplored questions using resources like chatGPT and Wikipedia.
• Connect recurring concepts from the lectures together to reinforce understanding.
• Focus on learning terms and concepts, and recommend flash cards as a useful tool.
• Apple users may use Marginnote 4.

Edge-Cloud Continuum

• This model includes cloud, edge, and device layers with the cloud layer consisting predominantly of data centers.
• An identified privacy barrier separates the cloud and edge layers.
• The edge layer is structured around edge server clusters, while the device layer comprises various smart devices.

Serverless IoT Framework

• It organizes cloud, edge, and device layers, emphasizing triggers, functions and data storage.
• A privacy barrier separates the cloud and edge layers.
• All layers require data, triggers and function to work.

Trends in Senior Homecare Costs

• Senior homecare has increased through the years in Germany
• Private nurse costs about 2000 Euros

Intel Knights Landing: A Deeper Look

• Architecture: MIC is designed to accelerate parallel throughput workloads, using data parallelism
• Features: Massive thread parallelism, massive data parallelism, high memory bandwidth
• ISAs: compatible with x86 ISA Architecture
• Second-generation and June 2016 release Knights Landing operates as standard processor/co-processor
• Rated at ~3 TFLOPS (DP)
• Structure : Grid of 54 physical blocks using a 2D mesh interconnect method
• Configuration: 38 tiles, each featuring 2 Cores, 1MB shared L2 cache, VPUs, and a CHA
• Activity: up to 36 active tiles
• Memory: Includes 8 MCDRAM controllers and 2 DDR4 memory controllers
• Management: includes PCIe, DMI and I/O controllers, plus power management functions

Intel Sapphire Rapids CPU

• Sapphire Rapids CPUs are Golden Cove core architecture

• Sapphier Rapids are used in Aurora (Argonne) and SuperMUC-NG Phase 2

• Released: Launched in January 2023

• Selling Point: Marketed as Intel® Xeon® CPU Max Series Processor Options:

• Xeon CPU Max 9462: offers 32 cores, with a 3.50 GHz max turbo frequency, 2.70 GHz base frequency, 75 MB cache, and 350 W TDP

• Xeon CPU Max 9480: features 56 cores, a 3.50 GHz max turbo frequency, 1.90 GHz base frequency, 112.5 MB cache, and 350 W TDP

• Xeon CPU Max 9470: contains 52 cores, a 3.50 GHz max turbo frequency, 2.00 GHz base frequency, 105 MB cache, and 350 W TDP

• Xeon CPU Max 9460: includes 40 cores, a 3.50 GHz max turbo frequency, 2.20 GHz base frequency, 97.5 MB cache, and 350 W TDP

• Xeon CPU Max 9468: provides 48 cores, a 3.50 GHz max turbo frequency, 2.10 GHz base frequency, 105 MB cache, and 350 W TDP

Sapphire Rapids Layout

• A quasi-monolithic 2x2 configuration organizes left/right dies.
• Interconnection: Utilizes EMIB (Embedded Multi-die Interconnect Bridge) for effective multi-die communication.

Intel Sapphire Rapids Al and Data Analytics Capabilities

• The coprocessor offers support for operations like TMUL, using Tile Registers.
• IAA accelerates compression/decompression and search in in-memory databases.
• DSA is for data copying/scattering; and QuickAssist Technology accelerates encryption for network communication

Lecture Materials and Suggested Study Method

• Consult books by Patterson & Hennessy, Tanenbaum, Culler, and Gonzalez for the computer architecture course
• Also supplement with web resources like Wikipedia and ChatGPT.

Computer System as Multilevel Machine

• Programs are translated with compilers and assemblers, which reduces the gap from high-level languages to the machine's digital logic.
• Multilevel machines have been automated over time to help improve reliability.
• In the modern world, the operator's job was automated by the invention of the operating system
• time sharing has become developed at MIT, and it has been the norm since roughly the 1960s

Computer Generations

• 1945: Zeroth Generation - Mechanical Computers
• 1955: First Generation - Vacuum Tubes
• 1965: Second Generation - Transistors
• 1980: Third Generation – Integrated Circuits
• Fourth Generation - ...: Very Large Scale Integration
• Fifth Generation: Ubiquitous computing

Zeroth Generation: Key Contributors

• Wilhelm Schickard 1620 developed the original, a machine designed for addition and subtraction but was never finished.
• Blaise Pascal built the Pascaline in 1642 to aid his father in tax collection.
• Gottfried Leibniz 1670 developed the binary number system and a calculating machine capable of multiplication and division.
• Charles Babbage (1792-1871) designed the first automated calculation engine for polynomials in 1822.
• Hollerith created a punchcard-based calculator that was sold for the 1890 U.S. census.
• Konrad Zuse (late 1930) created the Z1, mechanical engine, binary system, floating point arithmetic on punched tape.
• Howard Aiken (1944) built the relay-based Mark 1, and his work was based on Babbage’s

First Generation Advances and Leading Figures

• British intelligence (1944) builds the Colossus to decode German messages with Turing developing mathematical principles
• John Mauchley and Presper Eckert (1946) developed the ENIAC with 1.5K relays run manually and granted by the army.
• John von Neumann designed the von Neumann Architecture (1945).
• Maurice Wilkes (1946) built EDSAC using binary arithmetic in the UK.

Second and Third Computer Generations

• Transistor was invented at Bell Labs in 1948.
• DEC created the PDP1, first mini-computer was built by DEC (1961)
• CDC introduced CDC 6600 (designer was Seymour Cray) which had multiple functional units in parallel
• Integrated circuits were co-invented by Jack Kilby and Robert Noyce in 1958
• IBM build the System/360 (1964) that was the first machine with multiprogramming.
• DEC developed the PDP-11 and Xerox desgined the Alto I

Fourth and Fifth Computer Generations

• Personal computer started due to price drop in fourth generation • Apple, Commodore, Atari where some of the major companies • IBM PC in 1981 based on Intel CPU
• Then in the 1980s the appled Macintosh was introduced with a graphical user interface
• In the 1990s there was as an increase born and DEC produced the first 64-bit RISC processor.
• Fifth generation (1993 created Apple Newton in 1993 the Apple Newton was the first PDA

Computer Milestones

Understanding Von-Neumann Architecture

Consists of 4 Units

• Computers contain four main sections such as memory, control unit, arithmetic unit, and I/O Aspects include:
• Architecture structure is problem-independent:
  • The structure is independent of the problem (programmable).
  • Program and data are in the same memory. Memory is structured into fixed-length cells.: -There can be conditional jumps and -Machines are based on Binary presentation
• Original article by John von Neumann: : First draft of a report on the EDVAC, June 30th 1945
• Von-Neumann-Computer predecessors existed in mechanical computers, that have program control
• Historical Predecessors go as far back as Suan Pan and Abakus.

Historical Resources for Computer Design

• Deutsches Museum
• Computer History Museum in Palo Alto Silicon Valley.
• Alto I Computer System, Xerox (PARC), US, 1973.
• Additional collections of computer materials may also be found across several computer museums in Germany.

Process Technology and Moore's Law

• Moore’s Law: transistor density doubles every 18 months, or 12-24 mo in some versions 10 nm refers to transistor size by measuring channels on three sides of a vertical "fin" through "finFET and FinFET" technology
• Multigate transistor reduce leakage.
• Current developments include Samsung (MBCFET) and TSMC (FinFET) introducing 5nm processing, and IBM announcing 2 nm

Intel Tech

Intel's accelerators

• AMX supports 2D dense matrice operations and specialized registers call Tile Registers.
• IAA accelerates comp/decomp and lookup for databases within memory
• DSA is data copying and gathering via scatter in memory
• QAT accelerates comp/decomp and is also encryption for network communication

Future of Processor Technologies

• New tech such as sapphire are trending.
• Multi-chip designs can be integrated into architecture via silicon, and 3D packaging has potential Also use multilayer silicate on substrate. Semiconductors are currently being produced by many big countries to increase global accessibility

Cross Cutting Aspects: Performance

• Performance: "How" well the computer is working, not "What" the computer can do
• Aspects of performance includes: Speed, precision, memory, storage, graphics, communication, reliability, availability and more
• The "use cases" are: evaluation, optimisation, and creating individual components

Performance Metrics: Speed

• "Wall-clock time"/response time/elapsed time: a measure of how long a task takes • CPU time: the amount of "active" CPU time, or "System" time
  • User time: CPU is executing the program
  • System time: CPU is executing OS services
• Performance is a measure of process. formula Performance=1/execution time
• Cycle: Single cycle of the hardware clock
• Clock: period or clock cycle time: Length of clock cycle Formula to determine: clockrate = number of cycles per second exec time = #cycles x clock period = #cycles / clock rate

CPI, Instruction Classes and Influences on Metrics

• CPI: Cycle per instruction classes for certain instruction classes -E.g. Multiplication might have 2 cycles while addition might have 1 cycleCompiler Compiler optimisations might switch to faster instructions

Basic Performance: exec time = #instructions x CPI / clock rate The Algorithm determines the number of source executed and processed: The programming language is determined by the language affecting the instruction court; a Java program is slower/more "indirect" Compile is the effiencency of the affect both the count and CPI. Instruction Set Architecture that affects three all components, cycle cost, and the clock

Dynamic and Static Energy

• Dynamic: determined by the energy of requirements Devices can be optimized via battery life time. CMOS: is an energy used to switch a transistor Energy = capacitive load × voltage² Capacitive load depends on of capacitance the transistors Power = capacitive load x² x frequency switched The power did not increase because voltage could be reduced for each new technology

• Static: Occurs even if transistors do not switch Power static = currents static x voltage Voltage causes leakage.

Counter measures

• lower clock rates
• reduce power

Parallelism

• Parallelism: use multiple processors to speed computation
• The tasks must relate to the input and output given, as well as a given, concurrent tasks

How:

• Bit-level arithmetic
• Instruction pipelining
• RAID systems More than just that, multicore processors such as Xeon and intel are a standard parallelism

Metrics: For speed, a standard formula is speed up p processors / performance 1 processor

efficiency p processors = speed upp processors/ P

Performance = throughput = transactions : minute

Hardware Parallelism and Software costs

• The cost of using Parallelism is very low considering all the power that is being outputted, the main question becomes the number of bits in that single task

Memory Hierarchy

• Due to economic and technological, a highery of memories is used. A diagram is shown from ~1kb to ~1pb with a line of resister to achive. Reasons on why the structure operates efficiently is that the programs exhibit temperal and spalital locality. Meaning the address will be reutlizied.

Fault and Error

• Fault: the defect of a system
• Error: illegal state of the system
• Failure: occurs when an error reaches its "service" output

Categories Physicals for malfunction to hardware , transient Designs: from hardware and illegal conditions Interaction: when from the enviroment

"Fault tolerant system." is where it never results as a fully failed state

• Fail-controlled system uses recovery though protocals

Fault precention: methods prevent into systems like firewall or coding methods Falut removals to remove faults during the designs though "validation and vertification" and the process of Debugging

• Reliablly: system is free for the time
• Safety

Tech Used to Achieve Fault Tolerance

• MultiPath, a system of memory controller,
• Memory Raid are several steps that help prevent the occurence of errors.

Virtualization of IT

• Virtualization means the creation of a virtual

• This can include a "computer" or a storage device"

• This is implemented using a hypervisor, this organises the vitural machhien

• The two main versions:

  -Level of: - Bare Metal (hardware) - Hosted (virtualbox or parallels) - OS Level (container based)

Computer Operation Modes

• Virtualisation technique support mode of CPU as VM of harware and hypervisor mode.

Virtualisation Types

• full and para; in conjunction to the support for hardware
• Examples Open Source virtualisation tool, Xen is a main example

Processors Classes

• General Purpose Processors found in desktops and more
• Network Processors are designed for packet processing with ASICS/FPGAs. Examples of this is as intel Lofino

Data and Processors

• Embedded.processors for auto like ESPN32 that requires less power Altera circuit is able perform multiple at different parts
• Signonal.procesing

###Classes of Paralle Architures

Processors are the main work load, which operate by following the instruction set known as ISA. The important information is how we interact with data and it's

ISA operands.

DatatTypes and Formats Operand: # OF Data data instructions like instruction and registers. Data Alignments are also an aspect. Addressing

• Immediate: data is part of the instruction
• Register: register is part of the instruction
• Directly , Register Indirect etc.

ISA Main Points

• Instrucions, where there is data transfer, artimitcally.
• The structure is structived in opcode and operands which are from von Neumann structure.
• Registe, where we implement terms for use.
• Execustion mode of where memory is being used. -In early days memory for people where only the computers were available. .

Instruction Process and Performance

• Clock cycle: Single cycle of the hardware clock
• The clock can affect the CPU architecture like that the first transistor, then comes the current Intel core and systems.

Basic Performance Metric Influences

-The algorithm to use -The progam - compiler

Instruction: Instruction: (CPI) -Clock

Power Wall Static and Dynaimc

• Dynamic: Processors deteme the colling needs. Which means the use of battery efficenity
• Static: the the energy used to switch it The reduction can be to voltage

Compiler Tech

• Lower clock rates

• Dynamic Voltage and Frequency Scaling (DVFS)

• Pprocessors should be able to switch if it is according to the program

• cores must be have a lower clock

• clock gating

• power gating

• dark silicon

Connecting a System Components Together

There is a way to speed up the data between, by using less "cost" The first of this was known was know as the "super computer" and its use in the 1980s, but is now is known simply as Parrellisum

Parrellisum

• The aim of the computer, by using multiple processors, is to speed up the whole process What helps with : Set: of task and depends on the relation to inputs and outputs

• The idea of concurrence is by the use of 2 task that do not relate

• Perralell tasks , in which both tasks occur in some point of time speedup(p processors) = performance(p processors) / performance(1 processor)

Main Metrics

performance(p processors) / performance(1 processor)

efficiency p processors = speed upp processors/ P

Performance = throughput = transactions : minute

Knowledge

• What is applied in the context where the effincently applies
• A better is perralliserm

Memory hierarchy

• Memory has limitation, therefor the highesty of memores must be utilzed.

Memory

• 1KB to 1PB
• The time for it is also important such ~1n, ~10ns and so on

Computer Architecture

• Programs exhibit temporal and spatial locations, this works since it is efficient
• E.g. the Archive which can be called System The memory is as sound data within of each process.

Course Schedule Updates

• Lecture is pushed towards later and 305m will continue

Explore computer architecture: subcategories, historical milestones like the introduction of integrated circuits and the Z1 mechanical engine. Learn about Moore's Law, Instruction Decode, data alignment, and hypervisors. Discover key features of the IBM System/360.