Computer Architecture: Bus and Memory

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Questions and Answers

What is the primary function of the Memory Address Register (MAR)?

Holds the address of the memory location to be accessed.

What is the purpose of a tri-state buffer in a multi-point bus?

To allow components to drive the bus or enter a high-impedance state, enabling multiple components to share the same bus.

What is the role of the Control Unit in a processor?

Coordinates and manages all CPU operations, generates control signals, interprets instructions, and directs actions.

What is stored in the Memory Buffer Register (MBR) or Memory Data Register (MDR)?

Data to be written to or read from the selected memory location. Signup and view all the answers

What is the fetch-decode-execute cycle in a processor?

The process by which the processor fetches, decodes, and executes instructions stored in main memory. Signup and view all the answers

What is the purpose of a memory bank in a computer system?

An array of registers organized as memory, where each register has a unique address. Signup and view all the answers

What is the primary function of the Program Counter (PC) register in a CPU?

Contains the memory address of the next instruction to be executed. Signup and view all the answers

What is the purpose of the Memory Address Register (MAR) in a CPU?

Holds the memory address of data or instruction to be accessed. Signup and view all the answers

What type of bus is responsible for transferring data between the CPU and memory or I/O devices?

Data Bus Signup and view all the answers

What is the role of the Condition Code Register (CCR) in a CPU?

Contains status flags indicating the result of the last operation (zero, negative, overflow). Signup and view all the answers

What is the primary function of the Stack Pointer (SP) register in a CPU?

Points to the top of the stack, used for temporary storage and function call management. Signup and view all the answers

What determines the speed of a CPU's operation?

Clock frequency Signup and view all the answers

What is the primary goal of the routing algorithm in a network?

To minimize the overall delay experienced by packets traversing the network and maximize the total amount of data that can be transferred across the network in a given time. Signup and view all the answers

What are the four types of delays that can occur in a network?

Propagation delay, transmission delay, processing delay, and queuing delay. Signup and view all the answers

What is the primary difference between static and dynamic routing?

Static routing uses fixed, manually configured routing tables, while dynamic routing uses automatically updated routing tables based on information exchanged between routers. Signup and view all the answers

What is the main function of a repeater in a network?

To extend the range of a physical medium by regenerating and forwarding signals. Signup and view all the answers

How do switches make forwarding decisions?

Switches use MAC addresses to make forwarding decisions and maintain a MAC address table to map addresses to ports. Signup and view all the answers

What is the primary responsibility of the transport layer?

To manage end-to-end delivery between communicating software processes. Signup and view all the answers

What is the purpose of sequence numbers in the transport layer?

To ensure that packets are reassembled in the correct order at the destination. Signup and view all the answers

What is the main difference between TCP and UDP?

TCP provides a connection-oriented, reliable, and error-checked service, while UDP provides a connectionless service with limited error control. Signup and view all the answers

What is the purpose of port numbers in the transport layer?

To direct incoming data to the appropriate application on a single computer. Signup and view all the answers

What is the function of the checksum in UDP and TCP headers?

To provide basic error detection by calculating a checksum over the header and data. Signup and view all the answers

Study Notes

Communication Channels and Buffers

Multi-Point Bus: Shared communication channel connecting multiple components; utilizes tri-state buffers.
Tri-State Buffers: Allow control over bus access by enabling components to drive the bus or enter a high-impedance state.

Computer Memory Components

Memory Bank: Array of registers organized with unique addresses.
Memory Address Register (MAR): Stores the address of memory for access.
Memory Buffer Register (MBR/MDR): Holds data to be read from or written to memory.
Read Operation: Transfers selected data into the MBR/MDR.
Write Operation: Sends data from the MBR/MDR to the specified memory location.

Central Processing Unit (CPU) Overview

CPU: The primary component executing instructions and performing calculations.
Fetch-Decode-Execute Cycle: Process involving fetching, decoding, and executing instructions from main memory.
Control Unit: Manages CPU operations, generates control signals, and interprets instructions.
Arithmetic Logic Unit (ALU): Handles arithmetic and logical operations (e.g., addition, subtraction).
Registers: Fast storage within CPU, including:
- Accumulator (ACC): Holds results of ALU operations.
- Program Counter (PC): Points to the next instruction address.
- Instruction Register (IR): Contains current instruction being executed.
- Memory Address Register (MAR) and Memory Buffer Register (MBR): Support data access.
- Condition Code Register (CCR): Indicates operation results’ status flags.
- Stack Pointer (SP): Manages temporary storage for function calls.

Bus Systems in CPU

Data Bus: Transfers data between CPU, memory, and I/O devices.
Address Bus: Carries memory addresses from CPU to other components.
Control Bus: Delivers control signals for operations.

Timing and Signal Propagation

Clock: Generates timing signals for CPU synchronization.
Propagation and Transmission Delays: Times related to signal travel and data processing.
Desirable Routing Attributes: Correctness, robustness, fairness, simplicity, minimizing delay, and maximizing throughput.

Routing Approaches

Static Routing: Manually configured by network administrators.
Random Routing: Packets forwarded randomly to neighbors.
Broadcast Routing: Sends packets to all network nodes.
Dynamic Routing: Automatically updated routing tables based on information exchanged.

Network Devices Functionality

Repeaters: Extend signal range, operate at the physical layer without processing data.
Switches: Interconnect LAN segments, enhance efficiency and direct frames based on MAC addresses.
Routers: Connect different LANs or to the Internet, determine best message paths, handle IP addressing and routing tables, and support advanced functions like NAT and QoS.

Transport Layer Responsibilities

Manages end-to-end delivery between software processes.
Segmentation: Breaks messages into packets and reassembles them at the destination.
Service-point Addressing: Directs messages to correct applications and ensures reliable transfers.

Error and Sequence Control

Transport Layer Error Control: Augments data link layer checking by managing errors across networks with techniques like checksums.
Sequence Control: Maintains integrity of data packets with sequence numbers for accurate reassembly.

Duplicate Packet Control

Sequence numbers help identify and manage duplicate packets, ensuring each is processed once.

Port Addressing

Unique port numbers (0-65535) assigned to applications for incoming data accuracy.
Common port assignments include:
- Port 20: FTP (data)
- Port 21: FTP (control)
- Port 80: HTTP (web)
- Port 443: HTTPS (secure web)

Protocols (UDP and TCP)

User Datagram Protocol (UDP): Connectionless protocol focusing on speed over reliability, suitable for real-time applications.
Transmission Control Protocol (TCP): Connection-oriented, ensures reliable delivery with flow control and congestion management, employing mechanisms like sequence numbers and acknowledgments for ordered delivery.

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Description

Learn about Multi-Point (Multi-Drop) Bus, Tri-State Buffers, Computer Memory, Memory Bank, and Memory Address Register (MAR) in computer architecture.