Computer Architecture Basics

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Questions and Answers

What does the Address Decoder do in a computer system?

It acts as a permanent storage for frequently accessed data.

It interfaces directly with the CPU to execute instructions.

It stores data temporarily before transfer.

It converts the address and points to the decoded address. (correct)

How does the CPU interact with the Memory Data Register (MDR) during data transfer?

The CPU transfers data directly without the MDR.

The CPU uses a continuous connection to send data.

The CPU activates the switch connecting the MDR with the register momentarily. (correct)

The CPU monitors the status of the MDR without engaging it.

What is the purpose of the bus in a computer system?

To generate electrical signals for processing tasks.

To allow data transfer between locations in the system. (correct)

To connect peripherals directly to the CPU.

To permanently store data for long-term access.

What is the decimal equivalent of the binary number 0011 0001?

49 Signup and view all the answers

Which switch configuration allows the MDR to receive data from an input cell?

WRITE switch Signup and view all the answers

Why is programmed I/O not suitable for faster devices?

It is best for slow devices and individual word transfers. Signup and view all the answers

What is necessary for handling I/O devices with different control requirements?

A simplified approach within CPU programs. Signup and view all the answers

How can high-speed I/O devices be efficiently connected with the computer?

Through buses capable of high data transfer rates. Signup and view all the answers

What is a key requirement for I/O systems handling multiple devices?

Guaranteed steady performance regardless of conditions. Signup and view all the answers

What describes the impact of device incompatibilities in speed on systems?

They complicate synchronization, especially when multiple devices are used. Signup and view all the answers

What facilitates block transfers between I/O and memory without CPU involvement?

Direct memory access methods. Signup and view all the answers

What type of control do disk drives require for effective operation?

Electromechanical control that is demanding on CPU resources. Signup and view all the answers

What must peripheral devices be able to do to alert the CPU effectively?

Initiate communication in response to unexpected inputs. Signup and view all the answers

Which category of lines is responsible for carrying the actual data being transferred?

Data Signup and view all the answers

What type of bus transfers data one bit at a time using a single data line pair?

Serial bus Signup and view all the answers

Which of the following describes a half-duplex line?

Data can only flow in one direction at a time. Signup and view all the answers

What function do control lines provide within a bus system?

They provide timing signals for synchronization. Signup and view all the answers

A point-to-point bus is characterized by which of the following?

Transferring data to a single specific destination. Signup and view all the answers

What is the purpose of power lines in an integrated circuit?

To provide electrical charge for modules. Signup and view all the answers

Which type of bus is also known as a broadcast bus?

Multipoint bus Signup and view all the answers

What is NOT a requirement for handling I/O within a bus system?

All devices must communicate on the same frequency. Signup and view all the answers

What is the primary function of interrupt lines in a computer system?

To notify the CPU of events needing immediate attention Signup and view all the answers

Which statement accurately describes Direct Memory Access (DMA)?

DMA allows for blocks of data to be transferred without CPU intervention Signup and view all the answers

What information is saved when a program is suspended due to an interrupt?

The location of the last instruction executed and values in various registers Signup and view all the answers

In a standard I/O configuration, how many interrupt lines may a modern PC support?

32 Signup and view all the answers

What must be true for an I/O controller to facilitate DMA operations?

It should be able to simulate the CPU interface with memory Signup and view all the answers

Which of the following is NOT a condition for DMA to take place?

The CPU must be free of instruction execution Signup and view all the answers

What is indicated by an external event notifier?

A keyboard has been struck Signup and view all the answers

Which aspect does a completion signal address in a computer system?

Acknowledgment that a device has finished processing data Signup and view all the answers

What is required to avoid conflict between the CPU and the I/O controller during DMA?

Special control circuits must indicate control ownership of memory and bus. Signup and view all the answers

What function does the disk controller perform in relation to DMA?

It provides a buffer for data before transferring it to the disk. Signup and view all the answers

How does the presence of I/O controllers affect CPU workload?

It frees the CPU to perform other tasks during slower I/O operations. Signup and view all the answers

What role does the disk controller have when ignoring commands from the CPU?

It will continue operating as per previous instructions until reset. Signup and view all the answers

What kind of registers must the disk controller have for direct memory transfer?

Separate memory address and data registers from those of the CPU. Signup and view all the answers

Why are interrupt capabilities important for the disk controller?

To notify the CPU when transfers are complete or errors occur. Signup and view all the answers

Which of the following illustrates a function of I/O controllers?

Facilitating operations between the CPU and multiple different devices. Signup and view all the answers

What certification does a disk controller need to recognize data messages?

Hardware control validation for specific devices. Signup and view all the answers

Study Notes

Basic Computer Hardware Servicing (ITEC 102)

The course is about basic computer hardware servicing.
The Polytechnic University of the Philippines (PUP) offers this course.
PUP's vision is to be a leading comprehensive polytechnic university in Asia; its mission is to advance an inclusive, equitable, and globally relevant polytechnic education.
Strategic goals include teaching and learning, research and extension, and internal governance, focusing on innovation, faculty empowerment, student development, and resource management.
Core values include integrity, accountability, nationalism, sense of service, passion for learning, respect for human rights, innovation, inclusivity, and excellence.
The course material includes memory units, buses, I/O devices, programmed I/O, interrupts, and direct memory access.

Memory Unit

MAR has 0011 0001 in decimal, it is 49.
Address Decoder converts the address and points to the decoded address.
MDR then lets you access the data in the memory unit.
Read Switch connects to output cell to MDR.
Write Switch connects to input cell to MDR.
The CPU momentarily turns on the switch to connect the MDR with the register using the activation line, transferring data between memory and MDR.

Buses

Buses are the physical connections for transferring data between locations in a computer system.
Buses are a group of electrical or optical conductors that carry computer signals from one location to another.
Components of buses include wires, integrated circuit conductors, printed circuits, and special thin glass fibers.
Bus lines have names and carry a single electrical signal (one bit of a memory address, a sequence of data bits, or a timing control).
Four general categories of bus lines are data, addressing, control, and power.
Data lines carry the data being moved.
Addressing lines specify the recipient of data.
Control lines provide control and timing signals for synchronization.
Power lines provide electrical power.
Bus types include parallel (individual lines for each bit), serial (data transferred sequentially), simplex (unidirectional), half-duplex (data one direction at a time), and full-duplex (both directions simultaneously).
Buses can also be point-to-point (cables carrying signals from a specific source to a specific destination), ports (internal connectors for external cables), and multipoint (multidrop, connecting several points together), also known as broadcast buses.

I/O Devices

I/O devices need means for individually addressing devices and initiating communication with the CPU, handling unexpected inputs.
Programmed I/O is suitable for slow devices (and individual word transfers). Block transfers require a more efficient method.
Memory is suitable for block transfers, and the process should ideally be independent of CPU involvement for efficiency.
I/O buses must have the capability for high data transfer rates, handling devices at various speeds with varying delays.
Handling extreme control requirements for various devices needs a means to manage I/O operations in a simplified, similar way by programs within the CPU.
I/O devices need different formats, and incompatibilities in speed between devices and the CPU lead to synchronization challenges.
I/O devices and connections need to guarantee steady multimedia performance, but electromechanical control of devices ties up too much CPU time.
I/O controller acts as an interface between the CPU and the particular device.

Programmed I/O

Input from peripheral devices is transferred one word at a time from the I/O controller to the I/O data register and then to an accumulator or general-purpose register.
Individual output data words move from a register to the I/O data register, controlled by program instructions.
Each instruction produces a single input or output.

Interrupts

Interrupts are special control lines emitting signals from hardware/software when an event needs immediate attention.
The computer suspends the current program and jumps to a special interrupt processing program when an interrupt occurs on a line.
The pertinent information about the suspended program (location of the last instruction, register values) is saved in a special memory area (like a process control block (PCB)).
To service interrupts:
The program counter and CPU registers are saved in the stack during an interrupt.
The interrupt routine is run (to handle the interrupt).
Registers and the program counter are restored from the stack upon interrupt completion. This resumes the original process.
Uses of interrupts include notifying of external events, signaling completion, allocating CPU time (like time-sharing), and indicating abnormal events.

Direct Memory Access (DMA)

DMA bypasses the CPU for block data transfers, with the CPU providing initial setup (instructions, addresses, block sizes).
A DMA controller transfers data between peripheral devices and memory.
Upon completion, the DMA controller sends a completion interrupt to the CPU.
DMA requires method for connecting I/O and memory; some systems already connect them to the same bus, easing design.
The I/O controller needs to simulate CPU interactions during DMA.
DMA must avoid potential conflicts. Disk I/O controllers, for example, need to have separate memory registers and addresses from the CPU to avoid conflicts.

I/O Controllers

I/O controllers serve as interfaces between CPUs and devices (e.g., a disk drive) by accepting CPU commands and controlling devices.
Disk controllers recognize requests, establish disk operations, recognize when DMA is used. They offer buffering of data until ready for transfer.
The disk controller uses specific registers (memory address and data registers) separate from the CPU's registers to orchestrate I/O operations.
Functions of the disk controller include controlling the disk drive (moving the head), buffering data, and using interrupts to signal transfer completion or errors.
Controllers allow I/O devices to run simultaneously, freeing the CPU to perform other tasks.

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Description

This quiz covers fundamental concepts in computer architecture, including the role of the address decoder, CPU interactions with the Memory Data Register, and the function of buses within a system. Test your understanding of binary to decimal conversions and switch configurations related to data transfer.