Computer Architecture Basics

Basic Computer Hardware Servicing (ITEC 102)

• The course is about basic computer hardware servicing.
• The Polytechnic University of the Philippines (PUP) offers this course.
• PUP's vision is to be a leading comprehensive polytechnic university in Asia; its mission is to advance an inclusive, equitable, and globally relevant polytechnic education.
• Strategic goals include teaching and learning, research and extension, and internal governance, focusing on innovation, faculty empowerment, student development, and resource management.
• Core values include integrity, accountability, nationalism, sense of service, passion for learning, respect for human rights, innovation, inclusivity, and excellence.
• The course material includes memory units, buses, I/O devices, programmed I/O, interrupts, and direct memory access.

Memory Unit

• MAR has 0011 0001 in decimal, it is 49.
• Address Decoder converts the address and points to the decoded address.
• MDR then lets you access the data in the memory unit.
• Read Switch connects to output cell to MDR.
• Write Switch connects to input cell to MDR.
• The CPU momentarily turns on the switch to connect the MDR with the register using the activation line, transferring data between memory and MDR.

Buses

• Buses are the physical connections for transferring data between locations in a computer system.
• Buses are a group of electrical or optical conductors that carry computer signals from one location to another.
• Components of buses include wires, integrated circuit conductors, printed circuits, and special thin glass fibers.
• Bus lines have names and carry a single electrical signal (one bit of a memory address, a sequence of data bits, or a timing control).
• Four general categories of bus lines are data, addressing, control, and power.
• Data lines carry the data being moved.
• Addressing lines specify the recipient of data.
• Control lines provide control and timing signals for synchronization.
• Power lines provide electrical power.
• Bus types include parallel (individual lines for each bit), serial (data transferred sequentially), simplex (unidirectional), half-duplex (data one direction at a time), and full-duplex (both directions simultaneously).
• Buses can also be point-to-point (cables carrying signals from a specific source to a specific destination), ports (internal connectors for external cables), and multipoint (multidrop, connecting several points together), also known as broadcast buses.

I/O Devices

• I/O devices need means for individually addressing devices and initiating communication with the CPU, handling unexpected inputs.
• Programmed I/O is suitable for slow devices (and individual word transfers). Block transfers require a more efficient method.
• Memory is suitable for block transfers, and the process should ideally be independent of CPU involvement for efficiency.
• I/O buses must have the capability for high data transfer rates, handling devices at various speeds with varying delays.
• Handling extreme control requirements for various devices needs a means to manage I/O operations in a simplified, similar way by programs within the CPU.
• I/O devices need different formats, and incompatibilities in speed between devices and the CPU lead to synchronization challenges.
• I/O devices and connections need to guarantee steady multimedia performance, but electromechanical control of devices ties up too much CPU time.
• I/O controller acts as an interface between the CPU and the particular device.

Programmed I/O

• Input from peripheral devices is transferred one word at a time from the I/O controller to the I/O data register and then to an accumulator or general-purpose register.
• Individual output data words move from a register to the I/O data register, controlled by program instructions.
• Each instruction produces a single input or output.

Interrupts

• Interrupts are special control lines emitting signals from hardware/software when an event needs immediate attention.
• The computer suspends the current program and jumps to a special interrupt processing program when an interrupt occurs on a line.
• The pertinent information about the suspended program (location of the last instruction, register values) is saved in a special memory area (like a process control block (PCB)).
• To service interrupts:
• The program counter and CPU registers are saved in the stack during an interrupt.
• The interrupt routine is run (to handle the interrupt).
• Registers and the program counter are restored from the stack upon interrupt completion. This resumes the original process.
• Uses of interrupts include notifying of external events, signaling completion, allocating CPU time (like time-sharing), and indicating abnormal events.

Direct Memory Access (DMA)

• DMA bypasses the CPU for block data transfers, with the CPU providing initial setup (instructions, addresses, block sizes).
• A DMA controller transfers data between peripheral devices and memory.
• Upon completion, the DMA controller sends a completion interrupt to the CPU.
• DMA requires method for connecting I/O and memory; some systems already connect them to the same bus, easing design.
• The I/O controller needs to simulate CPU interactions during DMA.
• DMA must avoid potential conflicts. Disk I/O controllers, for example, need to have separate memory registers and addresses from the CPU to avoid conflicts.

I/O Controllers

• I/O controllers serve as interfaces between CPUs and devices (e.g., a disk drive) by accepting CPU commands and controlling devices.
• Disk controllers recognize requests, establish disk operations, recognize when DMA is used. They offer buffering of data until ready for transfer.
• The disk controller uses specific registers (memory address and data registers) separate from the CPU's registers to orchestrate I/O operations.
• Functions of the disk controller include controlling the disk drive (moving the head), buffering data, and using interrupts to signal transfer completion or errors.
• Controllers allow I/O devices to run simultaneously, freeing the CPU to perform other tasks.

This quiz covers fundamental concepts in computer architecture, including the role of the address decoder, CPU interactions with the Memory Data Register, and the function of buses within a system. Test your understanding of binary to decimal conversions and switch configurations related to data transfer.