Computer Architecture 2: Registers and Memory

Course Information

• Course name: Computer Architecture 2
• Course instructor: Dr. Rouda Mahbani
• Department: Computer Engineering
• Year: 2nd year
• University: Al-Wataniya Private University
• Country: Syria

Registers and General Structure

• Introduction to memory operations
• Buses in computer architecture
• Registers are important components of the processor
• Types of registers:
  • Data registers
  • Address registers
  • Status/flag registers

Data Registers AX, BX, CX, DX

• General-purpose registers (AX, BX, CX, DX)
• Each register has a high and low byte (e.g., AX has AH and AL)
• AX (Accumulator): Primarily used for arithmetic and logical operations, input/output, and memory access; considered most efficient for programming
• BX (Base Register): Usually employed for indirect addressing; composed of BH and BL
• CX (Count Register): Commonly used for loops, shifts, and rotations; serves as a counter in array operations
• DX (Data Register): Commonly used for I/O operations and upper 16 bits in 32-bit multiplication/division operations

Segment Registers CS, DS, SS, ES

• 8086 architecture limits addressing to 64KB
• Memory is divided into segments (64KB each)
• Segment registers specify the start address of each segment in memory
• CS (Code Segment): Holds the address of the first instruction in the code segment
• DS (Data Segment): Contains the first address of the data segment
• SS (Stack Segment): Holds the address of the first address in the stack segment
• ES (Extra Segment): An extra data segment for added functionality

Index and Pointer Registers SI, DI, SP, BP

• Used with segment registers to access specific memory locations
• SI (Source Index): Contains the offset from the data segment (DS)
• DI (Destination Index): Used with the Extra segment (ES) register
• SP (Stack Pointer): Points to the top of the stack within the stack segment (SS); automatically adjusts when elements are pushed or popped onto the stack
• BP (Base Pointer): Holds offset from the stack segment (SS); used to access data in the stack without removing them from the stack.

Other Registers IP and Flags Register

• IP (Instruction Pointer): Contains the address of the next instruction to execute in the code segment (CS)
• Flags Register (Status/Control): A 16-bit register, although only 9 bits are commonly used; contains status and control flags.

Main Memory

• Essential for program and data storage during execution; temporary space
• Consists of binary cells, organized as an array
• Each row has a unique address
• Each cell uses the binary system to represent data
• Word Register: Temporary data register integrated with the control unit to control read/write operations
• Memory cells: Can be represented by magnetic cells or switches
• Address & Control lines are used to control memory read/write operations

Buses

• Communication channels between components
• Types of buses:
  • Address Bus: Carries addresses of memory locations
  • Data Bus: Transfers data between components; bidirectional
  • Control Bus: Transmits control signals (e.g., read/write); unidirectional

Control Signals (Control Bus)

• MEMR: Read from RAM/ROM
• MEMW: Write to RAM
• IOR: Read from I/O
• IOW: Write to I/O
• The control bus contains signals to indicate when a read or write operation should occur.

Instruction Cycle

• CPU performs operations in a cycle
• Consists of two phases:
  • Fetch: Retrieves next instruction from memory
  • Execute: Decodes and executes the instruction