Verilog Programs for Combinational Circuits PDF

Combinational Circuits 1: HALF ADDER Circuit Diagram Truth Table DATAFLOW MODEL: module ha(sum, carry, a, b); input a, b; output sum, carry; assign sum = a^b; assign carry = a&b; endmodule BEHAVIORAL MODEL: module ha(sum, carry, a, b); input a,b; output sum, carry; reg sum, carry;...

Combinational Circuits 1: HALF ADDER Circuit Diagram Truth Table DATAFLOW MODEL: module ha(sum, carry, a, b); input a, b; output sum, carry; assign sum = a^b; assign carry = a&b; endmodule BEHAVIORAL MODEL: module ha(sum, carry, a, b); input a,b; output sum, carry; reg sum, carry; always @(a,b) begin case({a,b}) 2'b00:{s,c}=00; 2'b01:{s,c}=10; 2'b10:{s,c}=10; 2'b11:{s,c}=01; endcase end endmodule STRUCTURAL MODEL: module ha (sum, carry, a, b); input a, b; output sum, carry; 1  xor A1(sum,a,b); and A2(carry,a,b); endmodule TEST BENCH for HALF ADDER: module ha_tb(); reg a, b; wire sum, carry; ha uut (sum,carry,a,b); initial begin {a,b} = 2’b00; #10 {a,b} = 2’b01; #10 {a,b} = 2’b10; #10 {a,b} = 2’b11; end endmodule 2: FULL ADDER Circuit Diagram Truth Table: DATAFLOW MODEL: module fa(sum,carry,a,b,cin); input a,b,cin; output sum,carry; assign sum=a^b^c; assign carry=(a&b)|(b&c)|(c&a); endmodule 2 BEHAVIORAL MODEL: module fa(sum,carry,a,b,cin); input a,b,cin; output sum,carry; reg sum,carry; always @(a,b,c) begin case ({a,b,c}) 3'b000:{sum,carry}=00; 3'b001:{sum,carry}=10; 3'b010:{sum,carry}=10; 3'b011:{sum,carry}=01; 3'b100:{sum,carry}=10; 3'b101:{sum,carry}=01; 3'b110:{sum,carry}=01; 3'b111:{sum,carry}=11; endcase end endmodule STRUCTURAL MODEL: module fa(a,b,c,sum,carry); input a,b,c; output sum,carry; wire n1,n2,n3; xor A1 (sum,a,b,cin); and A2 (n1,a,b); and A3 (n2,b,cin); and A4 (n3,a,cin); or A5 (carry, n1,n2,n3); endmodule TESTBENCH for FULL ADDER: module fa_tb(); reg a, b, cin; wire sum, carry; fa uut (sum,carry,a,b,cin); initial begin {a,b,cin} = 3’b000; #10 {a,b,cin} = 3’b001; #10 {a,b,cin} = 3’b010; #10 {a,b,cin} = 3’b011; #10 {a,b,cin} = 3’b100; #10 {a,b,cin} = 3’b101; #10 {a,b,cin} = 3’b110; 3 #10 {a,b,cin} = 3’b111; end endmodule 3: HALF SUBTRACTOR Circuit Diagram Truth Table DATAFLOW MODEL: module hs(d, bo, a, b); input a,b; output d,bo; assign d = a^b; assign bo = (~a) & b; endmodule BEHAVIORAL MODEL: module hs(d, bo, a, b); input a,b; output d, bo; reg d, bo; always @(a,b) case({a,b}) 2'b00:{d,bo}=00; 2'b01:{d,bo}=11; 2'b10:{d,bo}=10; 2'b11:{d,bo}=00; endcase endmodule STRUCTURAL MODEL: module hs(d, bo, a, b); input a,b; output d,bo; wire w1; 4  xor n1 (d,a,b); not n2 (w1,a); an n3 (bo,w1,b); endmodule TEST BENCH for HALF SUBTRACTOR module hs_tb(); reg a, b; wire sum, carry; hs uut (d, bo, a, b); initial begin {a,b} = 2’b00; #10 {a,b} = 2’b01; #10 {a,b} = 2’b10; #10 {a,b} = 2’b11; end endmodule 4: FULL SUBTRACTOR Circuit Diagram Truth Table DATAFLOW MODEL: module fs(d,bo,a,b,c); input a,b,c; output d,bo; 5  assign d = a^b^c; assign bo = ((~a)&b)|(b&c)|(c&(~a)); endmodule BEHAVIORAL MODEL: module fs(d,bo,a,b,c); input a,b,c; output d,bo; reg d,bo; always @(a,b,c) case ({a,b,c}) 3'b000:{d,bo}=00; 3'b001:{d,bo}=11; 3'b010:{d,bo}=11; 3'b011:{d,bo}=01; 3'b100:{d,bo}=10; 3'b101:{d,bo}=00; 3'b110:{d,bo}=00; 3'b111:{d,bo}=11; endcase endmodule STRUCTURAL MODEL: module fs(d,bo,a,b,c); input a,b,c; output d,bo; wire w1,w2,w3,w4; xor n1 (d,a,b,c); not n2 (w1,a); and n3 (w2,w1,b); and n4 (w3,b,c); and n5 (w4,w1,c); or n6 (bo, w2,w3,w4); endmodule TESTBENCH for FULL SUBTRACTOR: module FS_tb(); reg a, b, c; wire d, bo; fs uut (d,bo,a,b,c); initial begin {a,b,c} = 3’b000; #10 {a,b,c} = 3’b001; #10 {a,b,c} = 3’b010; #10 {a,b,c} = 3’b011; #10 {a,b,c} = 3’b100; #10 {a,b,c} = 3’b101; #10 {a,b,c} = 3’b110; 6 #10 {a,b,c} = 3’b111; end endmodule 5: FULL ADDER USING HALF ADDER Circuit Diagram module fa_ha(sum,carry,a,b,cin); input a,b,cin; output sum,carry; wire s1,c1,c2; ha h1 (s1,c1,a,b); ha h2 (sum,c2,s1,cin); or o1(carry,c1,c2); endmodule 6: FULL SUBTRACTOR USING HALF SUBTRACTOR Circuit Diagram module fs_hs(d,bo,a,b,c); input a,b,c; output d,bo; wire w1,w2,w3; hs_m h1 (d1,bo1,a,b); hs_m h2 (d,bo2,d1,c); or o1 (bo,bo1,bo2); endmodule 7 7: DECODER (3:8) Circuit Diagram Truth Table DATAFLOW MODEL: module dec38(y0,y1,y2,y3,y4,y5,y6,y7,a,b,c); input a,b,c; output y0,y1,y2,y3,y4,y5,y6,y7; assign y0 = (~a)&(~b)&(~c); assign y1 = (~a)&(~b)&c; assign y2 = (~a)&b&(~c); assign y3 = (~a)&b&c; assign y4 = a&(~b)&(~c); 8  assign y5 = a&(~b)&c; assign y6 = a&b&(~c); assign y7 = a&b&c; endmodule BEHAVIORAL MODEL: module dec38_b(y,a,b,c); input a,b,c; output [7:0]y; reg [7:0]y; always @(a,b,c) case ({a,b,c}) 3'b000: y = 8'h01; 3'b001: y = 8'h02; 3'b010: y = 8'h04; 3'b011: y = 8'h08; 3'b100: y = 8'h10; 3'b101: y = 8'h20; 3'b110: y = 8'h40; 3'b111: y = 8'h80; endcase endmodule STRUCTURAL MODEL: module dec38(y0,y1,y2,y3,y4,y5,y6,y7,a,b,c); input a,b,c; output y0,y1,y2,y3,y4,y5,y6,y7; wire w1,w2,w3; not n1 (a,w1); not n2 (b,w2); not n3 (c,w3); and a1 (y0,w1,w2,w3); and a2 (y1,w1,w2,c); and a3 (y2,w1,b,w3); and a4 (y3,w1,b,c); and a5 (y4,w2,w3); and a6 (y5,w2,c); and a7 (y6,a,b,w3); and a8 (y7,a,b,c); endmodule TESTBENCH for DECODER: module decoder_tb(); reg a, b, c; wire y0,y1,y2,y3,y4,y5,y6,y7; dec38 uut (y0,y1,y2,y3,y4,y5,y6,y7,a,b,c); initial begin {a,b,c} = 3’b000; #10 {a,b,c} = 3’b001; 9 #10 {a,b,c} = 3’b010; #10 {a,b,c} = 3’b011; #10 {a,b,c} = 3’b100; #10 {a,b,c} = 3’b101; #10 {a,b,c} = 3’b110; #10 {a,b,c} = 3’b111; End endmodule 8: ENCODER (8:3) DATAFLOW MODEL: module enc83_df(y0,y1,y2,d0,d1,d2,d3,d4,d5,d6,d7); input d0,d1,d2,d3,d4,d5,d6,d7; output y0,y1,y2; assign y2 = d4|d5|d6|d7; assign y1 = d2|d3|d6|d7; assign y0 = d1|d3|d5|d7; endmodule BEHAVIORAL MODEL: module enc83_b(y,a); input [7:0]a; output [2:0]y; reg [2:0]y; always @(a) case (a) 8'h01:y=3'b000; 8'h02:y=3'b001; 8'h04:y=3'b010; 8'h08:y=3'b011; 8'h10:y=3'b100; 8'h20:y=3'b101; 8'h40:y=3'b110; 8'h80:y=3'b111; endcase endmodule TESTBENCH for ENCODER: module decoder_tb(); reg [7:0] a; wire y0,y1,y2; enc83 uut (y0,y1,y2,a); initial begin a = 8’b00000001; #10 a = 8’b00000010; #10 a = 8’b00000100; #10 a = 8’b00001000; #10 a = 8’b00010000; #10 a = 8’b00100000; 10 #10 a = 8’b01000000; #10 a = 8’b10000000; End endmodule 9a: MULTIPLEXER (2:1) Logic Symbol Truth Table Circuit Diagram DATAFLOW MODEL: module mux_2(y,a,b,s); input a,b,s; output y; assign y = s?b:a; endmodule BEHAVIORAL MODEL: module mux_2(y,a,b,s); input a,b,s; output y; reg y; always @(a,b,s) case (s) 1'b0:y=a; 1'b1:y=b; Endcase endmodule STRUCTURAL MODEL: module mux_2(y,a,b,s); input a,b,s; output y; wire i1,w1,w2; not n1 (s,i1); and a1 (i1,a,w1); and a2 (s,b,w2); or o1(w1,w2,y); endmodule 11  9b: MULTIPLEXER (4:1) Logic Symbol Truth Table Circuit Diagram DATAFLOW MODEL module mux_4(y,a,b,c,d,s1,s2); input a,b,c,d,s1,s2; output y; assign y=s2?(s1?d:c):(s1?b:a); endmodule BEHAVIORAL MODEL module mux_4(y,a,b,c,d,s1,s2); input a,b,c,d,s1,s2; output y; reg y; always @(s1,s2) case ({s1,s2}) 2'b00:y=a; 2'b01:y=b; 2'b10:y=c; 2'b11:y=d; endcase endmodule 12 STRUCTURAL MODEL module mux_4(y,a,b,c,d,s1,s2); input a,b,c,d,s1,s2; output y; wire n1,n2; notn01(s1,n1); notn02(s2,n2); and A1(n1,n2,a,w1); and A2(n1,s2,b,w2); and A3(s1,n2,c,w3); and A4(s1,s2,d,w4); or A5(w1,w2,w3,w4,y); endmodule 10a: DEMULTIPLEXER (2:1) Circuit Diagram Truth Table DATAFLOW MODEL module demux_2d(a,s,y); input a,s; output [1:0]y; assign y=(~s)&a; assign y=s&a; endmodule BEHAVIORAL MODEL module demux_2b(a,s,y); input a,s; output [1:0]y; reg [1:0]y; 13  always @(a,s) case (s) 1'b0:y=a; 1'b1:y=a; endcase endmodule STRUCTURAL MODEL module demux_2s(a,s,y); input a,s; output [1:0]y; wire w; notn1(s,w); anda1(w,a,y); anda2(s,a,y); endmodule 10b: DEMULTIPLEXER (4:1) Circuit Diagram Truth Table 14 DATAFLOW MODEL module demux_4d(a,s0,s1,y); input a,s0,s1; output [3:0]y; assign y=(~s1)&(~s0)&a; assign y=(~s1)&s0&a; assign y=s1&(~s0)&a; assign y=s1&s0&a; endmodule BEHAVIORAL MODEL module demux_4b(a,s1,s0,y); input a,s1,s0; output [3:0]y; reg [3:0]y; always @(a,s1,s0) case ({s1,s0}) 2'b00:y=a; 2'b01:y=a; 2'b10:y=a; 2'b11:y=a; endcase endmodule STRUCTURAL MODEL module demux_4s(a,s0,s1,y); input a,s0,s1; output [3:0]y; wire w1,w2; notn1(s0,w1); notn2(s1,w2); anda1(w2,w1,a,y); anda2(w2,s0,a,y); anda3(s1,w1,a,y); anda4(s1,s0,a,y); endmodule 15