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Digital electronics First Stage Dr. Yousif Hardan 1- Asynchronous Counters : The term asynchronous refers to events that do not have a fixed time relationship with each other and, generally, do not occur at the same time. An asynchronous counter is one in which the flip-flops (FF) within the count...

Digital electronics First Stage Dr. Yousif Hardan 1- Asynchronous Counters : The term asynchronous refers to events that do not have a fixed time relationship with each other and, generally, do not occur at the same time. An asynchronous counter is one in which the flip-flops (FF) within the counter do not change states at exactly the same time because they do not have a common clock pulse. A 2-Bit Asynchronous Binary Counter Figure 1 shows a 2-bit counter connected for asynchronous operation. Notice that the clock (CLK) is applied to the clock input (C) of only the first flip-flop, FF0, which is always the least significant bit (LSB). The second flip-flop, FF1, is triggered by the Q0 output of FF0. FF0 changes state at the positive-going edge of each clock pulse, but FF1 changes only when triggered by a positive-going transition of the Q0 output of FF0. Because of the inherent propagation delay time through a flip-flop, a transition of the input clock pulse (CLK) and a transition of the Q0 output of FF0 can never occur at exactly the same time. Therefore, the two flip- flops are never simultaneously triggered, so the counter operation is asynchronous. FIGURE 1-1 A 2-bit asynchronous binary counter. 1 Digital electronics First Stage Dr. Yousif Hardan The Timing Diagram Let’s examine the basic operation of the asynchronous counter of Figure 1 by applying four clock pulses to FF0 and observing the Q output of each flip-flop. Figure 2 illustrates the changes in the state of the flip-flop outputs in response to the clock pulses. Both flip-flops are connected for toggle operation (D = Q) and are assumed to be initially RESET (Q LOW). The positive-going edge of CLK1 (clock pulse 1) causes the Q0 output of FF0 to go HIGH, as shown in Figure 2. At the same time the Q0 output goes LOW, but it has no effect on FF1 because a positive-going transition must occur to trigger the flip-flop. After the leading edge of CLK1, Q0 = 1 and Q1 = 0. The positive-going edge of CLK2 causes Q0 to go LOW. Output Q0 goes HIGH and triggers FF1, causing Q1 to go HIGH. After the leading edge of CLK2, Q0 = 0 and Q1 = 1. The positive-going edge of CLK3 causes Q0 to go HIGH again. Output Q0 goes LOW and has no effect on FF1. Thus, after the leading edge of CLK3, Q0 = 1 and Q1 = 1. The positive-going edge of CLK4 causes Q0 to go LOW, while Q0 goes HIGH and triggers FF1, causing Q1 to go LOW. After the leading FIGURE 1-2 Timing diagram for the counter of Figure 1. edge of CLK4, Q0 = 0 and Q1 = 0. The counter has now recycled to its original state (both flip-flops are RESET). In the timing diagram, the waveforms of the Q0 and Q1 outputs are shown relative to the clock pulses as illustrated in Figure 2. For simplicity, the transitions of Q0, Q1, and the clock pulses are shown as simultaneous even though this is an asynchronous counter. There is, of course, some small delay between the CLK and the Q0 transition and between the Q0 transition and the Q1 transition. 2 Digital electronics First Stage Dr. Yousif Hardan Note in Figure 2 that the 2-bit counter exhibits four different states, as you would expect with two flip-flops (22 4). Also, notice that if Q0 represents the least significant bit (LSB) and Q1 represents the most significant bit (MSB), the sequence of counter states represents a sequence of binary numbers as listed in Table 1. Since it goes through a binary sequence, the counter in Figure 1 is a binary counter. It actually counts the number of clock pulses up to three, and on the fourth pulse it recycles to its original state (Q0 = 0, Q1 = 0). The term recycle is commonly applied to counter operation; it refers to the transition of the counter from its final state back to its original state. A 3-Bit Asynchronous Binary Counter The state sequence for a 3-bit binary counter is listed in Table 2, and a 3-bit asynchronous binary counter is shown in Figure 3(a). The basic operation is the same as that of the 2-bit 3 Digital electronics First Stage Dr. Yousif Hardan FIGURE 1-3 Three-bit asynchronous binary counter and its timing diagram for one cycle. 4 Digital electronics First Stage Dr. Yousif Hardan counter except that the 3-bit counter has eight states, due to its three flip- flops. A timing diagram is shown in Figure 3(b) for eight clock pulses. Notice that the counter progresses through a binary count of zero through seven and then recycles to the zero state. This counter can be easily expanded for higher count, by connecting additional toggle flip-flops. Propagation Delay Asynchronous counters are commonly referred to as ripple counters for the following reason: The effect of the input clock pulse is first “felt” by FF0. This effect cannot get to FF1 immediately because of the propagation delay through FF0. Then there is the propagation delay through FF1 before FF2 can be triggered. Thus, the effect of an input clock pulse “ripples” through the counter, taking some time, due to propagation delays, to reach the last flip-flop. To illustrate, notice that all three flip-flops in the counter of Figure 3 change state on the leading edge of CLK4. This ripple clocking effect is shown in Figure 4 for the first four clock pulses, with the propagation delays indicated. The LOW-to-HIGH transition of FIGURE 1-4 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter. 5 Digital electronics First Stage Dr. Yousif Hardan Q0 occurs one delay time (tPLH) after the positive-going transition of the clock pulse. The LOW-to-HIGH transition of Q1 occurs one delay time (tPLH) after the positive-going transition of Q0. The LOW-to-HIGH transition of Q2 occurs one delay time (tPLH) after the positive-going transition of Q1. As you can see, FF2 is not triggered until two delay times after the positive-going edge of the clock pulse, CLK4. Thus, it takes three propagation delay times for the effect of the clock pulse, CLK4, to ripple through the counter and change Q2 from LOW to HIGH. This cumulative delay of an asynchronous counter is a major disadvantage in many applications because it limits the rate at which the counter can be clocked and creates decoding problems. The maximum cumulative delay in a counter must be less than the period of the clock waveform. Asynchronous Decade Counters The modulus of a counter is the number of unique states through which the counter will sequence. The maximum possible number of states (maximum modulus) of a counter is 2n, where n is the number of flip-flops in the counter. Counters can be designed to have a number of states in their sequence that is less than the maximum of 2n. This type of sequence is called a truncated sequence. One common modulus for counters with truncated sequences is ten (called MOD10). Counters with ten states in their sequence are called decade counters. A decade counter with a count sequence of zero (0000) through nine (1001) is a BCD decade counter because its ten-state sequence produces the BCD code. This type of counter is useful in display applications in which BCD is required for conversion to a decimal readout. To obtain a truncated sequence, it is necessary to force the counter to recycle before going through all of its possible states. For example, the BCD decade counter must recycle back to the 0000 state after the 1001 state. A decade counter requires four flip-flops (three flip-flops are insufficient because 23 = 8). 6 Digital electronics First Stage Dr. Yousif Hardan Let’s use a 4-bit asynchronous counter such as the one in Example 9–1 and modify its sequence to illustrate the principle of truncated counters. One way to make the counter recycle after the count of nine (1001) is to decode count ten (1010) with a NAND gate and connect the output of the NAND gate to the clear (CLR) inputs of the flip-flops, as shown in Figure 5(a). Partial Decoding Notice in Figure 5(a) that only Q1 and Q3 are connected to the NAND gate inputs. This arrangement is an example of partial decoding, in which the two unique states (Q1 = 1 and Q3 = 1) are sufficient to decode the count of ten because none of the other states (zero through nine) have both Q1 and Q3 HIGH at the same time. When the counter goes into count ten (1010), the decoding gate output goes LOW and asynchronously resets all the flip- flops. The resulting timing diagram is shown in Figure 5(b). Notice that there is a glitch on the Q1 waveform. The reason for this glitch is that Q1 must first go HIGH before the count of ten can be decoded. Not until several nanoseconds after the counter goes to the count of ten does the output of the decoding gate go LOW (both inputs are HIGH). Thus, the counter is in the 1010 state for a short time before it is reset to 0000, thus producing the glitch on Q1 and the resulting glitch on the CLR line that resets the counter. 7 Digital electronics First Stage Dr. Yousif Hardan FIGURE 1-5 An asynchronously clocked decade counter with asynchronous recycling. 2- Synchronous Counters : The term synchronous refers to events that have a fixed time relationship with each other. A synchronous counter is one in which all the flip-flops in the counter are clocked at the same time by a common clock pulse. J-K flip-flops are used to illustrate most synchronous counters. D flip-flops can also be used but generally require more logic because of having no direct toggle or no-change states. A 2-Bit Synchronous Binary Counter Figure 1 shows a 2-bit synchronous binary counter. Notice that an arrangement different from that for the asynchronous counter must be used for the J1 and K1 inputs of FF1 in order to achieve a binary sequence. A D flip-flop implementation is shown in part (b). 8 Digital electronics First Stage Dr. Yousif Hardan FIGURE 2-1 2-bit synchronous binary counters. The operation of a J-K flip-flop synchronous counter is as follows: First, assume that the counter is initially in the binary 0 state; that is, both flip- flops are RESET. When the positive edge of the first clock pulse is applied, FF0 will toggle and Q0 will therefore go HIGH. What happens to FF1 at the positive-going edge of CLK1? To find out, let’s look at the input conditions of FF1. Inputs J1 and K1 are both LOW because Q0, to which they are connected, has not yet gone HIGH. Remember, there is a propagation delay from the triggering edge of the clock pulse until the Q output actually makes a transition. So, J = 0 and K = 0 when the leading edge of the first clock pulse is applied. This is a no-change condition, and therefore FF1 does not change state. A timing detail of this portion of the counter operation is shown in Figure 2 (a). FIGURE 2-2 Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-flops are assumed to be equal). 9 Digital electronics First Stage Dr. Yousif Hardan After CLK1, Q0 = 1 and Q1 = 0 (which is the binary 1 state). When the leading edge of CLK2 occurs, FF0 will toggle and Q0 will go LOW. Since FF1 has a HIGH (Q0 = 1) on its J1 and K1 inputs at the triggering edge of this clock pulse, the flip-flop toggles and Q1 goes HIGH. Thus, after CLK2, Q0 = 0 and Q1 = 1 (which is a binary 2 state). The timing detail for this condition is shown in Figure 2 (b). When the leading edge of CLK3 occurs, FF0 again toggles to the SET state (Q0 = 1), and FF1 remains SET (Q1 = 1) because its J1 and K1 inputs are both LOW (Q0 = 0). After this triggering edge, Q0 = 1 and Q1 = 1 (which is a binary 3 state). The timing detail is shown in Figure 2 (c). Finally, at the leading edge of CLK4, Q0 and Q1 go LOW because they both have a toggle condition on their J and K inputs. The timing detail is shown in Figure 2 (d). The counter has now recycled to its original state, binary 0. Examination of the D flip-flop counter in Figure 1 (b) will show the timing diagram is the same as for the J-K flip-flop counter. The complete timing diagram for the counters in Figure 1 is shown in Figure 3. Notice that all the waveform transitions appear coincident; that is, the propagation delays are not indicated. Although the delays are an important factor in the synchronous counter operation, in an overall timing diagram they are normally omitted for simplicity. Major waveform relationships resulting from the normal operation of a circuit can be conveyed completely without showing small delay and timing differences. However, in high-speed digital circuits, these small delays are an important consideration in design and troubleshooting. FIGURE 2-3 Timing diagram for the counters of Figure 1. 10 Digital electronics First Stage Dr. Yousif Hardan A 3-Bit Synchronous Binary Counter A 3-bit synchronous binary counter is shown in Figure 4, and its timing diagram is shown in Figure 5. You can understand this counter operation by examining its sequence of states as shown in Table 1. FIGURE 2-4 A 3-bit synchronous binary counter. FIGURE 2-5 Timing diagram for the counter of Figure 4. 11 Digital electronics First Stage Dr. Yousif Hardan First, let’s look at Q0. Notice that Q0 changes on each clock pulse as the counter progresses from its original state to its final state and then back to its original state. To produce this operation, FF0 must be held in the toggle mode by constant HIGHs on its J0 and K0 inputs. Notice that Q1 goes to the opposite state following each time Q0 is a 1. This change occurs at CLK2, CLK4, CLK6, and CLK8. The CLK8 pulse causes the counter to recycle. To produce this operation, Q0 is connected to the J1 and K1 inputs of FF1. When Q0 is a 1 and a clock pulse occurs, FF1 is in the toggle mode and therefore changes state. The other times, when Q0 is a 0, FF1 is in the no- change mode and remains in its present state. Next, let’s see how FF2 is made to change at the proper times according to the binary sequence. Notice that both times Q2 changes state, it is preceded by the unique condition in which both Q0 and Q1 are HIGH. This condition is detected by the AND gate and applied to the J2 and K2 inputs of FF2. Whenever both Q0 and Q1 are HIGH, the output of the AND gate makes the J2 and K2 inputs of FF2 HIGH, and FF2 toggles on the following clock pulse. At all other times, the J2 and K2 inputs of FF2 are held LOW by the AND gate output, and FF2 does not change state. 12 Digital electronics First Stage Dr. Yousif Hardan The analysis of the counter in Figure 4 is summarized in Table 2. A 4-Bit Synchronous Binary Counter Figure 6 (a) shows a 4-bit synchronous binary counter, and Figure 6 (b) shows its timing diagram. This particular counter is implemented with negative edge-triggered flip- flops. The reasoning behind the J and K input control for the first three flip- flops is the same as previously discussed for the 3-bit counter. The fourth stage, FF3, changes only twice in the sequence. Notice that both of these transitions occur following the times that Q0, Q1, and Q2 are all HIGH. This condition is decoded by AND gate G2 so that when a clock pulse occurs, FF3 will change state. For all other times the J3 and K3 inputs of FF3 are LOW, and it is in a no-change condition. 13 Digital electronics First Stage Dr. Yousif Hardan FIGURE 2-6 A 4-bit synchronous binary counter and timing diagram. A 4-Bit Synchronous Decade Counter As you know, a BCD decade counter exhibits a truncated binary sequence and goes from 0000 through the 1001 state. Rather than going from the 1001 state to the 1010 state, it recycles to the 0000 state. A synchronous BCD decade counter is shown in Figure 7. The timing diagram for the decade counter is shown in Figure 8. 14 Digital electronics First Stage Dr. Yousif Hardan FIGURE 2-7 A synchronous BCD decade counter. FIGURE 2-8 Timing diagram for the BCD decade counter (Q0 is the LSB). The counter operation is shown by the sequence of states in Table 3. First, notice that FF0 (Q0) toggles on each clock pulse, so the logic equation for its J0 and K0 inputs is J 0 = K0 = 1 This equation is implemented by connecting J0 and K0 to a constant HIGH level. 15 Digital electronics First Stage Dr. Yousif Hardan Next, notice in Table 3 that FF1 (Q1) changes on the next clock pulse each time Q0 = 1 and Q3 = 0, so the logic equation for the J1 and K1 inputs is J1 = K1 = Q0Q3 This equation is implemented by ANDing Q0 and Q3 and connecting the gate output to the J1 and K1 inputs of FF1. Flip-flop 2 (Q2) changes on the next clock pulse each time both Q0 = 1 and Q1 = 1. This requires an input logic equation as follows: J2 = K2 = Q0Q1 This equation is implemented by ANDing Q0 and Q1 and connecting the gate output to the J2 and K2 inputs of FF2. Finally, FF3 (Q3) changes to the opposite state on the next clock pulse each time Q0 = 1, Q1 = 1, and Q2 = 1 (state 7), or when Q0 = 1 and Q3 = 1 (state 9). The equation for this is as follows: J3 = K3 = Q0Q1Q2 + Q0Q3 16 Digital electronics First Stage Dr. Yousif Hardan This function is implemented with the AND/OR logic connected to the J3 and K3 inputs of FF3 as shown in the logic diagram in Figure 7. Notice that the differences between this decade counter and the modulus-16 binary counter in Figure 6 (a) are the Q0Q3 AND gate, the Q0Q3 AND gate, and the OR gate; this arrangement detects the occurrence of the 1001 state and causes the counter to recycle properly on the next clock pulse. Up/Down Synchronous Counters An up/down counter is one that is capable of progressing in either direction through a certain sequence. An up/down counter, sometimes called a bidirectional counter, can have any specified sequence of states. A 3-bit binary counter that advances upward through its sequence (0, 1, 2, 3, 4, 5, 6, 7) and then can be reversed so that it goes through the sequence in the opposite direction (7, 6, 5, 4, 3, 2, 1, 0) is an illustration of up/down sequential operation. In general, most up/down counters can be reversed at any point in their sequence. For instance, the 3-bit binary counter can be made to go through the following sequence: 17 Digital electronics First Stage Dr. Yousif Hardan Table 4 shows the complete up/down sequence for a 3-bit binary counter. The arrows indicate the state-to-state movement of the counter for both its UP and its DOWN modes of operation. An examination of Q0 for both the up and down sequences shows that FF0 toggles on each clock pulse. Thus, the J0 and K0 inputs of FF0 are J 0 = K0 = 1 For the up sequence, Q1 changes state on the next clock pulse when Q0 = 1. For the down sequence, Q1 changes on the next clock pulse when Q0 = 0. Thus, the J1 and K1 inputs of FF1 must equal 1 under the conditions expressed by the following equation: J1 = K1 = (Q0. UP) + (Q0. DOWN) For the up sequence, Q2 changes state on the next clock pulse when Q0 = Q1 = 1. For the down sequence, Q2 changes on the next clock pulse when Q 0 = Q1 = 0. Thus, the J2 and K2 inputs of FF2 must equal 1 under the conditions expressed by the following equation: J2 = K2 = (Q0. Q1. UP) + (Q0. Q 1. DOWN) 18 Digital electronics First Stage Dr. Yousif Hardan Each of the conditions for the J and K inputs of each flip-flop produces a toggle at the appropriate point in the counter sequence. Figure 9 shows a basic implementation of a 3-bit up/down binary counter using the logic equations just developed for the J and K inputs of each flip-flop. Notice that the UP/DOWN control input is HIGH for UP and LOW for DOWN. FIGURE 2-9 A basic 3-bit up/down synchronous counter. Counter Decoding In many applications, it is necessary that some or all of the counter states be decoded. The decoding of a counter involves using decoders or logic gates to determine when the counter is in a certain binary state in its sequence. For instance, the terminal count function previously discussed is a single decoded state (the last state) in the counter sequence. Suppose that you wish to decode binary state 6 (110) of a 3-bit binary counter. When Q2 = 1, Q1 = 1, and Q0 = 0, a HIGH appears on the output of the decoding gate, indicating that the counter is at state 6. This can be done as shown in Figure 10. This is called 19 Digital electronics First Stage Dr. Yousif Hardan active-HIGH decoding. Replacing the AND gate with a NAND gate provides active-LOW decoding. FIGURE 2-10 Decoding of state 6 (110). 20