Digital Counter Decoding

Partial Decoding

• Partial decoding is an arrangement where only specific states are sufficient to decode the count because none of the other states have both inputs HIGH at the same time.
• In Figure 5(a), only Q1 and Q3 are connected to the NAND gate inputs, which is an example of partial decoding.
• When the counter goes into count ten (1010), the decoding gate output goes LOW and asynchronously resets all the flip-flops.

Synchronous Counters

• A synchronous counter is one in which all the flip-flops in the counter are clocked at the same time by a common clock pulse.
• J-K flip-flops are used to illustrate most synchronous counters.
• D flip-flops can also be used but generally require more logic because of having no direct toggle or no-change states.

2-Bit Synchronous Binary Counter

• Figure 1 shows a 2-bit synchronous binary counter.
• The operation of a J-K flip-flop synchronous counter is as follows:
  • First, assume that the counter is initially in the binary 0 state; that is, both flip-flops are RESET.
  • When the positive edge of the first clock pulse is applied, FF0 will toggle and Q0 will therefore go HIGH.
  • FF1 does not change state at the positive-going edge of CLK1 because J1 and K1 are both LOW.

Timing Details

• A timing detail of the 2-bit synchronous counter operation is shown in Figure 2 (a).
• After CLK1, Q0 = 1 and Q1 = 0 (which is the binary 1 state).
• When the leading edge of CLK2 occurs, FF0 will toggle and Q0 will go LOW.
• FF1 toggles and Q1 goes HIGH because J1 and K1 are both HIGH at the triggering edge of this clock pulse.

3-Bit Synchronous Binary Counter

• A 3-bit synchronous binary counter is shown in Figure 4, and its timing diagram is shown in Figure 5.
• The counter operation can be understood by examining its sequence of states as shown in Table 1.

BCD Decade Counter

• The counter operation is shown by the sequence of states in Table 3.
• FF0 (Q0) toggles on each clock pulse, so the logic equation for its J0 and K0 inputs is J0 = K0 = 1.
• FF1 (Q1) changes on the next clock pulse each time Q0 = 1 and Q3 = 0, so the logic equation for the J1 and K1 inputs is J1 = K1 = Q0Q3.
• FF2 (Q2) changes on the next clock pulse each time both Q0 = 1 and Q1 = 1, so the logic equation for the J2 and K2 inputs is J2 = K2 = Q0Q1.
• FF3 (Q3) changes to the opposite state on the next clock pulse each time Q0 = 1, Q1 = 1, and Q2 = 1 (state 7), or when Q0 = 1 and Q3 = 1 (state 9), so the equation is J3 = K3 = Q0Q1Q2 + Q0Q3.

Up/Down Synchronous Counters

• An up/down counter is one that is capable of progressing in either direction through a certain sequence.
• A 3-bit binary counter that advances upward through its sequence (0, 1, 2, 3, 4, 5, 6, 7) and then can be reversed so that it goes through the sequence in the opposite direction (7, 6, 5, 4, 3, 2, 1, 0) is an illustration of up/down sequential operation.
• Table 4 shows the complete up/down sequence for a 3-bit binary counter.
• For the up sequence, Q1 changes state on the next clock pulse when Q0 = 1. For the down sequence, Q1 changes on the next clock pulse when Q0 = 0.