VLSI Design Flow: RTL to GDS Lecture 22 PDF

VLSI DESIGN FLOW: RTL TO GDS Lecture 22 Static Timing Analysis – Part I Sneh Saurabh Electronics and Communications Engineering...

VLSI DESIGN FLOW: RTL TO GDS Lecture 22 Static Timing Analysis – Part I Sneh Saurabh Electronics and Communications Engineering IIIT Delhi Lecture Plan Static Timing Analysis (STA) ▪ Basics of STA (this lecture) ▪ Subsequent Lectures: Mechanics of STA Advanced concepts of STA Constraints VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh  Static Timing Analysis Basics VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Static Timing Analysis (STA): What is done? ▪ Ensures that the circuit is in a valid state at each STA Simulation clock cycle ▪ Verifies that the design is capable of operating at No test-vector Test vector the given frequency required required Information of frequency comes from constraints No check of Checks ▪ Ensures that the design does not have setup or functionality functionality hold violation at flip-flop Analysis Simulation done performed taking based on ▪ The analysis is based on worst case scenario and pessimistic view of specified test takes a pessimistic view wherever possible delays and other vectors and Verification is done without test vector and attributes of the delays simulation (therefore static) design Ensures that design will not have setup or hold violations for any test vector VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Synchronous Circuit: Data Propagation Consider a synchronous circuit shown alongside. Assume that: ▪ Flip-flops are ideal ▪ Buffers have some delay ▪ Inputs at the port IN are applied as shown [using identifiers for clarity] ▪ State defined by the combination of values at the Q-pin ▪ Initial state is {PQ} Let us understand the behavior of the circuit in different clock cycles for various cases of delay of the buffers. VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Synchronous Circuit: Synchronous Behavior Assume that: ▪ Delay of D1, D2, and D3 be some finite value less than the clock period, and ▪ Delays of C1 and C2 are negligible. These are valid states of a synchronous circuit. VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Synchronous Circuit: Zero Clocking Assume that: ▪ Delay of C1 and C2 are negligible. ▪ Delay of the circuit element D2 is more than one clock period, but less than two clock periods. ▪ Delay of D1 and D3 are minimal. ▪ In effect clock fails to capture the right data (zero-clocking) due to late data arrival ▪ The circuit goes into invalid states VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Synchronous Circuit: Double Clocking Assume that: ▪ Delay of circuit elements D1, D2, D3, and C1 are insignificant. ▪ Delay of the circuit element C2 is ∆ ▪ In effect, the data gets captured by two flop-flops by the same clock edge (double clocking) ▪ The circuit goes into invalid states VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Synchronous Circuit: Verification To ensure synchronous behavior: ▪ Avoid Zero Clocking: setup analysis or late analysis ▪ Avoid Double Clocking: hold analysis or early analysis ▪ A synchronous circuit can contain many flip-flops Data can propagate sequentially through a pipeline before reaching the output ▪ Examine each pair of launch and capture flip-flops separately ▪ Various types of combinational gates can be encountered in a path ▪ Add the delay of all the combinational circuit elements (and also the wire delay) in the path and check for delay requirements ▪ Real flip-flops have ST, HT, CK-Q delay ▪ Account for them (make the verification a bit more pessimistic) VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Static Timing Analysis (STA) : Setup Requirement (1) ▪ Ensures that the data sent by launch flip-flop in a given clock cycle is captured reliably by the capture flip-flop in the next clock cycle ▪ Ensures that the setup requirement of the flip-flop is also met Arrival Time of data at the D-pin: 𝑡𝑎𝑟𝑟𝑖𝑣𝑎𝑙 = 𝑇𝑙𝑎𝑢𝑛𝑐ℎ + 𝑇𝑐𝑙𝑘−𝑞𝑙 + 𝑇𝑑𝑎𝑡𝑎 Required time for data to settle at FF2/D: 𝑡𝑟𝑒𝑞,𝑠𝑒𝑡 = 𝑇𝑝𝑒𝑟𝑖𝑜𝑑 + 𝑇𝑐𝑎𝑝𝑡𝑢𝑟𝑒 − 𝑇𝑠𝑒𝑡𝑢𝑝−𝑐 To avoid zero clocking and setup-time constraints of flip-flops: 𝑡𝑟𝑒𝑞,𝑠𝑒𝑡 > 𝑡𝑎𝑟𝑟𝑖𝑣𝑎𝑙 Setup requirement: 𝑇𝑝𝑒𝑟𝑖𝑜𝑑 + 𝑇𝑐𝑎𝑝𝑡𝑢𝑟𝑒 − 𝑇𝑠𝑒𝑡𝑢𝑝−𝑐 > 𝑇𝑙𝑎𝑢𝑛𝑐ℎ + 𝑇𝑐𝑙𝑘−𝑞𝑙 + 𝑇𝑑𝑎𝑡𝑎 VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Static Timing Analysis (STA) : Setup Requirement (2) Setup Violations can occur if: ▪ Clock Period is decreased (clock frequency is increased) ▪ Delay of capture clock path is decreased ▪ Delay of data path is increased ▪ Delay of launch clock path is increased Setup requirement: 𝑇𝑝𝑒𝑟𝑖𝑜𝑑 + 𝑇𝑐𝑎𝑝𝑡𝑢𝑟𝑒 − 𝑇𝑠𝑒𝑡𝑢𝑝−𝑐 > 𝑇𝑙𝑎𝑢𝑛𝑐ℎ + 𝑇𝑐𝑙𝑘−𝑞𝑙 + 𝑇𝑑𝑎𝑡𝑎 𝑇𝑝𝑒𝑟𝑖𝑜𝑑 > (𝑇𝑙𝑎𝑢𝑛𝑐ℎ −𝑇𝑐𝑎𝑝𝑡𝑢𝑟𝑒 ) + 𝑇𝑐𝑙𝑘−𝑞𝑙 + 𝑇𝑑𝑎𝑡𝑎 + 𝑇𝑠𝑒𝑡𝑢𝑝−𝑐 What happens for an ideal flip-flop? 𝑇𝑝𝑒𝑟𝑖𝑜𝑑 > 𝛿𝑙𝑐 + 𝑇𝑐𝑙𝑘−𝑞𝑙 + 𝑇𝑑𝑎𝑡𝑎 + 𝑇𝑠𝑒𝑡𝑢𝑝−𝑐 [𝛿𝑙𝑐 is the clock skew] What happens for an ideal clocking structure? Most Restrictive: 𝑇𝑝𝑒𝑟𝑖𝑜𝑑 > 𝛿𝑙𝑐 + 𝑇𝑐𝑙𝑘−𝑞𝑙 + 𝑇𝑑𝑎𝑡𝑎,𝑚𝑎𝑥 + 𝑇𝑠𝑒𝑡𝑢𝑝−𝑐 VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Static Timing Analysis (STA) : Hold Requirement (1) ▪ The hold check is from one active edge of the clock in the launch flip-flop to the same clock edge at the capture flip-flop (independent of clock-period) ▪ Ensures that the hold requirement of the flip-flop is also met Data Reaches D-pin: 𝑡𝑎𝑟𝑟𝑖𝑣𝑎𝑙 = 𝑇𝑙𝑎𝑢𝑛𝑐ℎ + 𝑇𝑐𝑙𝑘−𝑞𝑙 + 𝑇𝑑𝑎𝑡𝑎 Data to arrive at FF2/D after the required time: 𝑡𝑟𝑒𝑞,ℎ𝑜𝑙𝑑 = 𝑇𝑐𝑎𝑝𝑡𝑢𝑟𝑒 + 𝑇ℎ𝑜𝑙𝑑−𝑐 To avoid double clocking and hold-time constraints of flip-flops: 𝑡𝑎𝑟𝑟𝑖𝑣𝑎𝑙 > 𝑡𝑟𝑒𝑞,ℎ𝑜𝑙𝑑 Hold requirement: 𝑇𝑙𝑎𝑢𝑛𝑐ℎ + 𝑇𝑐𝑙𝑘−𝑞𝑙 + 𝑇𝑑𝑎𝑡𝑎 > 𝑇𝑐𝑎𝑝𝑡𝑢𝑟𝑒 + 𝑇ℎ𝑜𝑙𝑑−𝑐 VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Static Timing Analysis (STA) : Hold Requirement (2) Hold requirement: 𝑇𝑙𝑎𝑢𝑛𝑐ℎ + 𝑇𝑐𝑙𝑘−𝑞𝑙 + 𝑇𝑑𝑎𝑡𝑎 > 𝑇𝑐𝑎𝑝𝑡𝑢𝑟𝑒 + 𝑇ℎ𝑜𝑙𝑑−𝑐 𝛿𝑙𝑐 + 𝑇𝑐𝑙𝑘−𝑞𝑙 + 𝑇𝑑𝑎𝑡𝑎 > 𝑇ℎ𝑜𝑙𝑑−𝑐 Most Restrictive requirement: 𝛿𝑙𝑐 + 𝑇𝑐𝑙𝑘−𝑞𝑙 + 𝑇𝑑𝑎𝑡𝑎,𝑚𝑖𝑛 > 𝑇ℎ𝑜𝑙𝑑−𝑐 ▪ Hold Violations can occur if: What happens for an ideal ▪ Delay of data path is decreased flip-flop? ▪ Delay of launch clock path is decreased What happens for an ideal ▪ Delay of capture clock path is increased clocking structure? VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh  References ▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press, 2023. soprotection.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh VLSI DESIGN FLOW: RTL TO GDS Lecture 23 Static Timing Analysis – Part II Sneh Saurabh Electronics and Communications Engineering IIIT Delhi Lecture Plan ▪ Mechanism of Static Timing Analysis VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Static Timing Analysis: Definitions STA considers two types of paths: Data Path: 1. Data Path ▪ Timing startpoints: input ports or 2. Clock Path clock-pin of a flip-flop ▪ Goes through combinational circuit elements ▪ Timing endpoints: D-pin of a flip-flop or output ports Setup and hold checks are performed at the timing endpoints Clock Path: ▪ Starts at clock source (specified in constraints) ▪ Four data paths ▪ Passes through the combinational circuit elements (buffers and ▪ Two clock paths inverters) ▪ Ends at a clock-pin of a flip-flop VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh  Static Timing Analysis How it works VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Timing Graph (1) STA starts with building a Timing Graph for a given circuit ▪ Timing Graph: is a directed acyclic graph 𝐺 = (𝑉 , 𝐸), where 𝑉 is the vertex set and 𝐸 is the edge set. ▪ The vertex 𝑣 ∈ 𝑉 corresponds to a pin or a port in the circuit. ▪ An edge 𝑒 ∈ 𝐸 represents a timing arc in the circuit An edge 𝑒𝑖,𝑗 = (𝑣𝑖 , 𝑣𝑗 ) exists in 𝐸 if and only if there ▪ Each edge 𝑒𝑖,𝑗 has annotated exists a timing arc between the corresponding pins information of delay 𝐷𝑖,𝑗 or ports in the circuit. (computed by Delay Calculation) Two types of edges: ▪ Cell Arc: Timing arc between two pins of the same cell ▪ Each vertex in the graph has arrival time, required time, ▪ Net Arc: Timing arc between two pins of different cells slack, etc. that are connected directly by a net VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Timing Graph (2) Source: vertices with no incoming edges ▪ Timing startpoints (input ports, clock-pin of FFs) and clock start points treated as sources Sink: vertices with no outgoing edges ▪ Timing endpoints (output ports, D- pin of FFs) treated as sinks VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Delay Calculation: Stage STA needs to know the delays for the timing arcs existing in the timing graph ▪ Retrieves it from a delay calculator ▪ Inbuilt or coupled with an STA tool ▪ Decomposes a given circuit into separate stages ▪ A stage is composed of a driving cell and its driven pins connected through wires. VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Delay Calculation: Essential Components Driver model: NLDM, CCS, ECSM Interconnect: ▪ Zero capacitance models, parasitic extraction ▪ Interconnect delay model: Lumped Capacitance, Elmore, Asymptotic Waveform Evaluation (AWE) Receiver model: capacitance, or more advanced ▪ Given a stage, we can compute the output waveform once we know the input waveform ▪ Delay calculation can be done in topological order (from input to output) ▪ Transition at input ports obtained using SDC or assumed by a tool ▪ Each edge 𝑒𝑖,𝑗 has annotated information of delay 𝐷𝑖,𝑗 and slew 𝑆𝑖,𝑗 VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Arrival Time Computation: Basic Concept Arrival Time (AT): time at which a signal settles at a given vertex When there is only one incoming edge: 𝐴𝑗 = 𝐴𝑖 + 𝐷𝑖𝑗 When there are multiple incoming edges: ▪ Can associate different arrival time for different edges ▪ Value at a vertex can toggle multiple times before settling ▪ A bound on the arrival time at a given vertex 𝑣𝑗 can be computed if the arrival times at all its input vertices 𝑣𝑖 are known: ▪ 𝑨𝒋,𝒎𝒊𝒏 = 𝑴𝒊𝒏(𝑨𝒊,𝒎𝒊𝒏 + 𝑫𝒊𝒋 ) ▪ 𝑨𝒋,𝒎𝒂𝒙 = 𝑴𝒂𝒙(𝑨𝒊,𝒎𝒂𝒙 + 𝑫𝒊𝒋 ) VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Arrival Time Computation: Method ▪ Arrival Time (AT) is computed and stored at each vertex in a timing graph ▪ AT at input ports specified by constraints or assumed to be zero ▪ AT computation is done by Forward Traversal of Timing Graph ▪ AT computation starts from the vertices corresponding to input ports ▪ A vertex is chosen for computing AT such that: ▪ All the input vertices of the given vertex have their AT already computed ▪ AT can be computed in one traversal of the vertices and edges of the timing graph VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Maximum Arrival Time Computation: Illustration 1 0 4 5 3 8 9 7 0 1 2 3 4 5 6 7 8 9 0 1 ▪ Assume that delay of all the edges = 1 time unit ▪ Similarly, minimum arrival time computation can be done ▪ Assume that AT is 0 at all sources VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Arrival Time Computation : Complications ▪ Rise/Fall Delays: ▪ Separate AT is computed for rise/fall cases ▪ Dependence of delay on the input slew (rise/fall transition time) ▪ Slew is also propagated and stored at each vertex, in addition to delay VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Required Time Computation: Basic Concept Required Time (RT): time constraint for a given vertex to avoid setup/hold violation ▪ Setup/Late analysis: the maximum time by which a signal should arrive to avoid violation ▪ Hold/Early analysis: the minimum time after which a signal should arrive to avoid timing violation ▪ Required time for a vertex 𝑣𝑖 can be computed if required times at all its output vertices 𝑣𝑗 are known: 𝑹𝒊,𝒉𝒐𝒍𝒅 = 𝑴𝒂𝒙(𝑹𝒋,𝒉𝒐𝒍𝒅 − 𝑫𝒊𝒋 ) 𝑹𝒊,𝒔𝒆𝒕𝒖𝒑 = 𝑴𝒊𝒏(𝑹𝒋,𝒔𝒆𝒕𝒖𝒑 − 𝑫𝒊𝒋 ) VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Required Time Computation: Method ▪ At each vertex in the Timing Graph Required Time (RT) is computed and stored ▪ RT at output ports or timing end-points is specified or inferred from constraints ▪ RT computation is done by Backward Traversal of Timing Graph ▪ RT computation starts from the vertices corresponding to output ports ▪ A vertex is chosen for computing RT such that: All the output vertices of the given vertex have their RT already computed ▪ RT can be computed in one traversal of the vertices and edges of the timing graph ▪ Delay of cell/net arcs calculated during AT computation is reused in RT computation ▪ RT constraints primarily determined by clock period VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Required Time Computation: Setup Analysis 8 7 9 10 8 11 12 10 2 3 4 5 6 7 8 9 10 11 6 7 ▪ Assume that delay of all the edges = 1 time unit ▪ Similarly, required time for hold analysis can be computed ▪ Assume that RT is 11 and 12 as shown at the sinks VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Slack Computation Setup or Late Analysis: ▪ 𝑆𝑙𝑎𝑐𝑘 = 𝑅𝑇 − 𝐴𝑇 ▪ Slack is the time by which AT at a vertex can be increased without causing setup violation AT can be increased till slack becomes zero Hold or Early Analysis: ▪ 𝑆𝑙𝑎𝑐𝑘 = 𝐴𝑇 − 𝑅𝑇 ▪ Slack is the time by which AT at a vertex can be decreased without causing hold violation AT can be decreased till slack becomes zero A negative slack implies that: ▪ Setup/Hold violation exists in the circuit ▪ Need to fix the circuit for proper operation VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Slack Computation: Illustration 1 0 4 5 3 8 9 7 0 1 2 3 4 5 6 7 8 9 0 1 8 7 9 10 8 11 12 10 2 3 4 5 6 7 8 9 10 11 6 7 VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh  References ▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press, 2023. ▪ Bhasker, Jayaram, and Rakesh Chadha. Static timing analysis for nanometer designs: A practical approach. Springer Science & Business Media, 2009. soprotection.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh VLSI DESIGN FLOW: RTL TO GDS Lecture 24 Static Timing Analysis – Part III Sneh Saurabh Electronics and Communications Engineering IIIT Delhi Lecture Plan ▪ Slew Propagation ▪ Accounting for Variations VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh  Static Timing Analysis Slew Propagation VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Need for Slew Propagation ▪ For computing delays for a given stage, the slews at its inputs must be known. An STA tool must also propagate the slews in the timing graph ▪ The propagated slews can be different through different combinational paths. VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Relationship between Slew and Delay ▪ Delay and the output slew are typically monotonically nondecreasing functions of the input slew ▪ Allows computing, storing, and propagating only the minimum/maximum slews Can obtain the bounds on the delay and the output slews using the bounds on the input slews. VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Slew Propagation: Bound on Slew ▪ 𝐴𝑗,𝑚𝑖𝑛 = 𝑀𝑖𝑛 𝐴𝑖,𝑚𝑖𝑛 + 𝐷𝑖𝑗,𝑚𝑖𝑛 ▪ 𝐴𝑗,𝑚𝑎𝑥 = 𝑀𝑎𝑥 𝐴𝑖,𝑚𝑎𝑥 + 𝐷𝑖𝑗,𝑚𝑎𝑥 ▪ 𝑆𝑗,𝑚𝑖𝑛 = 𝑀𝑖𝑛 𝑂𝑆𝑖𝑗,𝑚𝑖𝑛 ▪ 𝑆𝑗,𝑚𝑎𝑥 = 𝑀𝑎𝑥 𝑂𝑆𝑖𝑗,𝑚𝑎𝑥 VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Slew Propagation: Example (Maximum Case) ▪ 𝐴𝑦,𝑚𝑎𝑥 = 𝑀𝑎𝑥 100 + 50, 20 + 80 = 150 ▪ 𝐴𝑥,𝑚𝑎𝑥 = 150 + 100 = 250 ▪ 𝑆𝑦,𝑚𝑎𝑥 = 𝑀𝑎𝑥 10,30 = 30 ▪ 𝑆𝑥,𝑚𝑎𝑥 = 20 ▪ Graph-based Analysis (GBA): Safe Bound, Not tight (most popular) ▪ 𝐴𝑦,𝑚𝑎𝑥 = 150 ▪ 𝐴𝑥,𝑚𝑎𝑥 = 180 ▪ 𝐴𝑦,𝑚𝑎𝑥 = 100 ▪ 𝐴𝑥,𝑚𝑎𝑥 = 200 ▪ 𝑆𝑦,𝑚𝑎𝑥 = 10 ▪ 𝑆𝑥,𝑚𝑎𝑥 = 10 ▪ 𝑆𝑦,𝑚𝑎𝑥 = 30 ▪ 𝑆𝑥,𝑚𝑎𝑥 = 20 ▪ Path-based Analysis (PBA): Path-specific, computationally difficult VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh  Static Timing Analysis Accounting for Variations VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Need to Account for Variations ▪ Behavior of transistors/circuit elements can differ from the nominal behavior due to process-induced variations and fluctuations in temperature and voltage (PVT variations) Delay and other timing attributes change Can result in timing failure ▪ To tackle variations, different techniques are employed. Differ in accuracy, modeling effort, computational resource requirement, and design effort. VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Safety Margins ▪ Easiest technique ▪ Can convey margins to an STA tool using appropriate constraints Adjust the required time such that timing requirements become stricter ▪ Large Margin: overly pessimistic (loss in PPA) ▪ Small Margin: chance of timing failure, yield loss ▪ Need to consider these tradeoffs ▪ Typically employed in early stages of VLSI design flow VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh Multi-mode Multi-Corner (MMMC) Analysis ▪ Carry out STA at some discrete set of scenarios to account for variations Scenarios are created by a combination of: ▪ PVT corners for technology libraries: accounts for global variations (worst, best, typical, etc.) ▪ Multiple modes: using SDC files for different modes such functional, test, sleep, turbo, etc. ▪ Analyze multiple scenarios simultaneously using ▪ RC corners: extract multiple SPEF MMMC analysis files to account for process-induced ▪ Efficiency: variations in interconnects. Avoiding computation of the dominated scenarios Exploiting parallel processing VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh On-Chip Variations (OCV) Derate ▪ Need to account for local variations in Late path derating factor = 1.1 the properties of devices and Early path derating factor = 0.9 interconnects on the same die Specify OCV derate factors Setup Analysis: ▪ Effective delay: obtained by multiplying ▪ Data path and clock launch path: 1.1 the nominal delay with the OCV derating ▪ Clock capture path: 0.9 factor Hold Analysis: Can define different OCV derating factors ▪ Data path and clock launch path: 0.9 based on: ▪ Clock capture path: 1.1 ▪ Path bounds (early or late) ▪ Path type (data or clock) Demerit: ▪ Delay type (gate delay or interconnect ▪ Assumes perfect positive correlation delay) among timing arcs of same group ▪ Corners (best, worst, typical, etc.) ▪ Assumes perfect negative correlation among timing arcs of different group ▪ Overly pessimistic VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh  References ▪ S. Saurabh, “Introduction to VLSI Design Flow”. Cambridge: Cambridge University Press, 2023. ▪ Bhasker, Jayaram, and Rakesh Chadha. Static timing analysis for nanometer designs: A practical approach. Springer Science & Business Media, 2009. inprotected.com VLSI Design Flow: RTL to GDS NPTEL 2023 S. Saurabh