Integrated Circuits Design Lecture Notes PDF

Ministry of Higher Education Nahda University Faculty of Engineering Communications and Computers Engineering Program INTEGRATED CIRCUITS DESIGN (CCE313) BY D...

Ministry of Higher Education Nahda University Faculty of Engineering Communications and Computers Engineering Program INTEGRATED CIRCUITS DESIGN (CCE313) BY DR. MOHAMED ABDELKAREEM AHMED Fall 2025 What is an Integrated Circuit (IC)? Discrete vs. Integrated Electronics What is an Integrated Circuit (IC)? Analog vs Digital Signals Why Digital? IC Technology Generations IC Technology Generations cont’d How to Design a Billion Transistor Chip? Design Abstraction  Economics of VLSI ❑ The cost of an IC is roughly composed of two major factors: Fixed cost Variable cost. ❑ The fixed cost, also referred to as the nonrecurring engineering (NRE) cost, is independent of the sales volume. ❑ It is mainly contributed by the cost from which a project is started until the first successful prototype is obtained. ❑ More precisely, the fixed cost covers direct and indirect costs. ❑ The direct cost includes the research and design (R&D) cost, manufacturing mask cost, as well as marketing and sales cost. ❑ The indirect cost includes the investment of manufacturing equipment, the investment of CAD tools, building infrastructure cost, and so on. Economics of VLSI  Economics of VLSI ❑ The variable cost is proportional to the product volume and is mainly the cost of manufacturing wafers, namely, wafer price, which is roughly in the range between 1,200 and 1,600 USD for a 300-mm wafer. ❑ From the above discussion, the cost per IC can be expressed as follows. ❑ The variable cost per IC can be formulated as the following equation.  Economics of VLSI ❑ The cost of a die is the wafer price divided by the number of good dies and can be represented as the following formula. ❑ From the above discussion, the cost per IC can be expressed as follows. ❑ The number of dies in a wafer, excluding fragmented dies on the boundary, can be approximated by the following equation. Where: d is the diameter of the wafer. A is the area of square dies  Economics of VLSI ❑ The die yield can be estimated by the following widely used function. Where D0 is the defect density, i.e., the defects per unit area, in defects/cmsqure. The typical values of D0 are from 0.3 to 1.3. 𝛼 is a measure of manufacturing complexity. The typical values = 4. ❑ From this equation, it is clear that the die yield is inversely proportional to the die area. Economics of VLSI Economics of VLSI  ICs are categorized in three different ways: ❑ The underlying technology upon which their circuitry is based: ✓ Transistor-Transistor Logic (TTL) ✓ Complementary Metal Oxide Semiconductor (CMOS) ❑ The scale of integration: ✓ Small Scale Integration –SSI ✓ Medium Scale Integration –MSI ✓ Large Scale Integration -LSI ✓ Very Large-Scale Integration –VLSI ❑ Package Style: ✓ Through-Hole Technology -THT ✓ Dual Inline Packages -DIP ✓ Surface-Mount Technology –SMT ✓ Small Outline IC -SOIC ✓ Plastic Leaded Chip Carrier -PLCC ✓ Quad Flat Pack -QFP  TTL Vs. CMOS Logic ❑ Transistor Transistor Logic ❑ CMOS: Complementary Metal Constructed from Bipolar Junction Oxide Semiconductor Transistors (BJT) Constructed from Metal Oxide Semiconductor Field Effect Transistors ( MOSFET) ❑ Advantages: ❑ Advantages: Faster than CMOS Uses less power than TTL Not sensitive to damage from electrostatic discharge ❑ Disadvantages: ❑ Disadvantages: Uses more power than CMOS Slower than TTL Very sensitive to damage from electrostatic discharge IC Density of Integration  Package Styles Through-Hole Technology (THT) Surface Mount Technology (SMT) DIP: Dual Inline Package SOIC: Small Outline IC TTL Logic Sub Families TTL Logic Gate Numbering System