Addressing Modes PDF

Chap 4 - Addressing Modes CE/CZ1106 Chapter 4 Addressing Modes 1 Addressing Modes Introduction to Assembly Programming...

Chap 4 - Addressing Modes CE/CZ1106 Chapter 4 Addressing Modes 1 Addressing Modes Introduction to Assembly Programming and Addressing Modes Learning Objectives (4.1) 1. Identify why and when to use assembly language programming. 2. Describe what are addressing modes. 2 (c) A/P Goh Wooi Boon - 2020 1 Chap 4 - Addressing Modes CE/CZ1106 What is an Assembly Program? Unlike high-level programming languages, assembly level statements: Are known as mnemonics. Each has a one-to-one correspondence with a binary pattern (machine code) that is directly understood by CPU. Are hardware-dependent and address the architecture of processor directly. (e.g. they are CPU register-aware and reference them by name). Are converted to machine code by an assembler. CMP R0,R2 BLE Else if (a > c) MOV R1,R0 ;b = a b = a; B Skip else Else MOV R1,R2 ;b = c b = c; Skip : C program example ARM assembly program equivalent 3 Why Use Assembly Language? More efficient codes can be created: Codes with faster execution speed. e.g. Algorithms for real-time signal processing in handheld devices can be computationally demanding. More compact program size. e.g. Low cost embedded devices may have small memory capacity but require many functionalities. Exploit optimized features of processor’s ISA. e.g. High-level language compiled codes may not exploit optimized instructions, addressing modes and features available in the processor instruction set architecture to produce efficient run-time code. Many cybersecurity jobs needs good knowledge in assembly programming. 4 (c) A/P Goh Wooi Boon - 2020 2 Chap 4 - Addressing Modes CE/CZ1106 When to Use Assembly Language? Critical parts of the operating system’s software. Especially parts of system kernel that are constantly being executed (e.g. scheduler, interrupt handlers). Input/Output intensive codes. Device drivers and “loopy” segments of code that processes streaming data (e.g. video decoders, etc). Time-critical codes. Code that detect incoming sensor signals and respond rapidly, e.g. Anti-lock brake system (ABS) in cars. Learn More: Google “Is Linux kernel written in assembly” 5 Addressing Modes Addressing mode (AM) is concerned with how data is accessed, not the way data is processed. The correct AM allows the CPU to identify the actual operand or the address location where operand is stored. The ARM processor instruction set architecture supports many different addressing modes. Register direct Immediate data Register indirect Register indirect with offset Register indirect with index register Pre and post auto-indexing Learn More: Google “addressing modes” 6 (c) A/P Goh Wooi Boon - 2020 3 Chap 4 - Addressing Modes CE/CZ1106 Addressing Mode Examples Addressing Mode ARM Intel Absolute (Direct) None MOV AX,[1000h] Register Direct MOV R1,R0 MOV AX,DX Immediate MOV R1,#3 MOV AX,0003h Register Indirect LDR R1,[R0] MOV AX,[BX] Register Indirect LDR R1,[R0,#4] MOV AX,[BX+4] with Offset Register Indirect LDR R1,[R0,R2] MOV AH,[BX+DI] with Index Implied BNE LOOP JMP -8 7 Summary Codes written well in assembly language can usually execute faster and are smaller in size. Code for low-level OS kernels, I/O intensive and time-critical operations can benefit significantly from assembly-level coding. Understanding the characteristics and application of different addressing modes available in a processor’s ISA allows programmers to write efficient codes. 8 (c) A/P Goh Wooi Boon - 2020 4 Chap 4 - Addressing Modes CE/CZ1106 Chapter 4 Addressing Modes Register Direct and Immediate Addressing Learning Objectives (4.2) 1. Describe what is register direct. 2. Describe what is immediate data and its application. 9 Register Direct Operand is the content of the specified register. Register direct can be used for both destination and source operand. In the MOV instruction, the right operand is the source and left operand is the destination. R0 0x12345678 Copy operation R1 0x00000000 Before execution MOV R1,R0 Destination Source R0 0x12345678 A fast addressing mode since no further memory R1 0x00000000 12345678 access is involved during execution. Before execution After execution Should be used to optimise execution speed. 10 (c) A/P Goh Wooi Boon - 2020 5 Chap 4 - Addressing Modes CE/CZ1106 Register Direct (cont) All ARM’s 16 registers can be a register direct operand. These registers can be either a source or destination operand. MOV R3,LR ;make copy of LR in R3 R0 R1 R2 MOVS R0,R0 ;test for N or Z condition in R0 R3 R4 R5 MOV PC,R1 ;make a jump to address in R1 R6 R7 R8 R9 R10 R11 R12 SP R13 LR R14 PC R15 11 Immediate Addresing Operand is directly specified within the instruction itself. “#” symbol precedes the immediate value. #3 Example: MOV R1,#3 Immediate Value Copy operation After execution, the immediate value is copied into the destination register (left operand). R1 0x12345678 Immediate addressing can only be used as a source operand. Before execution Used for loading constant values into registers. Values must be known at the time of coding R1 0x12345678 00000003 (e.g. load loop count into a loop counter register). Before execution After execution 12 (c) A/P Goh Wooi Boon - 2020 6 Chap 4 - Addressing Modes CE/CZ1106 Immediate Addressing (cont) How is the 32-bit immediate value encoded? The immediate value is specified within the instruction bit pattern itself. 20 bits 12 bits ARM Op-code Operands Immediate Operand Instruction 32 bits Bit 11 8 7 0 Format of 12-bit Rotate Right 8-bit Immediate Immediate Operand (0, 2,..30 bits) (0..255) How can a 12-bit operand encode a 32-bit immediate value? It can only describe a subset of all 232 possible values. Immediate value is a number between (0..255) rotated right by 2n bits, where the value of n is given by 4 bits (0  n  15). 13 Immediate Addressing (cont) Assembler does the necessary calculations and gives warning if requested immediate value cannot be encoded. MOV R3,#0xFF ;immediate values within 8 bits always valid MOV R0,#0x100 ;right rotate 8-bit value of 0x01 with n=12 MOV R1,#0x102 ;this is not a valid immediate value Bit 11 1 0 2 Bit 0 MOV R1,#0x100 ; load 0x100 to R1 A combination 0 0 0 of 1 instructions 0 0 0 0 can0 be 0 1 0 ADD R1,R1,#2 ; add 2 to R1 used to achieved the desired 0x81immediate values that is not valid. 1 bit only (right rotate are in 2n bits) 14 (c) A/P Goh Wooi Boon - 2020 7 Chap 4 - Addressing Modes CE/CZ1106 Summary Register direct is efficient as its execution involves no access to memory. Immediate addressing encode the operand within the instruction. Like register direct, immediate addressing in the ARM is efficient as memory access is not incurred during execution, only when fetching the instruction. Because data is encoded within fixed-length instruction, only a subset of immediate values are available. Immediate addressing is used when the operand value is known during the time of coding (e.g. loading known constants into registers). 15 16 (c) A/P Goh Wooi Boon - 2020 8 Chap 4 - Addressing Modes CE/CZ1106 Chapter 4 Addressing Modes Register Indirect with Base Register Learning Objectives (4.3) 1. Describe what is register indirect and the ARM instructions that support this addressing mode. 2. Describe the variants and application of register indirect that uses base plus offset and index register. 3. Compare the relative pros and cons of register direct and register indirect addressing modes. 17 Limitation of Register Direct and Immediate Addressing Register direct and immediate addressing do not allow CPU to access operands stored in memory. C variables are usually allocated memory for storage (especially large arrays). How do you specific a 32-bit address in memory using a 32-bit long instruction? The ARM specifies the 32-bit address of the operand in a 32-bit register. The register with the memory address points to the memory location where the operand is stored. Memory operand is fetched during instruction execution using register indirect addressing. The ARM uses the LDR and STR mnemonics to access memory operands. 18 (c) A/P Goh Wooi Boon - 2020 9 Chap 4 - Addressing Modes CE/CZ1106 The LDR Instruction The LDR operator is used to copy memory content to a register. The left operand the destination register. The right source operand is a memory location R0 0x00000100 100 whose address is contained in a register (register indirect addressing). R1 0x12345678 Copy operation Address Memory Before execution LDR R1,[R0] 0x100 0xDD 0x101 0xCC R0 0x00000100 Destination Source 0x102 0xBB (Register) (Memory) 0x103 0xAA R1 0x12345678 AABBCCDD Address in Register 0x104 : Before execution After execution 19 The STR Instruction The STR operator is used to copy register content to memory. The left operand is always a source register. The right destination operand is a memory R0 0x00000100 location whose address is contained in the indirect register. R1 0x12345678 Copy operation Address Memory Before execution STR R1,[R0] 0x100 0x100 0xDD 0x78 0x101 0xCC 0x56 R0 0x00000100 Source Destination 0x102 0xBB 0x34 (Register) (Memory) 0x103 0xAA 0x12 R1 0x12345678 12345678 Address in Register 0x104 : Before execution After execution 20 (c) A/P Goh Wooi Boon - 2020 10 Chap 4 - Addressing Modes CE/CZ1106 Data Alignment Constraints Access of 32-bit operand from memory must follow data alignment constraints. The 4-byte data read or written to memory must start at an address that is a multiple of 4. The effects of an unaligned memory access depend on the ARM architecture but they invariably result in performance degradation. LDR R1,[R0]  Address Memory 0x100 0x01  0x101 0x23 R0 102 0x00000100 104 0x102 0x45 0x103 0x67 R1 0x12345678  0x104 0x89 Before execution : : 21 Register Indirect with Offset Adds a specific offset value to the indirect register to compute the effective address (EA) in memory. Base Plus Offset addressing does not change indirect register’s content. Offset value allows required BA element in an array to be Address Memory retrieved with respect to its BA 0x100 0x00 R0 0x00000100 base address (BA) in R0. 0x101 0x00 i 0x102 0x00 R1 0x12345678 + 0x103 0x03 0x104 0xDD Before execution LDR R1,[R0,#4] 0x105 0xCC i 0x106 0xBB R0 0x00000100 0x107 0xAA 0x108 : R1 0x12345678 AABBCCDD Destination Source (Register) (Memory) Integer Array Before execution After execution 22 (c) A/P Goh Wooi Boon - 2020 11 Chap 4 - Addressing Modes CE/CZ1106 Program Example Accessing Array Elements Use base plus offset to access array element whose index is known during coding time. main() MOV R2,#0x100 1 { MOV R1,#7 2 // assume base address // of array i is 0x100 STR R1,[R2,#0] 3 int i; STR R1,[R2,#16] i=7; i=7; Using register indirect with base plus offset } 1 Initialize base address of array i into register R2. C program example 2 Load value of 7 into register R1. Assign first & last elements 3 Store the value of 7 into i and i using offsets of 0 and 16 of of array i with value of 7. register R2 respectively. In computing offset, note that each integer element occupies 4 bytes in memory. 23 Register Indirect with Index Register This variant adds the content of the index register to the indirect register to compute EA. Base Plus Index Register does not change base register’s content. BA Modifiable index value in R2 allow different array elements Address Memory R0 0x00000100 to be retrieved with respect to BA 0x100 0x00 base address (BA) during 0x101 0x00 i R1 0x12345678 0x102 0x00 program execution. 0x03 R2 0x00000004 0x103 + 0x104 0xDD Before execution 0x105 0xCC i LDR R1,[R0,R2] 0x106 0xBB 0x107 0xAA R0 0x00000100 0x108 : Destination Source R1 0x12345678 AABBCCDD (Register) (Memory) Integer Array Before execution After execution 24 (c) A/P Goh Wooi Boon - 2020 12 Chap 4 - Addressing Modes CE/CZ1106 Program Example Clearing All Array Elements Use base plus index register to access each array element in turn. MOV R2,#0x100 1 main() { MOV R0,#0 2 // assume base address MOV R1,#0 // of array i is 0x100 : loop int i; STR R0,[R2,R1] 3 back int n=0; 3 ×400 = 1200 cycles 399 ADD R1,R1,#4 4 while (n < 400) { times i[n] = 0; n = n + 1; Using register indirect with base plus index } 1 Initialize base address of array i into register R2. } 2 Load value of 0 into register R0 and R1(index register). C program example 3 Store 0 in R0 into i[n] using current index value in R1 plus base Initialise all 400 elements in address in R2. array i with zero. 4 Increment index by 4, the size of each integer element in array. 25 Summary Register indirect (with the LDR and STR operators) allows memory operands to be accessed. There are two variants of register indirect using base register. Register indirect with offset (base plus offset) Register indirect with index (base plus index register) Contents in base register do not change after execution. Given the base address of an array, register indirect with base addressing is useful for accessing the contents of the array. Use base plus offset if position of array element is known during coding time Use base plus index if array element position is computed during run time. 26 (c) A/P Goh Wooi Boon - 2020 13 Chap 4 - Addressing Modes CE/CZ1106 Chapter 4 Addressing Modes Register Indirect with Autoindexing and Stacks Learning Objectives (4.4) 1. Describe what is autoindexing feature of ARM’s register indirect addressing mode. 2. Describe the differences between pre-index and post-index addressing modes. 3. Describe the various stack implementations and operations using the ARM addressing modes. 27 Register Indirect with Autoindexing Recap – Register indirect with base register: The base address in the indirect register can be added with an offset or the contents of index register to compute effective address of operand in memory. Base address is never modified after execution as it is assumed to be the sole reference to the start of the array. What if we allow the indirect register to be modified before Effective or after address of computing the effective address? + operand in memory Keep a copy of the LDR array’s R0base address R1,[R0,#4] Baseelsewhere. plus offset Autoindexing allows the indirect register’s content to be modified during execution.LDR R1,[R0,R2]R0 Base plus index register Autoindexing provides an efficient way to access consecutive array elements. 28 (c) A/P Goh Wooi Boon - 2020 14 Chap 4 - Addressing Modes CE/CZ1106 Offset with Autoindexing Adds offset value to the autoindex register (AR) to compute effective address (EA) and AR gets modified. “!” in mnemonic causes autoindex register to be modified with the EA. Offset value added to Autoindex autoindex register R0 to Address Memory compute the EA in 0x100 0x00 memory. R0 takes on R0 0x00000100 0x101 0x00 i EA value after 0x102 0x00 R1 0x12345678 execution. + 0x103 0x03 EA 0x104 0xDD Before execution R0 ! LDR R1,[R0,#4]! 0x105 0xCC i 0x106 0xBB R0 0x00000100 0x00000104 0x107 0xAA 0x108 : R1 0x12345678 AABBCCDD Destination Source (Register) (Memory) Integer Array Before execution After execution 29 Program Example (Optimised Version) Clearing All Array Elements Use offset with autoindex to efficiently access each array element in turn. MOV R2,#0x100 1 main() { MOV MOV R0,#0 R1,#0 2 // assume base address MOV STR R1,#0 R1,[R2] 3 // of array i is 0x100 : 2 ×400 = 800 cycles loop int i; STR R0,[R2,R1] 4 back R1,[R2,#4]! int n=0; 398 399 ADD R1,R1,#4 while (n < 400) { times i[n] = 0; n = n + 1; Using register indirect with plus base offsetplus withindex autoindex (previous) } 1 Initialize base address of array i into register R2. } 2 Load value of 0 into source register R1. C program example 3 Store 0 in R1 into first element of array i. Initialise all 400 elements in Store 0 in R1 into i[n] using current effective address (EA) of array i with zero. 4 autoindex register R2 plus offset 4. Then put this EA into R2. 30 (c) A/P Goh Wooi Boon - 2020 15 Chap 4 - Addressing Modes CE/CZ1106 Index Register with Autoindex Adds index register value to autoindex register (AR) to compute effective address (EA) and AR gets modified. Use “!” in mnemonic to update autoindex register with EA value. Autoindex Index value (-8) in R2 added to autoindex register R0 to Address Memory R0 0x00000108 compute next EA in memory. EA 0x100 0x00 R0 takes on EA value after 0x101 0x00 i R1 0x12345678 0x102 0x00 execution. 0x03 R2 0xFFFFFFF8 0x103 + 0x104 0xDD Before execution 0x105 0xCC i R0 LDR R1,[R0,R2]! 0x106 0xBB 0x107 0xAA R0 0x00000108 0x00000100 0x108 : Destination Source R1 0x12345678 03000000 (Register) (Memory) Integer Array Before execution After execution 31 Pre-index and Post-index In pre-index, the indirect register is autoindex before being used to compute effective address. LDR R1,[R0,#4]! ; R0 = R0+4 LDR R1,[R0,R2]! ; R0 = R0+R2 ; R1 = mem[R0] ; R1 = mem[R0] Offset with Autoindexing (pre-index) Index with Autoindexing (pre-index) In post-index, the indirect register is used to compute the effective address before it is autoindexed. LDR R1,[R0],#4 ; R1 = mem[R0] LDR R1,[R0],R2 ; R1 = mem[R0] ; R0 = R0+4 ; R0 = R0+R2 Offset with Autoindexing (post-index) Index with Autoindexing (post-index) 32 (c) A/P Goh Wooi Boon - 2020 16 Chap 4 - Addressing Modes CE/CZ1106 Program Example (Alternative Version) Clearing All Array Elements Use offset with post-index autoindex to keep all array access within loop. MOV R2,#0x100 1 main() { MOV R1,#0 2 // assume base address STR R1, // of array i is 0x100 : loop int i; R0,[R2,#4]! STR R1,[R2],#4 3 2 ×400 = 800 cycles back int n=0; 398 399 while (n < 400) { times i[n] = 0; n = n + 1; Using offset with post-index autoindexing(previous) pre-index autoindexing } 1 Initialize base address of array i into register R2. } 2 Load value of 0 into source register R1. C program example 3 Store 0 in R1 into i[n] using current effective address (EA) in Initialise all 400 elements in indirect register R2. Then add offset 4 to the current EA in R2 so array i with zero. that R2 is now pointing to the next array element. 33 The System Stack A stack is a first-in, last-out linear data structure that is maintained in the memory’s data area. The system stack in the ARM is maintained Full Descending (FD) Stack by a dedicated stack pointer (SP) or R13. 0xFE000008 SP 0xFE00000C 0xFE000004 The FD stack grows towards lower memory 0x00000000 addresses. (e.g. by default, SP starts at 0xFF000000 in VisUAL ARM simulator). Stack grows In the FD stack, the SP points to the top towards lower item (full) on the stack (but SP can also point SP 0xFE000004 Item #n (top) address to the next empty space on the stack). SP 0xFE000008 Item #n-1 The 3 basic stack operations are push, pop SP 0xFE00000C System and access items on the stack. stack 0xFF000000 Stack Learn More: of warm Google “ARMplates on dispenser stack implementation” Memory map 34 (c) A/P Goh Wooi Boon - 2020 17 Chap 4 - Addressing Modes CE/CZ1106 ARM Stack Implementation (FD) The are 4 possible stack implementations supported by the ARM instruction set. Full Descending, Full Ascending, Empty Descending and Empty Ascending Example of Full Descending (FD) stack implementation: Access top item on stack Push R1 to stack Pop stack into R2 0xFE000003 Grow SP 0x88 0x55 SP 0x88 towards 0xFE000004 0x77 0x66 0x77 lower 0xFE000005 memory 0xFE000006 0x66 0x77 0x66 address 0x55 0x88 0x55 0xFE000007 0x44 SP 0x44 SP 0x44 SP 0xFE000008 0x33 Little 0x33 0x33 0xFE000009 0x22 Endian 0x22 0x22 0xFE00000A 0xFE00000B 0x11 format 0x11 0x11 0xFE00000C LDR R0,[R13] STR R1,[R13,#-4]! LDR R2,[R13],#4 R0 0x00000000 0x11223344 R1 0x55667788 0x00000000 R2 0x55667788 After execution Before execution Before execution After execution Before execution 35 Empty Ascending Implementation (EA) EA is an alternative stack implementation. Empty means SP points to an available unoccupied stack space. Ascending means stack grows toward higher memory address. Access top item on stack Push R1 to stack Pop stack into R2 0xFE000003 0x44 0x44 0x44 0xFE000004 0x33 0x33 0x33 0xFE000005 0x22 0x22 0x22 0xFE000006 0x11 0x11 0x11 0xFE000007 0x88 SP 0x88 SP 0xFE000008 0x77 0x77 0xFE000009 Grow 0x66 0x66 0xFE00000A towards 0x55 0x55 0xFE00000B higher SP 0xFE00000C memory address LDR R2,[R13,#-4]! LDR R0,[R13,#-4] R2 0x55667788 R0 0x11223344 STR R1,[R13],#4 After execution After execution R1 0x55667788 After execution 36 (c) A/P Goh Wooi Boon - 2020 18 Chap 4 - Addressing Modes CE/CZ1106 Summary Autoindexing modifies the indirect register besides just computing the effective address. The autoindexing can use either offset or index register. Pre-index does the autoindexing first before computing the effective address. Post-index computes the effective address first, then does the autoindexing. ARM’s autoindexing feature can be used to implement stacks. There are 4 possible stack implementations (FD, FA, ED, EA). For a given stack implementation, the Push and Pop operation must complement each other to ensure the stack grows and collapses correctly. 37 38 (c) A/P Goh Wooi Boon - 2020 19 Chap 4 - Addressing Modes CE/CZ1106 Chapter 4 Addressing Modes PC-related Addressing Modes Learning Objectives (4.5) 1. Describe difference between absolute & relative jump. 2. Describe the concept of position-independent code and how it is achieved. 3. Describe how data can be accessed using PC relative addressing 39 Absolute Jump A new address can be loaded into the PC to alter the sequential order of program execution. An absolute jump to a new code position is done by loading the address to jump to into the PC. Example: MOV PC,#0x060 ;Jump to CodeB Address Absolute Jump 0x050 0x060 MOV PC,#0x060 Skip execution 0x054 CodeA MOV R0,R1 : : of CodeA 0x060 CodeB MOV R0,R2 segment : Absolute jump is not position-independent. This code can only execute correctly in this specific area of code memory. 40 (c) A/P Goh Wooi Boon - 2020 20 Chap 4 - Addressing Modes CE/CZ1106 Relative Jump An offset can be added to the PC to alter the sequential order of program execution. A relative jump is done using the branch instruction (e.g. B) with an appropriate signed offset. (Note: the range of this offset in ARM is +/- 32 Mbytes). Example: B CodeB ;Jump to CodeB AddressRelative Jump Offset of 0x008 is 0x050 B CodeB Skip added since PC has 0x054 CodeA MOV R0,R1 incremented by 8 execution : : during instruction 0x060 CodeB MOV R0,R2 of CodeA execution. segment : Relative jump supports Note: In the ARM processor the PC points 8 position-independent code. bytes ahead of the current executed instruction due to its pipeline architecture. 41 Position-Independent Code Such programs can be loaded anywhere in memory and still execute correctly (i.e. relocatable). Address Address 0x00F offset don’t change with code relocation Original Position Original Position 0x040 PROG 0x040 PROG 0x050 MOV PC,#0x060 0x050 B 0x008 0x060 CodeB 0x060 CodeB 0x090 PROG 0x090 PROG Shifted code Shifted code 0x0A0 MOV PC,#0x060 0x0A0 B 0x008 0x0B0 CodeB 0x0B0 CodeB Does not jump to CodeB after B still branch to CodeB after PROG is shifted to 0x090 PROG is shifted to 0x090 42 (c) A/P Goh Wooi Boon - 2020 21 Chap 4 - Addressing Modes CE/CZ1106 ADD Instruction (Introduction) This instruction does the addition operation. The 3-operand ADD instruction adds 2 source operands and puts result into a 3rd destination operand. The right and middle operands are added and R0 0x00000003 the result is placed in the destination register. R1 0x00000006 ADD R2,R0,R1 R2 0x00000000 Before execution Destination + R0 0x00000003 Destination and middle operands must be registers R1 0x00000006 but rightmost operand can be a register or an 0x00000009 R2 0x00000000 immediate value. Before execution After execution 43 Accessing Data Position-independent (P-I) programs require data to be accessed relative to the PC. PC-relative addressing is used to access variables in the data segment of program in memory. E.g.: ADD R0,PC,#0x0F8 ;Get P-I address of Var1 in Data Seg into R0 PC-relative offset of 0x0F8 is added Address PC-Relative Addressing since PC has incremented by 8 when 0x000 Get PC-relative address of Var1 ADD R0,PC,#0x0F8 0x004 Code executing ADD instruction. LDR R1,[R0] ;copy Var1 into R1 Segment : : PC-relative Offset: 0x100 Var1 Var address – (PC value + 8) 0x104 Var2 Data : Segment Referencing absolute address of variable in whatever ways will Note: In the ARM processor the PC points 8 violate P-I requirements. bytes ahead of the current executed instruction. 44 (c) A/P Goh Wooi Boon - 2020 22 Chap 4 - Addressing Modes CE/CZ1106 Summary Non-sequential execution of code can be achieved by modifying the PC contents directly. The Branch instruction does this by adding a signed offset. Such relative jumps create position-independent code. PC-relative addressing with appropriate offsets allows memory data to be accessed in a position-independent manner. 45 (c) A/P Goh Wooi Boon - 2020 23