ALU and Control Unit PDF

ALU, Data Path and Control Unit Memory ALU Registers R1R1+1 CLR 1 Timing signal, control signal 2 LOAD INC 3 Flags...

ALU, Data Path and Control Unit Memory ALU Registers R1R1+1 CLR 1 Timing signal, control signal 2 LOAD INC 3 Flags 4 Connection 5.. F D E  AD S0 S1 A3 B3 C3 D3 A2 B2 C2 D2 A1 B1 C1 D1 A0 B0 C0 D0 LOAD LOAD LOAD LOAD A3 A2 A1 A0 B3 B2 B1 B0 C3 C2 C1 C0 D3 D2 D1 D0 A B C D Memory: 4096 X 16 Registers: DR: 16 1100101010111111 AR: 12 0000101010111111 AC: 16 IR: 16 1100101010101010 PC: 12 TR  S2 BUS S1 S0 Memory 7 4096 X 16 Address W R AR < 1 LD INR CLR PC < 2 LD INR CLR DR < 3 LD INR CLR AC < 4 ALU Clock signal LD INR CLR INPR IR < 5 LD TR 6 < LD INR CLR OUTR < LD ARPC IRM[AR] PCPC+1 Decoder 4 X 16 SC (4-bit) ^ CLR INC CLK ID CLG TC Instruction Cycle 1. Fetch 2. Decode 3. Compute Effective Address Direct (0) – No computation Indirect (1) - Computation Needed 4. Execute T0 T7  Fetch T0: ARPC T1: IRM[AR] PC PC+1 T0 S2 T S1 BUS S0 AR 1 LD PC 2  Operation I=0 I=1 AND 0XXX 8XXX Decode ADD 1XXX 9XXX LDA 2XXX AXXX 1. Fetch: T0, T1 STA 3XXX BXXX 2. Decode: T2 – IR (14,13,12); ARIR(11…0);IIR(15) BUN 4XXX CXXX Opcode BSA 5XXX DXXX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ISZ 6XXX EXXX I Operand D6…D0 : Memory Reference Operation I/O Operation R Decoder D7: I (0) : Register INP F800 CLA 7800 3X8 I (1): I/O OUT F400 CLE 7400 SKI F200 CMA 7200 SKO F100 CME 7100 D7 D6 D5 D4 D3 D2 D1 D0 ION F080 CIR 7080 STA: Store AC BUN: Branch Unconditionally IOF F040 CIL 7040 BSA: Branch and Save Return Address ISZ: Increment and Skip if Zero INC 7020 CLA: Clear AC CLE: Clear E(overflow bit) SPA 7010 INP: Input character to AC CMA: Complement AC OUT: Input character to AC CME: Complement E SNA 7008 SKI: Input character to AC CIR: Circulate right AC and E SZA 7004 SKO: Skip on output flag CIL: Circulate left AC and E ION: Interrupt On INC: Circulate left AC and E SZE 7002 IOF: Interrupt Off SPA: Skip next instruction if AC > 0 SNA: Skip next instruction if AC < 0 HLT 7001 SZA: Skip next instruction if AC = 0 SZE: Skip next instruction if E = 0 Decode 1. Fetch: T0, T1 2. Decode: T2 – IR (14,13,12); ARIR(11…0);IIR(15) D6…D0 : Memory Reference Compute D7: I (0) : Register I (1): I/O 1. ~(D7).I.T3: ARM[AR] 2. ~(D7).~(I).T3: Nothing 3. D7.I.T3: Execute the I/O instruction 4. D7. ~(I).T3: Execute I M Instructions M D R I/O  Operation I=0 I=1 1. T4.D0: DRM[AR] AND 0XXX 8XXX 2. T5.D0:ACDR^AC, SC0 ADD 1XXX 9XXX LDA 2XXX AXXX STA 3XXX BXXX 1. T4.D1: DRM[AR] BUN 4XXX CXXX 2. T5.D1: ACDR^AC, ECout,SC0 BSA 5XXX DXXX ISZ 6XXX EXXX 1. T4.D2: DRM[AR] STA: Store AC BUN: Branch Unconditionally 2. T5.D2: ACDR, SC0 BSA: Branch and Save Return Address ISZ: Increment and Skip if Zero 1. T4.D3: M[AR]AC, SC0 1. T4.D4: PCAR, SC0 1. T4.D5: M[AR] PC, ARAR+1 2. T5.D5: PCAR, SC0 1. T4.D6: DRM[AR] 2. T5.D6: DRDR+1 3. T6.D6:M[AR]DR; (if DR==0), PCPC+1, SC0  Operation R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLA 7800 I 1 1 1 Operand CLE 7400 CMA 7200 CME 7100 CIR 7080 D7.~(I).T3.b11 CIL 7040 INC 7020 T0,T1 ; T2 ; T3 SPA 7010 SNA 7008 SZA 7004 SZE 7002 HLT 7001 CLA: Clear AC CLE: Clear E(overflow bit) CMA: Complement AC CME: Complement E CIR: Circulate right AC and E CIL: Circulate left AC and E INC: Circulate left AC and E SPA: Skip next instruction if AC > 0 SNA: Skip next instruction if AC < 0 SZA: Skip next instruction if AC = 0 SZE: Skip next instruction if E = 0  Operation I/O INP F800 ACINPR; FGI0 OUT F400 OUTRAC; FGO0 SKI F200 SKO F100 If (FGI==1), PCPC+1 ION F080 If (FGO==1), PCPC+1 IOF F040 INT1 FGI; FGO INT0 INP: Input character to AC OUT: Input character to AC SKI: Skip on input flag SKO: Skip on output flag ION: Interrupt On IOF: Interrupt Off